JPS6329294Y2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a muting circuit that reduces offset due to on/off of a muting transistor.

Conventionally, a muting circuit as shown in FIG. 1 has been used. In Fig. 1, 1 is a signal input terminal, 2 is an amplifier, 3 and 4 are coupling capacitors, 5 is an output terminal, 6 is a control terminal to which a muting control signal is input, 7 is a muting transistor, 8 and 9 are It is resistance. In addition,
In FIG. 1, the DC potential is separated by coupling capacitors 3 and 4, and the signal transmission path consisting of the connection point between resistor 8 and the emitter of transistor 7 is brought to ground potential by resistor 8.

Now, when an H level signal is input to the control terminal 6, the transistor 7 is turned on, and the signal transmitted through the signal transmission line is grounded to prevent the signal from appearing at the output terminal 5. Conversely, when an L level signal is input to the control terminal 6, the transistor 7 is turned off and the signal applied to the input terminal 1 is transmitted to the output terminal 5.

Here, focusing on the transistor 7, the emitter potential when it is off is zero potential as shown in FIG. 3 because it is grounded through the resistor 8, but when it is on, there is normally a voltage of 1 between the collector and emitter. ~
Since a saturation voltage of about 5 mV is generated, the emitter potential rises from zero potential by the saturation voltage. Therefore, the change in emitter potential caused by turning on and off the transistor 7 is differentiated by the coupling capacitor 4, and a click waveform as shown in FIG. 3 appears at the output terminal 5. The amplitude V _DC of this waveform is the saturation voltage between the collector and emitter of the transistor,
It is expressed by equation (1) using the well-known Evers-Mole equation.

V _DC =kT/qln1+h _RE /h _RE …(1) where k is Boltzmann constant, T is absolute temperature, q
is the electron charge and _hRE is the reverse current amplification factor. In Figure 1, the configuration is such that the base current flows from the base to the collector, that is, the emitter and collector are interchanged with the normal case, and h _RE in this case is the forward current increase rate in the normal case. is applicable. Therefore, when formula (1) is calculated with h _RE = 100, V _DC is 0.26 mV. Note that when the base current flows from the base to the emitter as is commonly used, that is, when the emitter and collector are swapped in the case of Figure 1, V _DC is calculated from equation (1) with h _RE = 1. ,
The voltage will be approximately 18mV.

From the above, the reverse connection as shown in Figure 1 is superior in that V _DC is small and the noise level is low.
Furthermore, as mentioned above, there is a problem in that an amplitude of 0.26 mV is generated and this is heard as noise.

The present invention provides a muting circuit that solves these problems with an extremely simple configuration.

An embodiment of the present invention will be described below with reference to FIG. In FIG. 2, parts having the same functions as those in FIG. 1 are denoted by the same reference numerals, and explanations thereof will be omitted. 10
is a second transistor whose emitter is connected to the signal transmission path via a resistor 8 and whose collector is grounded;
11 is a second transistor 10 via a resistor 12
A second control terminal connected to the base of the. Note that the first and second transistors 7 and 10 are transistors having the same characteristics.

In FIG. 2, the first transistor 7
It is turned on and off according to the control signal applied to the control terminal 6 of the control terminal 6, and the signal on the signal transmission line is turned on and off in the same manner as in FIG.

Here, if the second transistor 10 is always turned on by applying an H level signal to the second control terminal 11, when the first transistor 7 is off, the emitter of the first transistor 7 is turned on. The potential becomes equal to the saturation voltage of the second transistor 10. On the other hand, considering the case where the first transistor 7 is turned on, the emitter potential of the first transistor 7 becomes the saturation voltage. Therefore, if transistors with the same characteristics are used as the first and second transistors 7 and 10, their saturation voltages will be the same, and the emitter potential will not change when the first transistor 7 is turned on or off. . Therefore, output terminal 5
In this case, the click waveform shown in FIG. 3 does not occur, and the shock noise can be reduced.

Note that in the above embodiment, the second transistor 10
is always on, but the second transistor 10 may be turned on only when the first transistor 7 is off.

As described above, according to the present invention, by simply adding one transistor, it is possible to reduce the offset based on the on/off state of the muting transistor and reduce the click noise.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of a conventional example, FIG. 2 is a circuit diagram of an embodiment of the present invention, and FIG. 3 is a waveform diagram for explaining the reason why the clicking sound occurs in FIG. 1. 1...Input terminal, 2...Amplifier, 3, 4...Coupling capacitor, 5...Output terminal, 6,1
1... Control terminal, 7... First transistor,
8, 9, 12...Resistor, 10...Second transistor.

Claims (1)

[Scope of utility model registration request] A first transistor having an emitter and a collector connected between a signal transmission path from which DC potential is separated and ground, and mutating a signal transmitted through the signal transmission path by interrupting a base current; a second transistor connected to the signal transmission path via the signal transmission line and having a collector grounded, the muting circuit turning on and off the first transistor while the second transistor is turned on.