JPH036036Y2 - - Google Patents

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Publication number
JPH036036Y2
JPH036036Y2 JP1981104926U JP10492681U JPH036036Y2 JP H036036 Y2 JPH036036 Y2 JP H036036Y2 JP 1981104926 U JP1981104926 U JP 1981104926U JP 10492681 U JP10492681 U JP 10492681U JP H036036 Y2 JPH036036 Y2 JP H036036Y2
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JP
Japan
Prior art keywords
circuit
voltage
mos
resistor
power supply
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP1981104926U
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Japanese (ja)
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JPS5811337U (en
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP10492681U priority Critical patent/JPS5811337U/en
Publication of JPS5811337U publication Critical patent/JPS5811337U/en
Application granted granted Critical
Publication of JPH036036Y2 publication Critical patent/JPH036036Y2/ja
Granted legal-status Critical Current

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Description

【考案の詳細な説明】 本考案はC−MOS用電源回路の改良に関する。[Detailed explanation of the idea] The present invention relates to improvement of a C-MOS power supply circuit.

接点の動作信号を読出すデイジタル回路にあつ
ては、ノイズマージンを大きくとり、かつ接点へ
の供給電流をある程度大きくする必要から24Vの
直流電源が多用されている。しかし、24Vの直流
電源ではC−MOS回路に直接適用できないので、
24V直流電圧を電圧降下する等の工夫を施してC
−MOS回路に適用している。第1図および第2
図はそれぞれ従来のC−MOS用電源回路を示し、
第1図は回路供給電圧Vaを抵抗1にて電圧降下
した後、ツエナーダイオード2により一定電圧の
C−MOS用電源電圧Vbを得る構成である。次
に、第2図は回路供給電圧Vaの変動を抵抗3を
介してトランジスタ4で吸収し一定電圧のC−
MOS用電源電圧を得る構成である。5は基準電
圧用ダイオードである。そして、第3図に示すC
−MOSICにおいて図示一点鎖線のブロツク部分
6に第1図又は第2図のC−MOS用電源回路が
適用される。なお、第3図において7は信号入力
端子、8〜10は第1の抵抗分圧回路を構成する
抵抗、11はフイルタ用コンデンサ、12はC−
MOSゲートである。
In digital circuits that read out operating signals from contacts, a 24V DC power supply is often used because it is necessary to have a large noise margin and to increase the current supplied to the contacts to some extent. However, since a 24V DC power supply cannot be directly applied to a C-MOS circuit,
C by taking measures such as reducing the 24V DC voltage.
-Applied to MOS circuits. Figures 1 and 2
Each figure shows a conventional C-MOS power supply circuit.
FIG. 1 shows a configuration in which a circuit supply voltage Va is dropped by a resistor 1, and then a constant voltage C-MOS power supply voltage Vb is obtained by a Zener diode 2. Next, in FIG. 2, fluctuations in the circuit supply voltage Va are absorbed by a transistor 4 through a resistor 3, and a constant voltage C-
This is the configuration to obtain the power supply voltage for MOS. 5 is a reference voltage diode. Then, C shown in FIG.
- In the MOSIC, the C-MOS power supply circuit shown in FIG. 1 or 2 is applied to the block portion 6 indicated by the dashed line shown in the figure. In FIG. 3, 7 is a signal input terminal, 8 to 10 are resistors constituting the first resistance voltage divider circuit, 11 is a filter capacitor, and 12 is a C-
It is a MOS gate.

ところで、第1図および第2図の回路では、回
路供給電圧Vaに誤差があり、或いは回路供給電
圧Va自体に変動があつてもツエナーダイオード
2又はトランジスタ4により一定のC−MOS電
源電圧Vbを得ることができるが、上記回路を第
3図のような回路に適用したときには逆に欠点と
なる。つまり、第3図のように入力側に分圧抵抗
8〜10を有しこれらの抵抗8〜10で回路供給
電圧Vaを分圧するものでは、回路供給電圧Vaの
誤差や変動がそのまま抵抗8〜10で分圧されて
C−MOSゲート12に入力されるが、このとき
Vb自体は定電圧化されているので、C−MOSゲ
ート12の入力電圧がC−MOS電源電圧Vbより
も高くなつてしまうことがある。そこで、従来の
回路はC−MOSゲート入力電圧がC−MOS電源
電圧Vbよりも高くならないように図示点線で示
す保護用ダイオード13を設ける必要がある。ま
た、C−MOS用電源電圧Vaが大きく変動した際
にC−MOSゲート入力電圧が変動するが、C−
MOSゲート12のスレツシユホールドレベルが
一定となつているため、入力電圧がスレツシユホ
ールドレベルに近づくと、出力が不安定となる欠
点がある。
By the way, in the circuits shown in FIGS. 1 and 2, even if there is an error in the circuit supply voltage Va, or even if the circuit supply voltage Va itself fluctuates, a constant C-MOS power supply voltage Vb can be maintained by the Zener diode 2 or the transistor 4. However, when the above circuit is applied to a circuit as shown in FIG. 3, it becomes a drawback. In other words, in a device that has voltage dividing resistors 8 to 10 on the input side and divides the circuit supply voltage Va by these resistors 8 to 10 as shown in Fig. 3, errors and fluctuations in the circuit supply voltage Va are directly transmitted to the resistors 8 to 10. The voltage is divided by 10 and input to the C-MOS gate 12, but at this time
Since Vb itself is a constant voltage, the input voltage of the C-MOS gate 12 may become higher than the C-MOS power supply voltage Vb. Therefore, in the conventional circuit, it is necessary to provide a protection diode 13 shown by a dotted line in the figure so that the C-MOS gate input voltage does not become higher than the C-MOS power supply voltage Vb. Also, when the C-MOS power supply voltage Va fluctuates greatly, the C-MOS gate input voltage fluctuates;
Since the threshold level of the MOS gate 12 is constant, there is a drawback that when the input voltage approaches the threshold level, the output becomes unstable.

本考案は上記実情にかんがみてなされたもの
で、その目的とするところは、C−MOS電源電
圧を、定電圧ではなく回路供給電圧を抵抗にて分
圧した電圧を用いることにより従来の欠点を除去
するC−MOS用電源回路を提供するものとする。
The present invention was developed in view of the above circumstances, and its purpose is to overcome the drawbacks of the conventional C-MOS power supply voltage by using a voltage obtained by dividing the circuit supply voltage using a resistor instead of a constant voltage. A C-MOS power supply circuit to be removed is provided.

以下、本考案の一実施例について第4図を参照
して説明する。この第4図の回路は、回路供給電
圧Vaを、トランジスタ21のコレクタ・ベース
間に挿入する分圧用抵抗22と他端を零電位に接
続した分圧用抵抗23とで分圧してトランジスタ
21のベースに供給し、同トランジスタ21のエ
ミツタ側よりC−MOS電源電圧Vbを取り出す構
成である。つまり、この回路は、第2の抵抗分圧
回路を構成する抵抗22,23による分圧手段を
とるとともに、トランジスタ21をエミツタホロ
ア形式とし低出力インピーダンスによりC−
MOS電源電圧Vbを得るようにしたC−MOS用
電源回路である。そして、第4図に示す回路は第
5図のC−MOS回路において図示一点鎖線のブ
ロツク部分24に適用される。なお、第5図の符
号は第3図と同一部分では同一符号を付してあ
る。
An embodiment of the present invention will be described below with reference to FIG. The circuit shown in FIG. 4 divides the circuit supply voltage Va by a voltage dividing resistor 22 inserted between the collector and base of the transistor 21 and a voltage dividing resistor 23 whose other end is connected to zero potential. The configuration is such that the C-MOS power supply voltage Vb is taken out from the emitter side of the transistor 21. In other words, this circuit takes voltage dividing means using the resistors 22 and 23 that constitute the second resistance voltage dividing circuit, and also uses the transistor 21 as an emitter follower type to achieve low output impedance.
This is a C-MOS power supply circuit designed to obtain a MOS power supply voltage Vb. The circuit shown in FIG. 4 is applied to the block portion 24 indicated by the dashed line in the C-MOS circuit shown in FIG. Note that the same reference numerals in FIG. 5 are given to the same parts as in FIG. 3.

次に、第4図および第5図を用いて本実施例の
作用について説明する。回路供給電圧Vaは、抵
抗22,23からなる第2の抵抗分圧回路で分圧
され、その分圧信号がエミツタホロワ接続のトラ
ンジスタ21で制御されてエミツタ側よりC−
MOS用電源電圧Vbとして取出される。この場
合、C−MOS用電源電圧Vbは第2の抵抗分圧回
路の分圧比によつて決定される。すなわち、回路
供給電圧Vaの変化に対して上記C−MOS用電源
電圧Vbの傾きは、抵抗22,23の抵抗値をR
22,R23とすると次の(1)式で現わされる。
Next, the operation of this embodiment will be explained using FIGS. 4 and 5. The circuit supply voltage Va is divided by a second resistance voltage divider circuit consisting of resistors 22 and 23, and the divided voltage signal is controlled by an emitter follower-connected transistor 21 and is applied from the emitter side to C-.
It is taken out as the MOS power supply voltage Vb. In this case, the C-MOS power supply voltage Vb is determined by the voltage division ratio of the second resistance voltage divider circuit. That is, the slope of the C-MOS power supply voltage Vb with respect to the change in the circuit supply voltage Va is such that the resistance value of the resistors 22 and 23 is
22, R23, it is expressed by the following equation (1).

Vbの傾き=R23/(R22+R23) ……(1) また、回路供給電圧Vaは、抵抗8〜10から
なる第1の抵抗分圧回路で分圧され、C−MOS
ゲート入力電圧VinとしてC−MOSゲート12
に入力される。この場合、C−MOSゲート入力
電圧Vinは第1の抵抗分圧回路の分圧比によつて
決定される。すなわち、回路供給電圧Vaの変化
に対して上記C−MOSゲート入力電圧Vinの傾
きは、抵抗8〜10の抵抗値をR8,R9,R1
0とすると次の(2)式で現わされる。
Slope of Vb = R23/(R22+R23) ...(1) Also, the circuit supply voltage Va is divided by the first resistor voltage divider circuit consisting of resistors 8 to 10, and the C-MOS
C-MOS gate 12 as gate input voltage Vin
is input. In this case, the C-MOS gate input voltage Vin is determined by the voltage division ratio of the first resistance voltage divider circuit. In other words, the slope of the C-MOS gate input voltage Vin with respect to the change in the circuit supply voltage Va changes the resistance values of the resistors 8 to 10 to R8, R9, R1.
If it is set to 0, it is expressed by the following equation (2).

Vinの傾き=R10/([R8+R9]+R10)……(2) 今、前記第(2)式で現わされる第1の抵抗分圧回
路の分圧比が前記第(1)式で現わされる第2の抵抗
分圧回路の分圧比よりも大きくならないように、
抵抗8〜10の抵抗値R8〜R10と抵抗22,
23の抵抗値R22,R23を設定したとする
と、回路供給電圧Vaの変化に対し、C−MOSゲ
ート入力電圧VinとC−MOS用電源電圧Vbの傾
きは、前記(1)式,(2)式によりそれぞれ第6図の
イ,ロのようになる。また、C−MOS用電源電
圧Vbの変化に応じて、スレツシユホールドレベ
ルも第6図ハのように変化する。なお、第6図に
おいてVbmaxはC−MOS最大電源電圧、Vboは
C−MOS動作電圧である。
Slope of Vin = R10/([R8+R9]+R10)...(2) Now, the voltage division ratio of the first resistor voltage divider circuit expressed by the above equation (2) is expressed by the above equation (1). so as not to become larger than the voltage division ratio of the second resistor voltage divider circuit.
Resistance values R8 to R10 of resistors 8 to 10 and resistor 22,
Assuming that the resistance values R22 and R23 of 23 are set, the slope of the C-MOS gate input voltage Vin and the C-MOS power supply voltage Vb with respect to the change in the circuit supply voltage Va is expressed by the above equations (1) and (2). Depending on the formula, the results will be as shown in A and B in Figure 6, respectively. Furthermore, in accordance with changes in the C-MOS power supply voltage Vb, the threshold level also changes as shown in FIG. 6C. In FIG. 6, Vbmax is the C-MOS maximum power supply voltage, and Vbo is the C-MOS operating voltage.

したがつて、第6図から明らかなように、第1
の抵抗分圧回路の分圧比が第2の抵抗分圧回路の
分圧比よりも大きくならないように各抵抗値を設
定することにより、回路供給電圧Vaが変動して
もC−MOSゲート入力電圧Vin(図示イ)が電源
電圧Vb(図示ロ)よりも高くなることはなくな
る。よつて、従来のように第3図に示す保護用ダ
イオード13を設ける必要がなくなる。しかも、
スレツシユホールドレベルも第6図ハのように変
化するので、回路供給電圧Vaの変動によつて不
安定な動作となることはない。
Therefore, as is clear from Figure 6, the first
By setting each resistance value so that the voltage division ratio of the second resistance voltage divider circuit is not larger than the voltage division ratio of the second resistance voltage divider circuit, the C-MOS gate input voltage Vin can be maintained even if the circuit supply voltage Va fluctuates. (A in the figure) will never become higher than the power supply voltage Vb (B in the figure). Therefore, there is no need to provide the protective diode 13 shown in FIG. 3 as in the conventional case. Moreover,
Since the threshold level also changes as shown in FIG. 6C, fluctuations in the circuit supply voltage Va will not cause unstable operation.

また、回路供給電圧Vaを抵抗22,23で分
圧し、その分圧信号でエミツタホロワ接続のトラ
ンジスタ21を制御してエミツタ側よりC−
MOS電源電圧Vbを得ており、抵抗22,23に
よる分圧手段をとつているためエミツタ側に現わ
れるC−MOS用電源電圧Vbの誤差は小さくな
る。
In addition, the circuit supply voltage Va is divided by resistors 22 and 23, and the divided voltage signal controls the emitter follower connected transistor 21 so that the C-
Since the MOS power supply voltage Vb is obtained and a voltage dividing means is provided using resistors 22 and 23, the error in the C-MOS power supply voltage Vb appearing on the emitter side is reduced.

以上詳記したように本考案によれば、回路供給
電圧とC−MOS用電源電圧との間に、回路供給
電圧を分圧する抵抗分圧回路と、この抵抗分圧回
路の分圧信号を受けて動作制御するエミツタホロ
ア接続のトランジスタとからなるC−MOS用電
源回路を適用したので、回路供給電圧が変化して
もC−MOS入力電圧とC−MOS電源電圧とを常
に所定の傾きで電圧差を維持させることができ、
特に回路供給電圧の変動を考慮してそのための回
路部品を追加する必要がない。また、回路供給電
圧の変動に追随してC−MOS回路のスレツシユ
ホールドレベルが変化するので、回路供給電圧が
変動しても安定した動作を行なうことができるC
−MOS用電源回路を提供できる。
As described in detail above, according to the present invention, there is a resistive voltage divider circuit that divides the circuit supply voltage between the circuit supply voltage and the C-MOS power supply voltage, and a resistor voltage divider circuit that receives the divided voltage signal of this resistor voltage divider circuit. Since a C-MOS power supply circuit consisting of an emitter-follower connected transistor whose operation is controlled by the C-MOS power supply circuit is applied, even if the circuit supply voltage changes, the voltage difference between the C-MOS input voltage and the C-MOS power supply voltage is always maintained at a predetermined slope. can be maintained,
In particular, there is no need to add circuit components to account for fluctuations in circuit supply voltage. Furthermore, since the threshold level of the C-MOS circuit changes in accordance with fluctuations in the circuit supply voltage, stable operation can be achieved even when the circuit supply voltage fluctuates.
-We can provide power supply circuits for MOS.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図および第2図はそれぞれ従来回路の構成
図、第3図は従来回路を適用したC−MOS回路
の構成図、第4図は本考案に係るC−MOS用電
源回路の一実施例を示す構成図、第5図は第4図
の回路を適用したC−MOS回路の構成図、第6
図は本考案回路の動作を説明する図である。 21……トランジスタ、22,23……分圧用
抵抗。
Figures 1 and 2 are block diagrams of conventional circuits, Figure 3 is a block diagram of a C-MOS circuit to which the conventional circuit is applied, and Figure 4 is an example of a C-MOS power supply circuit according to the present invention. Fig. 5 is a block diagram of a C-MOS circuit to which the circuit of Fig. 4 is applied.
The figure is a diagram explaining the operation of the circuit of the present invention. 21... Transistor, 22, 23... Voltage dividing resistor.

Claims (1)

【実用新案登録請求の範囲】 回路供給電圧に第1、第2および第3の抵抗の
順序で直列接続された第1の抵抗分圧回路が接続
され、そのうち第1の抵抗と第2の抵抗との間に
接点信号が入力され、かつ、第2の抵抗と第3の
抵抗との間から得られる電圧を入力電圧とするC
−MOS回路に適用するC−MOS用電源回路にお
いて、 前記回路供給電圧を分圧する第2の抵抗分圧回
路と、この第2の抵抗分圧回路の分圧信号をベー
ス入力として受けエミツタ側より前記C−MOS
回路の電源電圧を出力するエミツタホロワ接続の
トランジスタとからなり、前記第2の抵抗分圧回
路の分圧比を前記第1の抵抗分圧回路の分圧比よ
りも大きくしたことを特徴とするC−MOS用電
源回路。
[Claims for Utility Model Registration] A first resistor voltage divider circuit in which a first resistor, a second resistor, and a third resistor are connected in series in the order of the circuit supply voltage is connected to the circuit supply voltage. A contact signal is input between the second resistor and the third resistor, and the input voltage is the voltage obtained between the second resistor and the third resistor.
- In a C-MOS power supply circuit applied to a MOS circuit, a second resistance voltage divider circuit divides the circuit supply voltage, and a voltage division signal of this second resistance voltage divider circuit is received as a base input from the emitter side. Said C-MOS
A C-MOS comprising an emitter follower connected transistor that outputs the power supply voltage of the circuit, and characterized in that the voltage division ratio of the second resistance voltage divider circuit is larger than the voltage division ratio of the first resistance voltage divider circuit. power supply circuit.
JP10492681U 1981-07-15 1981-07-15 C-MOS power supply circuit Granted JPS5811337U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10492681U JPS5811337U (en) 1981-07-15 1981-07-15 C-MOS power supply circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10492681U JPS5811337U (en) 1981-07-15 1981-07-15 C-MOS power supply circuit

Publications (2)

Publication Number Publication Date
JPS5811337U JPS5811337U (en) 1983-01-25
JPH036036Y2 true JPH036036Y2 (en) 1991-02-15

Family

ID=29899484

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10492681U Granted JPS5811337U (en) 1981-07-15 1981-07-15 C-MOS power supply circuit

Country Status (1)

Country Link
JP (1) JPS5811337U (en)

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4714629U (en) * 1971-03-17 1972-10-20

Also Published As

Publication number Publication date
JPS5811337U (en) 1983-01-25

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