JPH036036Y2 - - Google Patents

Description

[Detailed explanation of the idea] The present invention relates to improvement of a C-MOS power supply circuit.

In digital circuits that read out operating signals from contacts, a 24V DC power supply is often used because it is necessary to have a large noise margin and to increase the current supplied to the contacts to some extent. However, since a 24V DC power supply cannot be directly applied to a C-MOS circuit,
C by taking measures such as reducing the 24V DC voltage.
-Applied to MOS circuits. Figures 1 and 2
Each figure shows a conventional C-MOS power supply circuit.
FIG. 1 shows a configuration in which a circuit supply voltage Va is dropped by a resistor 1, and then a constant voltage C-MOS power supply voltage Vb is obtained by a Zener diode 2. Next, in FIG. 2, fluctuations in the circuit supply voltage Va are absorbed by a transistor 4 through a resistor 3, and a constant voltage C-
This is the configuration to obtain the power supply voltage for MOS. 5 is a reference voltage diode. Then, C shown in FIG.
- In the MOSIC, the C-MOS power supply circuit shown in FIG. 1 or 2 is applied to the block portion 6 indicated by the dashed line shown in the figure. In FIG. 3, 7 is a signal input terminal, 8 to 10 are resistors constituting the first resistance voltage divider circuit, 11 is a filter capacitor, and 12 is a C-
It is a MOS gate.

By the way, in the circuits shown in FIGS. 1 and 2, even if there is an error in the circuit supply voltage Va, or even if the circuit supply voltage Va itself fluctuates, a constant C-MOS power supply voltage Vb can be maintained by the Zener diode 2 or the transistor 4. However, when the above circuit is applied to a circuit as shown in FIG. 3, it becomes a drawback. In other words, in a device that has voltage dividing resistors 8 to 10 on the input side and divides the circuit supply voltage Va by these resistors 8 to 10 as shown in Fig. 3, errors and fluctuations in the circuit supply voltage Va are directly transmitted to the resistors 8 to 10. The voltage is divided by 10 and input to the C-MOS gate 12, but at this time
Since Vb itself is a constant voltage, the input voltage of the C-MOS gate 12 may become higher than the C-MOS power supply voltage Vb. Therefore, in the conventional circuit, it is necessary to provide a protection diode 13 shown by a dotted line in the figure so that the C-MOS gate input voltage does not become higher than the C-MOS power supply voltage Vb. Also, when the C-MOS power supply voltage Va fluctuates greatly, the C-MOS gate input voltage fluctuates;
Since the threshold level of the MOS gate 12 is constant, there is a drawback that when the input voltage approaches the threshold level, the output becomes unstable.

The present invention was developed in view of the above circumstances, and its purpose is to overcome the drawbacks of the conventional C-MOS power supply voltage by using a voltage obtained by dividing the circuit supply voltage using a resistor instead of a constant voltage. A C-MOS power supply circuit to be removed is provided.

An embodiment of the present invention will be described below with reference to FIG. The circuit shown in FIG. 4 divides the circuit supply voltage Va by a voltage dividing resistor 22 inserted between the collector and base of the transistor 21 and a voltage dividing resistor 23 whose other end is connected to zero potential. The configuration is such that the C-MOS power supply voltage Vb is taken out from the emitter side of the transistor 21. In other words, this circuit takes voltage dividing means using the resistors 22 and 23 that constitute the second resistance voltage dividing circuit, and also uses the transistor 21 as an emitter follower type to achieve low output impedance.
This is a C-MOS power supply circuit designed to obtain a MOS power supply voltage Vb. The circuit shown in FIG. 4 is applied to the block portion 24 indicated by the dashed line in the C-MOS circuit shown in FIG. Note that the same reference numerals in FIG. 5 are given to the same parts as in FIG. 3.

Next, the operation of this embodiment will be explained using FIGS. 4 and 5. The circuit supply voltage Va is divided by a second resistance voltage divider circuit consisting of resistors 22 and 23, and the divided voltage signal is controlled by an emitter follower-connected transistor 21 and is applied from the emitter side to C-.
It is taken out as the MOS power supply voltage Vb. In this case, the C-MOS power supply voltage Vb is determined by the voltage division ratio of the second resistance voltage divider circuit. That is, the slope of the C-MOS power supply voltage Vb with respect to the change in the circuit supply voltage Va is such that the resistance value of the resistors 22 and 23 is
22, R23, it is expressed by the following equation (1).

Slope of Vb = R23/(R22+R23) ...(1) Also, the circuit supply voltage Va is divided by the first resistor voltage divider circuit consisting of resistors 8 to 10, and the C-MOS
C-MOS gate 12 as gate input voltage Vin
is input. In this case, the C-MOS gate input voltage Vin is determined by the voltage division ratio of the first resistance voltage divider circuit. In other words, the slope of the C-MOS gate input voltage Vin with respect to the change in the circuit supply voltage Va changes the resistance values of the resistors 8 to 10 to R8, R9, R1.
If it is set to 0, it is expressed by the following equation (2).

Slope of Vin = R10/([R8+R9]+R10)...(2) Now, the voltage division ratio of the first resistor voltage divider circuit expressed by the above equation (2) is expressed by the above equation (1). so as not to become larger than the voltage division ratio of the second resistor voltage divider circuit.
Resistance values R8 to R10 of resistors 8 to 10 and resistor 22,
Assuming that the resistance values R22 and R23 of 23 are set, the slope of the C-MOS gate input voltage Vin and the C-MOS power supply voltage Vb with respect to the change in the circuit supply voltage Va is expressed by the above equations (1) and (2). Depending on the formula, the results will be as shown in A and B in Figure 6, respectively. Furthermore, in accordance with changes in the C-MOS power supply voltage Vb, the threshold level also changes as shown in FIG. 6C. In FIG. 6, Vbmax is the C-MOS maximum power supply voltage, and Vbo is the C-MOS operating voltage.

Therefore, as is clear from Figure 6, the first
By setting each resistance value so that the voltage division ratio of the second resistance voltage divider circuit is not larger than the voltage division ratio of the second resistance voltage divider circuit, the C-MOS gate input voltage Vin can be maintained even if the circuit supply voltage Va fluctuates. (A in the figure) will never become higher than the power supply voltage Vb (B in the figure). Therefore, there is no need to provide the protective diode 13 shown in FIG. 3 as in the conventional case. Moreover,
Since the threshold level also changes as shown in FIG. 6C, fluctuations in the circuit supply voltage Va will not cause unstable operation.

In addition, the circuit supply voltage Va is divided by resistors 22 and 23, and the divided voltage signal controls the emitter follower connected transistor 21 so that the C-
Since the MOS power supply voltage Vb is obtained and a voltage dividing means is provided using resistors 22 and 23, the error in the C-MOS power supply voltage Vb appearing on the emitter side is reduced.

As described in detail above, according to the present invention, there is a resistive voltage divider circuit that divides the circuit supply voltage between the circuit supply voltage and the C-MOS power supply voltage, and a resistor voltage divider circuit that receives the divided voltage signal of this resistor voltage divider circuit. Since a C-MOS power supply circuit consisting of an emitter-follower connected transistor whose operation is controlled by the C-MOS power supply circuit is applied, even if the circuit supply voltage changes, the voltage difference between the C-MOS input voltage and the C-MOS power supply voltage is always maintained at a predetermined slope. can be maintained,
In particular, there is no need to add circuit components to account for fluctuations in circuit supply voltage. Furthermore, since the threshold level of the C-MOS circuit changes in accordance with fluctuations in the circuit supply voltage, stable operation can be achieved even when the circuit supply voltage fluctuates.
-We can provide power supply circuits for MOS.

[Brief explanation of the drawing]

Figures 1 and 2 are block diagrams of conventional circuits, Figure 3 is a block diagram of a C-MOS circuit to which the conventional circuit is applied, and Figure 4 is an example of a C-MOS power supply circuit according to the present invention. Fig. 5 is a block diagram of a C-MOS circuit to which the circuit of Fig. 4 is applied.
The figure is a diagram explaining the operation of the circuit of the present invention. 21... Transistor, 22, 23... Voltage dividing resistor.

Claims (1)

[Claims for Utility Model Registration] A first resistor voltage divider circuit in which a first resistor, a second resistor, and a third resistor are connected in series in the order of the circuit supply voltage is connected to the circuit supply voltage. A contact signal is input between the second resistor and the third resistor, and the input voltage is the voltage obtained between the second resistor and the third resistor.
- In a C-MOS power supply circuit applied to a MOS circuit, a second resistance voltage divider circuit divides the circuit supply voltage, and a voltage division signal of this second resistance voltage divider circuit is received as a base input from the emitter side. Said C-MOS
A C-MOS comprising an emitter follower connected transistor that outputs the power supply voltage of the circuit, and characterized in that the voltage division ratio of the second resistance voltage divider circuit is larger than the voltage division ratio of the first resistance voltage divider circuit. power supply circuit.