JP2684837B2 - Differential amplifier circuit - Google Patents

Description

The present invention relates to a front differential amplifier circuit used in an unbalanced-balanced conversion circuit.

[Conventional technology]

In recent years, a double balanced differential amplifier circuit suitable for a monolithic IC is often used as an input circuit of a tuner for a television or a modulation / demodulation circuit of a wireless transceiver. This double balanced differential amplifier circuit has two balanced input terminals, and the input signal is premised on balanced input. However, since it is usually an unbalanced input in a high frequency signal, the unbalanced input which is the subject of the present patent is between this unbalanced input and the above-mentioned double balanced differential amplifier circuit.
A differential amplifier circuit is generally used as a circuit for balanced conversion. Since a relatively high level signal is input to this front differential amplifier circuit to improve the S / N ratio, a low gain so that the differential amplifier circuit does not saturate due to its own gain. Is desired.

Conventionally, a differential amplifier circuit of this type is as shown in FIG.
The emitters of the transistor 1 and the transistor 2 are commonly connected to the constant current source I1 via resistors R1 and R2 having the same resistance value, and the collectors of the transistors are connected to the power supply voltage terminal V _cc through load resistors R7 and R8. To do. The bases of the transistors 1 and 2 are set to resistors R3, R4, R5 and R
A bias voltage is applied by 6. The input signal is input from the unbalanced input signal IN and added to the base of the transistor 1, and the base of the other transistor 2 is grounded at high frequency by the capacitor C1. As a result, balanced signals having opposite phases were output to the output terminals OUT1 and OUT2 at both collectors of the transistors 1 and 2 which are output terminals.

[Problems to be solved by the invention]

In the above-described conventional differential amplifier circuit, it is effective to increase the values of the resistors R1 and R2 in order to obtain a low gain. However, as the values of the resistors R1 and R2 are increased, the value of FIG. Two output terminals that are balanced outputs as shown in the characteristic diagram of
There is a drawback that the deviation of the amplitude of OUT1 and OUT2 occurs even in the low frequency region. That is, since a transistor is generally used for the constant current source I1, the stray capacitance attached to its collector is a resistance.
It exists between R1 and R2. Therefore, the signal applied to the input terminal IN is transmitted from the emitter of the transistor 1 to the resistors R1 and R1.
While passing through 2 to the emitter of transistor 2, some of the signal is lost due to this stray capacitance. This effect has a very small value of stray capacitance, so it has no effect unless the input signal frequency is high.
Increasing the values of R1 and R2 will affect the frequency actually used. Therefore, the balanced input of the double balanced differential amplifier circuit connected to the next stage has a drawback that it is adversely affected because it is detected as an in-phase signal.

On the other hand, as a method to improve the deviation of the amplitude of the balanced output,
A differential amplifier circuit in which two differential amplifier circuits are connected in cascade is conceivable. In this two-stage type differential amplifier circuit, the deviation of the amplitude of the balanced output at the high frequency described above occurs because of the unbalanced input. Therefore, the output is used as the balanced input in the differential amplifier circuit of the same type. If it is input, the deviation of the output amplitude will be smaller than that in the case of direct unbalanced input. However, in order to connect two differential amplifier circuits of the same type in cascade, the output DC potential of the differential amplifier circuit of the previous stage and the DC voltage of the input stage of the differential amplifier circuit of the latter stage are connected.
An emitter follower and a level shift circuit are required in the middle for matching with the potential, which has a drawback that the frequency characteristic is deteriorated and the power consumption is increased.

[Means for solving the problem]

In the differential amplifier circuit of the present invention, the first and second signal input terminals to which an unbalanced signal is input are connected to their respective bases, and their respective emitters are commonly connected to a constant current source via a resistor. In a differential amplifier circuit having first and second transistors, a base is connected to a predetermined set potential, an emitter is connected to a collector of the first transistor, and a collector is connected to a power supply potential via a load resistor. A third transistor, a base connected to the predetermined set potential via a resistor, an emitter connected to the collector of the second transistor, and a collector connected to a power supply potential via a load resistor. And a balanced output signal from the collectors of the third and fourth transistors.

〔Example〕

 Next, the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram of the first embodiment of the present invention, and FIG. 2 is a characteristic explanatory view of the present embodiment. In the embodiment shown in FIG. 1, the same reference numerals as those in the conventional example shown in FIG. 2 indicate the same components.
That is, the emitters of the added transistors 3 and 4 are connected to the collectors of the transistors 1 and 2, respectively, and the balanced signals are taken out from the collectors of the transistors 3 and 4.

In the circuit configuration of this embodiment, the emitters of the transistors 1 and 2 are connected to the constant current source I1 via the resistors R1 and R2, and the base applies a bias voltage by the resistors R3 and R4 and R5 and R6. Has been done. Transistors 3 and 4 are cascode-connected to the collector sides of the transistors 1 and 2. The base of the transistor 3 is connected to a predetermined potential V _B , and the base of the transistor 4 is connected to V _B through the resistor R9. The collectors of the transistors 3 and 4 are connected to the power supply potential terminal V _cc via load resistors R7 and R8.

Next, the operation of this embodiment will be described. Due to the input signal voltage applied to the base of the transistor 1, the collector current signal is input to the emitter of the transistor 3 and output as the voltage change of the load resistance R7 of the transistor 3. On the other hand, the current signal transmitted to the emitter side of the transistor 1 is the resistance
It is input to the emitter of transistor 2 through R1 and R2,
It is output as a voltage change of the load resistance R8 through the transistor 4 in the opposite polarity. Since the transistor 3 is a so-called cascode connection, the mirror capacitance can be reduced and the frequency characteristic can be improved as compared with the case where the load resistor is directly connected to the collector of the transistor 1. Now, paying attention to the operation of the transistor 4, when the current amplification factor of the transistor 4 is β for the base potential of the transistor 4,
The value of the resistance R9 of the base current of 1 / β of the signal current flowing through the transistor 4 varies with the voltage. However, this variation is almost negligible unless β is large, because β is usually a value of about 100, which is the same state that the base is grounded like the transistor 3.

By the way, when the input signal has a low frequency, the base potential of the transistor 4 which slightly varies and the emitter potential which varies with the signal current flowing through the transistor 4 vary in the same phase. The fluctuation of the potential is delayed in phase with respect to the fluctuation of the emitter potential. That is, since the change in the base current of the transistor 4 has a time constant determined by the stray capacitance between the base and the emitter of the transistor 4 and the resistance, at the frequency affected by this time constant, the change in the base current is more This is because it will be late. The delay of the variation of the base potential with respect to the variation of the emitter potential of the transistor 4 causes a change in the voltage between the base and the emitter, which causes a positive feedback action on the signal current flowing through the transistor 4. For example, in the direction in which the signal current of the transistor 4 decreases, the emitter potential,
In the low frequency where there is no phase shift in the normal potential change, the base
Due to the voltage variation ΔV _BE between the emitters, the change in the emitter current is absorbed. However, at high frequencies, if the rise in the base potential lags behind the rise in the emitter potential, then the variation of the base-emitter voltage ΔV _BE ′ is the variation of the base-emitter voltage that can absorb the emitter current ΔV.
_It is smaller than _BE , which acts to further reduce the emitter current. The same applies to the direction in which the emitter current increases. Therefore, as shown in FIG. 2, the frequency characteristic of the output signal is widened to the high frequency region.

Next, a second embodiment of the present invention will be described with reference to the circuit diagram of FIG. In the second embodiment, the collectors of the transistors 1 and 2 are connected to the emitters of the transistors 3 and 4 through load resistors R12 and R13, respectively. Transistor
The bases of 3 and 4 are connected to a predetermined potential of V _B via resistors R9 and R10 having the same resistance value. The collector of the transistor 3 is directly connected to the power supply voltage terminal _Vcc, and the collector of the transistor 5 is connected to the power supply voltage terminal via the resistor R11. Here, the unbalanced input is input from the input terminal and output from the output terminals OUT1 and OUT2.

Next, the operation of the second embodiment will be described. Transistor 1
By the input signal voltage applied to the base of the transistor 1, the current signal generated in the transistor 1 is converted into a voltage by the load resistor 12 and appears as a voltage signal in the collector of the transistor 1. Similarly, the current signal transmitted from the emitter of transistor 1 to transistor 2 through resistors R1 and R2 is the load resistance.
The voltage is converted by R13 and output to the collector of the transistor 2 with the opposite polarity. At this time, the impedance seen from the collector of the transistor 1 to the load side is a series impedance of the resistor R12 and the impedance of the emitter side of the transistor 3. The impedance Z ₃ on the emitter side of the transistor ₃ is generally expressed by equation (1), where h _FE is the current amplification factor of the transistor 3.

Z ₃ = r _e + R10 / (1 + h _FE ) ... (1) Here, the internal impedance r _e is r _e = kT / qI _E , and the emitter current I _E is about 26 Ω at 1 mA. h _FE is usually 50 ~
Since it is as large as 200, the impedance Z seen from the emitter side
_{Although 3} is small, since it is added to R12 by this amount, the load resistance becomes larger than the resistance value of R12. On the other hand, the same applies when the load side is viewed from the collector of the transistor 2. Focusing on the operation of the transistor 4 connected to the load side of the transistor 2, for example, the signal current of the transistor 2 increases due to the input signal, and the voltage drop of the load resistance causes the output terminal OU.
If the potential of T1 decreases, the base current also increases as the current of the transistor 4 increases, and the base potential of the transistor 4 decreases due to the voltage drop of the resistor R9. Further, as the current of the transistor 4 increases, the collector potential of the transistor 4 decreases due to the voltage drop of the resistor R11. This relationship indicates that the base potential and the collector potential of the transistor 4 change with the same polarity. Therefore, due to the stray capacitance between the base and the emitter of the transistor 4, a change in the voltage on the collector side is transmitted to the base, which serves as a kind of positive feedback. This positive feedback does not operate as a positive feedback for a low frequency signal because the stray capacitance between the base and the collector is small, but the positive feedback effect appears at higher frequencies. Due to the effect of this positive feedback, the variation of the base potential of the transistor 4 becomes larger than that without the resistor R11, and the variation is transmitted to the emitter. The fluctuation transmitted to the emitter has the same polarity as the voltage fluctuation of the collector of the transistor 2 and is added. As described above, in the transistor 2, a differential amplifier circuit in which the voltage amplitude of the collector, that is, the output amplitude of the OUT terminal increases at a high frequency where the above-mentioned positive feedback effect is obtained, and the frequency characteristic extends to the high frequency region, is provided. realizable.

〔The invention's effect〕

As described above, according to the present invention, the positive feedback action in the high frequency region between the base and collector of the transistor circuit provided on the load side of the transistor of the unbalanced / balanced conversion differential amplifier circuit to which the unbalanced input signal is applied. A differential amplifier circuit capable of extending one frequency characteristic of the differential amplifier circuit and extending the frequency range in which the deviation of the amplitude of the balanced output of the differential amplifier circuit occurs to a high range to extract a balanced output signal. There is an effect that can be provided.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of the first embodiment of the present invention, FIG. 2 is a characteristic explanatory diagram of the present embodiment, FIG. 3 is a circuit diagram of the second embodiment of the present invention, and FIG. FIG. 5 is a circuit diagram of a differential amplifier circuit, and FIG. 5 is a characteristic explanatory diagram of a conventional circuit. 1,2,3,4 …… transistor, R1 to R9 …… resistor, I1 …… constant current source, C1 …… capacitor, IN …… input terminal, OUT1, OUT
2 …… Output terminal.

Claims (2)

(57) [Claims] 1. A first and second signal input terminal to which an unbalanced signal is input are connected to respective bases, and respective emitters are commonly connected to a constant current source via a resistor. In a differential amplifier circuit having two transistors, a base is connected to a predetermined set potential, an emitter is connected to a collector of the first transistor, and a collector is connected to a power supply potential via a load resistor. A transistor; and a fourth transistor whose base is connected to the predetermined set potential via a resistor, whose emitter is connected to the collector of the second transistor, and whose collector is connected to the power supply potential via a load resistor. And the third
And a differential amplifier circuit which extracts a balanced output signal from the collector of the fourth transistor. 2. A first and second signal input terminal to which an unbalanced signal is input are connected to respective bases, and respective emitters are commonly connected to a constant current source via a resistor. In the differential amplifier circuit having two transistors, the emitters of the third and fourth transistors are respectively connected to the collectors of the first and second transistors via resistors, and the bases of the third and fourth transistors are respectively connected to each other via resistors. Connected to a set potential, the collector of the third transistor is directly connected to the power supply potential, the collector of the fourth transistor is connected to the power supply potential via a resistor, and the collectors of the first and second transistors A differential amplifier circuit characterized by extracting a balanced output signal from the output.