JP2797805B2 - Analog multiplier - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an analog multiplier.
In particular, the present invention relates to an analog multiplier which is formed into a monolithic IC and applied to an infinite phase shifter or the like of a wireless communication device.

[0002]

2. Description of the Related Art Conventionally, as shown in FIG. 3, an analog multiplier of this type is based on a double balanced differential amplifier circuit, and transistors Q1, Q3, Q4 and Q2, Q5,
The outputs of the two sets of differential amplifier circuits Q6 are connected in common with opposite polarities to the output terminals OUT1 and OUT2, and the resistance R
The power supply Vcc is supplied via R3 and R4.

On the other hand, the emitters of the transistors Q1 and Q2 are connected to a constant current source I1 via emitter resistors R1 and R2, thereby supplying a current that satisfies optimum operating conditions.

A high-frequency signal is applied to the input terminals IN1 and IN2. Since the high-frequency signal is generally unbalanced, the input terminal IN2 is grounded at a high frequency by a capacitor C1.

Next, the operation will be described.

The transistor Q1 sends an emitter current signal to the emitter of the transistor Q2 via the emitter resistors R1 and R2 in response to a high-frequency signal applied to the input terminal IN1. Therefore, a signal of the same magnitude and opposite polarity as the current signal of the transistor Q1 appears at the collector of the transistor Q2.

On the other hand, the collector current signal of the transistor Q1 flows to the transistors Q3 and Q4, and similarly, the collector current signal of the transistor Q2 is also changed to the transistors Q5 and Q4.
Flow to 6. Here, transistors Q3, Q4 and Q
Since the outputs of the two sets of differential amplifier circuits 5 and Q6 are connected in common with opposite polarities, if there is no potential difference between the input terminals IN3 and IN4, the transistors Q3 and Q5 and the transistors Q4 and Q6 Signals cancel each other out, and no signal appears at the output terminals OUT1 and OUT2.

When the potential of the input terminal IN3 is higher than IN4, the signal of the transistor Q3 is
5, the signal of the transistor Q3, that is, a signal of the same polarity as the transistor Q1 appears at the output terminal OUT1. Similarly, the output terminal OUT2
The signal of the transistor Q6, ie, the transistor Q
A signal of the same polarity as 2 appears. In this case, the input terminal I
The higher the potential difference between N3 and IN4, the greater the output signal.

When the potential of the input terminal IN4 is higher than the potential of the input terminal IN3, the signal of the transistor Q5 is larger than the signal of the transistor Q3.
1, a signal of the transistor Q5, that is, a signal of the same polarity as the transistor Q2 appears, and the input terminals IN3 and IN
The higher the potential difference from 4, the larger the output signal. Similarly, a signal from the transistor Q4, that is, a signal having the same polarity as that of the transistor Q1, appears at the output terminal OUT2.

As described above, since the magnitude and polarity of the output signal change depending on the potential difference and polarity of the input terminals IN3 and IN4, the phase difference is shifted by 90 ° from each other, for example, by using two analog multipliers. Input signal IN1
, And by combining the output signals by controlling the potential difference between the input terminals IN3 and IN4, an infinite phase shifter is provided which outputs a signal of a constant amplitude at an arbitrary phase irrespective of the phase of the input signal. Can be.

[0011]

When an infinite phase shifter is constituted by the above-described conventional analog multiplier, a relatively high-level signal is input in order to improve the S / N ratio of an output signal. Therefore, by increasing the values of the emitter resistors R1 and R2 on the emitter side of the transistors Q1 and Q2, the gain is reduced without saturation.

However, when the values of the emitter resistors R1 and R2 are increased, the influence of the stray capacitance Cs of the constant current source I1 appears. That is, since a part of the current signal from the emitter of the transistor Q1 flows out via the stray capacitance Cs, the phase of the current signal flowing into the emitter of the transistor Q2 is shifted.

As a result, an amplitude difference and a phase difference occur between the collector current signals of transistors Q1 and Q2. Therefore, even when there is no potential difference between input terminals IN3 and IN4, transistors Q3 and Q5 and transistors Q4 and Q6 do not.
Signals do not cancel each other, and signals appear at the output terminals OUT1 and OUT2. Also, input terminals IN3, I
Even if the amplitude is made equal by adjusting the potential difference of N4, the phase difference is deviated from 180 °, so that it cannot be completely canceled out, and signals appear at the output terminals OUT1 and OUT2. Therefore, when the conventional analog multiplier is applied to an infinite phase shifter, there is a problem that the output amplitude is not constant at an arbitrary phase.

SUMMARY OF THE INVENTION An object of the present invention is to provide an analog multiplier which can make the output amplitude constant at an arbitrary phase when applied to an infinite phase shifter by canceling a phase shift caused by a stray capacitance when an emitter resistance value is increased. Is to provide.

[0015]

In the analog multiplier of the present invention, a constant current source for supplying a constant current through an emitter resistor is connected to the emitters of two transistors constituting a differential amplifier circuit. In an analog multiplier including a double-balanced differential amplifier circuit in which a high-frequency signal is applied to the base of one of the transistors, the area between the one transistor is set larger than the other and the junction between the base and the collector is set. The capacitance is increased, and a current signal corresponding to a current signal flowing out through the stray capacitance of the constant current source flows to the collector of the one transistor through the junction capacitance.

[0016]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram showing an embodiment of the present invention, and shows an equivalent circuit when a monolithic IC is formed. The difference from the conventional analog multiplier shown in FIG. 3 is that the junction capacitance Cgc between the base and the collector of the transistor Q1 is increased.

Now, as in the conventional example, the emitter resistance R
When the values of R1 and R2 are increased, the influence of the stray capacitance Cs of the constant current source I1 appears. That is, since a part of the current signal ie1 from the emitter of the transistor Q1 flows out through the stray capacitance Cs, the phase of the current signal flowing into the emitter of the transistor Q2 is shifted.

When a high-frequency signal is applied to the input terminal IN1, a current signal igc flows to the emitters of the transistors Q3 and Q4 via the junction capacitance Cgc between the base and the collector of the transistor Q1. This current signal igc
Is delayed by 90 ° with respect to the current signal ie1,
A current signal synthesized on the collector side of the transistor Q1,
That is, a phase shift occurs in the current signals transmitted to the transistors Q3 and Q4. Here, by increasing the area of the transistor Q1 and setting the junction capacitance Cgc between the base and the collector to an appropriately large value, the transistor Q1
, And the phase shift of the current signal transmitted from the transistor Q1 to the transistors Q5 and Q6 via the transistor Q2 can be canceled.

Now, as shown in FIG.
Assuming that the current signal flowing from 1 to the emitter resistor R1 is ie1 and the current signal flowing out via the stray capacitance Cs is is
The current signal flowing from the emitter resistor R2 to the transistor Q2 is ie2. The base of the transistor Q1
A current signal igc flowing through the junction capacitance Cgc between the collectors,
From the collector of the transistor Q1 to the transistors Q3 and Q
Assuming that the current signal transmitted to the transistor 4 is ic1, the transistor Q
The current signal synthesized on the collector side of 1 is ic2.
Therefore, by setting the junction capacitance Cgc to an appropriate value, the phase difference between the current signal ic2 and the current signal ie2 can be made 180 °. That is, the influence of the phase shift due to the stray capacitance Cs can be eliminated.

It should be noted that even if the junction capacitance Cgc between the base and collector of the transistor Q1 is increased,
Since the impedances of the transistors Q3 and Q4 connected to the first collector are low, the influence of the Miller effect can be ignored. Further, since the base-emitter of the transistor Q1 is forward-biased, the increase in the base-emitter capacitance is small, and the influence on the high-frequency characteristics is small. Further, when an imbalance occurs in the bias current with the transistor Q2, the problem can be solved by increasing the area of the transistor Q2. In this case, for the same reason, the influence of the capacitance between the base and the emitter of the transistor Q2 is small.

[0022]

As described above, according to the present invention, in order to cancel the influence of the stray capacitance of the constant current source connected via the emitter resistor to the emitters of the two transistors constituting the differential amplifier circuit. By setting the area of one of the transistors large, the junction capacitance between the base and the collector to an appropriately large value, and flowing a current signal corresponding to the current signal flowing through the floating capacitance through the junction capacitance between the base and the collector. Since the phase shift at the output terminal can be corrected, when applied to an infinite phase shifter, it is possible to obtain an output having a constant amplitude at an arbitrary phase.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing one embodiment of the present invention.

FIG. 2 is a vector diagram for explaining the operation of the present embodiment.

FIG. 3 is a circuit diagram illustrating an example of a conventional analog multiplier.

[Explanation of symbols]

 Q1 to Q6 Transistors R1 and R2 Emitter resistances IN1 to IN4 Input terminals OUT1 and OUT2 Output terminals I1 Constant current source Cs Floating capacitance Cgc Base-collector junction capacitance is Current signal flowing through floating capacitance Cs igc Current signal flowing through junction capacitance Cgc

Claims (1)

(57) [Claims] 1. A constant current source for supplying a constant current to an emitter of two transistors constituting a differential amplifier circuit via an emitter resistor, and a high-frequency signal is supplied to a base of one of the two transistors. An analog multiplier comprising a double-balanced differential amplifier circuit to be applied, wherein an area of the one transistor is set larger than another to increase a junction capacitance between a base and a collector, and An analog multiplier, wherein a current signal corresponding to a current signal flowing out through a stray capacitance flows to a collector of the one transistor through the junction capacitance.