JPS6349938Y2 - - Google Patents

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to a limiter circuit for configuring, for example, an FM demodulator with good limiter characteristics.

[Background technology of the invention]

Generally, FM demodulators are basically ratio demodulators equipped with means to improve limiter characteristics, but Foster-Seeley demodulators without such means and ceramics suitable for recent integrated circuits are used. Quadruple layer demodulators that use filters or even phase shift circuits require a circuit that limits the amplitude of the FM signal input to the demodulator to a constant value. FIG. 1 shows a conventional example of a limiter circuit that suppresses the signal input of a demodulator to a constant amplitude, which is particularly suitable for such integration. This limiter circuit is composed of two stages of differential amplifiers that utilize the input/output characteristics of differential amplifiers, and the signal that enters input terminal 1 is amplified by transistors Q ₁ and Q ₂ of the previous stage differential amplifier. This differential output is supplied to transistors Q ₅ and Q ₆ forming a differential amplifier in the subsequent stage via emitter follower transistors Q ₃ and Q ₄ for interstage coupling, which are further connected to emitter follower transistors Q for output. ₇ and _Q8 to the differential output terminals 2 and 2'. In addition, constant current source transistors Q ₉ and 2 are connected to the common emitter terminals P ₁ and P ₂ of each differential amplifier
_Q10 is provided for each. In addition, the differential amplifier at the front stage connects the signals of differential output terminals 2 and 2' to the bases of each transistor Q ₁ and Q ₂ through a resistor R ₁ and a capacitor, respectively.
It is fed back as a base bias voltage through an integral filter consisting of C ₁ , resistor R ₂ , and capacitor C ₂ , and further through base resistors R ₃ and R ₄ , respectively. On the other hand, each transistor of the differential amplifier in the subsequent stage
The bases of Q ₅ and Q ₆ are the constant current source transistors Q ₉ and
Current source transistors Q ₁₁ and Q 12 that are driven with a constant current by the same bias circuit 3 (within the broken line frame) as Q ₁₀ are connected, respectively, and this constant current _source transistor
Q ₁₁ and Q ₁₂ also serve as current sources for the emitters of the interstage coupled emitter follower transistors Q ₃ and Q ₄ .

Further, the bias circuit 3 supplies the power supply voltage applied to the power supply terminal 4 to each of the differential amplifiers through the transistor _Q13 , and also supplies the power supply voltage applied to the power supply terminal 4 to each of the differential amplifiers through the transistor _Q13 and the transistor _Q14 connected in series with the transistor Q13.
From the emitter of each constant current source transistor Q ₉
A constant current is supplied to the base of _Q12 . In addition, a transistor is used as a configuration for this purpose.
_Q14 is a constant current circuit with diodes _D1 and _D2 arranged in series between the base and emitter.

Thus, the bias, that is, the operating point, of each of the differential amplifiers is determined by the current source transistors Q ₉ to _{Q 12} driven by the constant current supplied from the constant current circuit. In addition, since the bias voltage formed by the integrating filter is applied to the base of each transistor Q ₁ and Q ₂ in the front-stage differential amplifier,
The operating point can be stabilized, and when there is no signal, the base voltages of each differential amplifier are kept at the same potential (balanced state). Here, when there is an input signal at input terminal 1, this signal is applied to the base of one transistor Q ₁ of the previous stage differential amplifier, and each transistor
Output from the collectors of Q ₁ and Q ₂ . At this time,
The input signal is subjected to a limiting action at the bases of transistors Q ₁ and Q ₂ for signals with an amplitude of approximately 2V _F (V _F is the forward voltage of the PN junction) or less, and is made a constant output and output to the emitter follower transistor. This emitter follower transistor Q ₃ , which is transmitted to Q ₃ , Q ₄ ,
Q ₄ is each transistor Q ₅ of the subsequent differential amplifier,
It is derived to the base of Q ₆ , where the same limiter action is performed again. The output is led out to differential output terminals 2 and 2' via output emitter followers Q ₇ and Q ₈ and then introduced into a detection stage. Here, the output emitter follower transistors Q ₇ , Q ₈
The resistors R ₅ and R ₆ provided on the emitter side are simply emitter bias resistors.

[Problems with background technology]

The conventional circuit has been described above. In the above, when the input signal amplitude exceeds 2V _F , the transistor _Q1 of the front-stage differential amplifier operates close to the saturation region, causing waveform distortion. In other words, the limiter circuit using a differential amplifier is
The output is constant for inputs above a certain voltage, but the signal must have an amplitude close to the input that saturates each transistor, and the range of output without distortion is extremely narrow. Therefore,
If the input signal amplitude becomes excessive beyond this range,
The limiter performance deteriorated, and when combined with an FM demodulator, the amplitude component suppression performance (AMR) decreased.

[Purpose of invention]

This idea was made in view of the above points,
The present invention provides a limiter circuit that utilizes the limiter characteristics of a differential amplifier and has a wide input dynamic range.

[Summary of the idea]

The present invention connects two or more stages of amplifier circuits, each consisting of a differential amplifier and an emitter follower circuit provided at each of its differential output terminals, and inserts a constant voltage source such as a diode on the emitter side of the emitter follower circuit of a predetermined stage. This is a limiter circuit in which the signal that has passed through this constant voltage source is fed back to the differential input terminal of the first stage differential amplifier via an integrating filter, and the constant voltage source limits the amplitude and shifts the level of the output signal. do,
The base bias voltage applied to the differential input terminal of the first stage differential amplifier is lowered to widen the input dynamic range. This prevents waveform distortion even if the amplitude of the input signal exceeds a level that would saturate the transistors constituting the differential amplifier, thereby improving limiter performance.

[Example of idea]

Hereinafter, an embodiment of the present invention will be described based on FIG. 2. FIG. 2 shows a limiter circuit, and the same components as in FIG. 1 are denoted by the same reference numerals. In FIG. 2, input terminal 1 is connected via a coupling capacitor _C3 to the base of a transistor _Q1 constituting a first stage differential amplifier. This transistor Q ₁
The base of transistor _Q2 , which forms a differential pair with
It is grounded via R ₄ and capacitor C ₂ in series. The common emitter terminal P ₁ of the differential pair transistors Q ₁ and Q ₂ is grounded via the collector-emitter path of the constant current source transistor Q ₉ and the resistor R ₇ . Further, the collectors of the differential pair transistors Q ₁ and Q ₂ are connected to the emitter of the power supply voltage supply transistor Q ₁₃ of the bias circuit 3 via resistors R ₈ and R ₉ , respectively. In addition, the collectors of transistors Q ₁ and Q ₂ are interstage coupled emitter follower transistors.
It is connected via Q ₃ and Q ₄ to the respective bases of differential pair transistors Q ₅ and Q ₆ forming a rear-stage differential amplifier.

The base bias of the transistors Q ₅ and Q ₆ of this latter stage differential amplifier is the constant current source transistor Q ₁₁ ,
Powered by _Q12 . Further, the interstage coupled emitter follower transistors Q ₃ and Q ₄ are connected to the power supply terminal 4 and the ground so that the constant current source transistors Q ₁₁ and Q ₁₂ and their respective collector-emitter paths are in series. is provided in between. moreover,
Common emitter terminal of differential pair transistors Q ₅ and Q _6
P2 is grounded via the collector-emitter path of constant current source transistor _Q10 and resistor _R11 .

This constant current source transistor Q ₁₀ and each of the aforementioned constant current source transistors Q ₉ etc. are connected to the bias circuit 3.
The operating point of each differential amplifier is set by a constant current circuit consisting of a transistor Q ₁₄ and diodes D ₁ and D ₂ . Due to this operating point and the base bias voltage, even if the input signal has an amplitude component, it can be made constant at the output stage, and can function as a limiter. Further, the collector of the transistor _Q5 is connected to the emitter of the power supply transistor _Q13 via a resistor _R12 . Also,
Similarly _{, the voltage of the transistor Q13 is} supplied to the collector of the transistor _Q6 via the resistor R13. Also, differential pair transistors Q ₅ , Q ₆
The differential output is an emitter follower transistor for output.
The signal is taken out to the differential output terminals 2 and 2' via Q ₇ and Q ₈ . A power supply voltage is applied to each of these emitter follower transistors Q ₇ and Q ₈ from the collector.

In addition, output emitter follower transistor Q ₇ ,
The emitter of Q ₈ is connected to one end of a constant voltage source such as diodes D ₃ and D ₄ . These diodes D ₃ ,
The other end of _D4 is grounded through resistors _R5 and _R6 , and connected to the first stage through an integral filter consisting of resistor _R2 and capacitor _C2 , and an integral filter consisting of resistor _R1 and capacitor _C1 , respectively. It is connected to the base side resistances R ₄ and R ₃ of the differential pair transistors Q ₂ and Q ₁ .

Incidentally, the configuration of the bias circuit 3 is the same as the conventional one, so a description thereof will be omitted.

Next, the operation of the above circuit will be explained. First, when no signal is input, the DC level of the differential output terminals 2 and 2' is applied to the transistors Q ₂ and Q ₁ of the first stage differential amplifier via the diodes D ₃ and D ₄ , the integrating filter, and the resistors R ₄ and R ₃ , respectively. It is applied to the base and provides a predetermined bias voltage. This bias voltage has approximately the same potential in order to balance the circuit. This bias voltage increases as the input signal increases,
The limiting effect is no longer effective for large amplitude input signals, and the differential pair transistor Q ₁ ,
Since Q ₂ was saturated, distortion occurred in the transmitted waveform. In this embodiment, in order to prevent this distortion from occurring, the bias voltage fed back from the differential output terminals 2 and 2' is shifted by the constant voltage source diodes D ₃ and D ₄ to reduce the initial stage difference. The base bias voltage applied to the bases of the dynamic pair transistors Q ₁ and Q ₂ is lowered by the voltage drop of the diodes D ₄ and D ₃ .

When an input signal enters from terminal 1 in this state, it enters the base of transistor Q ₁ via capacitor C ₃ , and its differential output is transmitted to interstage emitter follower transistors Q ₃ and Q ₄ . At this time, if the input FM signal has an amplitude component, the amplitude component remains as noise in a later detection stage (not shown), so the amplitude is kept constant by this limiter circuit. This differential amplifier operates in a manner that can be called a limiter amplification, and if the input signal has a constant amplitude, it has a limiting function of outputting a constant amplitude even if the input signal has a slight change in amplitude. Now, when an excessive amplitude component is mixed into the input signal due to the influence of external noise, the DC level of this output excessive amplitude signal is shifted by the amount of the diodes D ₃ and D ₄ , and is further shifted by the resistor R ₂ and capacitor C _2. and resistor R ₁ and capacitor
The first stage differential pair transistors are integrated through _C1
Apply to each base of Q ₂ and Q ₁ . Therefore _, even if the input becomes excessive, the differential pair _transistor is
The bias voltage applied to Q ₁ and Q ₂ is always lower than in the past. This makes it possible to widen the amplitude limit of the input signal at which the differential pair transistors Q ₁ and Q ₂ are saturated. As a result, input terminal 1
Even if the FM signal has amplitude fluctuations with a wide dynamic range, this fluctuation is caused by differential output terminals 2 and 2.
2' is transmitted less.

In addition, the diode D ₃ used for level shift,
The constant voltage source of D ₄ is not limited to these diodes, but any semiconductor having constant voltage characteristics may be used, or a combination of a plurality of them may be used. In addition, the output format was a differential output type, but a limiter circuit with an unbalanced output type, that is, a differential amplifier with an emitter follower transistor added to only one output terminal, connected in multiple stages. It is also possible to do so.

[Effect of idea]

As described above, according to the present invention, an emitter follower is inserted between the stages of a limiter circuit using a plurality of differential amplifiers, and the emitter follower between the stages that performs feedback is connected to the first stage differential amplifier via a constant voltage source. Since the output signal is connected to the constant voltage source, the level-shifted output signal can be fed back to the circuit through the constant voltage source, and the input dynamic range can be expanded. In addition, it has excellent limiter characteristics.
It can provide an FM demodulator.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing a limiter circuit using a conventional differential amplifier, and FIG. 2 is a circuit diagram showing a limiter circuit according to an embodiment of the present invention. _Q1 to _Q14 ...transistor, _D1 to _D4 ...diode, _R1 to _R13 ...resistor, _C1 to _C3 ...capacitor.

Claims (1)

[Claim for Utility Model Registration] An amplifier circuit consisting of a differential amplifier having first and second transistors whose emitters are commonly connected, and an emitter follower circuit connected to the output terminal of the differential amplifier is connected in multiple stages in a cascade manner. , in a limiter circuit configured to supply an input signal to a first-stage differential amplifier, a constant voltage element for level shifting is connected to the emitter of a transistor forming an emitter follower circuit at a predetermined stage among the plurality of stages; A limiter circuit comprising means for supplying a signal level-shifted by a voltage element to the base of a transistor of the first-stage differential amplifier via an integrating filter and applying feedback to lower the base bias.