JPH07105671B2 - Balanced amplifier - Google Patents

Balanced amplifier

Info

Publication number
JPH07105671B2
JPH07105671B2 JP62107404A JP10740487A JPH07105671B2 JP H07105671 B2 JPH07105671 B2 JP H07105671B2 JP 62107404 A JP62107404 A JP 62107404A JP 10740487 A JP10740487 A JP 10740487A JP H07105671 B2 JPH07105671 B2 JP H07105671B2
Authority
JP
Japan
Prior art keywords
amplifier
input terminal
current source
terminal
voltage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP62107404A
Other languages
Japanese (ja)
Other versions
JPS63269813A (en
Inventor
浩一 西村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP62107404A priority Critical patent/JPH07105671B2/en
Publication of JPS63269813A publication Critical patent/JPS63269813A/en
Publication of JPH07105671B2 publication Critical patent/JPH07105671B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は閉ループの平衡増幅器に関し、特にそのバイア
ス法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a closed loop balanced amplifier, and more particularly to a bias method thereof.

〔従来の技術〕[Conventional technology]

第3図は従来の平衡増幅器の閉ループ回路におけるバイ
アス法の一例であり、非平衡の電流源I0で帰還抵抗をバ
イアスすることにより平衡出力を得ている。すなわち、
正および負の入力端子と正転および反転出力端子をもつ
演算増幅器A1の負入力端子−と正転出力端子3との間に
抵抗R1を接続し、正入力端子+には電流源5を接続す
る。又、正入力端子+と反転出力端子4との間には抵抗
R2を接続する。演算増幅器A1の電源端子にはそれぞれ正
電源端子1および負電源端子2が接続されている。
FIG. 3 shows an example of a bias method in a closed loop circuit of a conventional balanced amplifier, in which a balanced output is obtained by biasing a feedback resistor with an unbalanced current source I 0 . That is,
A resistor R 1 is connected between the negative input terminal − and the normal output terminal 3 of an operational amplifier A 1 having positive and negative input terminals and normal and inverted output terminals, and a current source 5 is connected to the positive input terminal +. Connect. In addition, there is a resistor between the positive input terminal + and the inverting output terminal 4.
Connect R 2 . A positive power supply terminal 1 and a negative power supply terminal 2 are connected to the power supply terminals of the operational amplifier A 1 , respectively.

ここで電流源5の電流値をI0とし、正転出力端子電圧を
VOUT、反転出力端子電圧V▲ ▼とすると となり不平衡の電流I0が平衡出力に変換される。
Here, the current value of the current source 5 is I0And the forward output terminal voltage
VOUT, Inverting output terminal voltage V ▲ And unbalanced current I0Are converted to balanced outputs.

〔発明が解決しようとする問題点〕[Problems to be solved by the invention]

上述した従来の平衡増幅器の回路構成では、正負両入力
端子+,−の電圧が反転出力端子4の電圧と同じにな
り、演算増幅器A1の出力端子の電圧範囲と同じだけ演算
増幅器A1の入力端子+,−の電圧範囲を広くとれるよう
な回路構成にする必要がある。又演算増幅器A1の入力端
子+,−の電圧が上記の理由により大きく変化し、演算
増幅器A1の同相信号除去比(CMRR)特性による誤差が大
きくなるという欠点がある。又入力耐電力の変化が大き
いということは、電流源の出力インピーダンスによる誤
差も受けやすいだけでなく、電流源の出力ダイナミック
レンジを広くする必要がある等の欠点があった。
In the circuit configuration of a conventional balanced amplifier we described above, positive and negative input terminals + and - of the voltage becomes equal to the voltage at the inverting output terminal 4, only the same as the voltage range of the output terminal of the operational amplifier A 1 of the operational amplifier A 1 It is necessary to have a circuit configuration that allows a wide voltage range of the input terminals + and-. The operational amplifier A 1 input terminal +, - voltage greatly changes by the above reasons, there is a drawback that error is increased due to common-mode rejection ratio (CMRR) characteristic of the operational amplifier A 1. Further, the large change in the input withstand power is not only susceptible to an error due to the output impedance of the current source, but also has a drawback that it is necessary to widen the output dynamic range of the current source.

〔問題点を解決するための手段〕[Means for solving problems]

本発明の目的は、入力端電圧の変化量を小さくして、不
平衡の電流を平衡出力に変換する精度を向上したバイア
ス回路を備えた平衡増幅器を提供することにある。
It is an object of the present invention to provide a balanced amplifier including a bias circuit that reduces the amount of change in the input terminal voltage and improves the accuracy of converting an unbalanced current into a balanced output.

本発明の平衡増幅器は、演算増幅器と、この演算増幅器
の負入力端子と正転出力端子間に接続された第1の抵抗
と、前記演算増幅器の正入力端子と反転出力端子間に接
続された第2の抵抗と、一端が前記演算増幅器の負入力
端子に接続された第3の抵抗と、一端が前記演算増幅器
の正入力端子に接続された第4の抵抗と、前記演算増幅
器の正転、又は負入力端子に接続された電流源とを具備
し、前記第3と第4の抵抗の他端を相互接続して基準電
圧に接続している。
The balanced amplifier of the present invention includes an operational amplifier, a first resistor connected between the negative input terminal and the non-inverting output terminal of the operational amplifier, and a positive resistance connected between the positive input terminal and the inverting output terminal of the operational amplifier. A second resistor, a third resistor whose one end is connected to the negative input terminal of the operational amplifier, a fourth resistor whose one end is connected to the positive input terminal of the operational amplifier, and a normal resistor of the operational amplifier. , Or a current source connected to the negative input terminal, and the other ends of the third and fourth resistors are interconnected and connected to a reference voltage.

〔実施例〕〔Example〕

次に、本発明について図面を参照して説明する。 Next, the present invention will be described with reference to the drawings.

第1図は本発明の一実施例に係る平衡増幅器の回路であ
る。本実施例では、負入力端子と正転出力端子3との間
に帰還抵抗R1を接続し、又正入力端子+と反転出力端子
4との間に帰還抵抗R2を接続する。そして負入力端子−
と正入力端子+と基準電圧Vrefとの間に各々抵抗R3とR4
を接続し、又負入力端子−と負電源端子との間に電流源
5を接続する。入力信号は電流源5の出力として与えら
れる。
FIG. 1 is a circuit diagram of a balanced amplifier according to an embodiment of the present invention. In this embodiment, a feedback resistor R 1 is connected between the negative input terminal and the non-inverted output terminal 3, and a feedback resistor R 2 is connected between the positive input terminal + and the inverting output terminal 4. And the negative input terminal −
Between the positive input terminal + and the reference voltage V ref, and resistors R 3 and R 4 respectively.
And the current source 5 is connected between the negative input terminal-and the negative power supply terminal. The input signal is given as the output of the current source 5.

次に本実施例の動作について説明する。今各抵抗R1〜R4
の抵抗値をR1〜R4とし、R1=R2=Rf,R3=R4=Rsとし、
基準電圧Vrefを0Vとし、電流源5の電流値をI0とする。
そして正転出力端子3の電圧をVOUT,反転出力端子4の
電圧をV▲ ▼とし、イマジナリーショートの正転
を反転入力の電圧をV1とすると 抵抗R4に流れる電流をI4とすると 抵抗R2に流れる電流をI2とすると 電流源5の電流値をI0とすると I0=I2+I4 ……(6) 又、正転・反転出力端子3,4の出力VOUTとV▲
は平衡出力であることから (4),(5),(6)式より (3),(8)式より (7),(9)式より となり、出力VOUT,V▲ ▼は抵抗値Rs、すなわち抵
抗R3およびR4の抵抗値と無関係となり、抵抗値Rsは入出
力関係に式上は影響を与えない。又、ここで(3)式か
らわかるように従来例に比べ入力端電圧比はRs/(Rs+R
f)となり、抵抗R3,R4の抵抗値RSを抵抗R1,R2の抵抗値R
fに対して小さくすればする程、入力端電圧変位は小さ
くなる。
Next, the operation of this embodiment will be described. Now each resistance R1~ RFour
The resistance value of R1~ RFourAnd R1= R2= Rf, R3= RFour= Rsage,
Reference voltage VrefIs 0V and the current value of the current source 5 is I0And
Then, the voltage of the normal output terminal 3 is changed to VOUTOf the inverted output terminal 4
Voltage is V ▲ ▼, and forward of imaginary short
Invert the input voltage to V1AndResistance RFourThe current flowing through IFourAndResistance R2The current flowing through I2AndSet the current value of the current source 5 to I0Then I0= I2+ IFour (6) Also, output V of the forward / reverse output terminals 3 and 4OUTAnd V ▲
Is a balanced outputFrom equations (4), (5), and (6)From equations (3) and (8)From equations (7) and (9) And output VOUT, V ▲ ▼ is the resistance value Rs, I.e.
Anti-R3And RFourIt becomes irrelevant to the resistance value ofsIs in and out
It does not affect the force relation in the formula. Also, here is equation (3)?
As can be seen, the input voltage ratio is Rs/ (Rs+ R
f) And the resistance R3, RFourResistance value RSResistance R1, R2Resistance value R
fThe smaller the input voltage deviation, the smaller
Become

第2図は本発明の他の実施例の平衡増幅器の回路図であ
る。
FIG. 2 is a circuit diagram of a balanced amplifier according to another embodiment of the present invention.

本実施例では、第1図の実施例における電流源5の位置
を換えたものであり、この定電流源5′を正電源端子1
と演算増幅器A1の負入力端子−との間に入れている。動
作原理は第1図の実施例の場合と同様であるので省略す
る。
In this embodiment, the position of the current source 5 in the embodiment of FIG. 1 is changed, and this constant current source 5'is connected to the positive power supply terminal 1
It has put between - the negative input terminal of the operational amplifier A 1 and. The principle of operation is the same as in the embodiment of FIG.

この第2図の実施例では、制御用の電流源がはき出し型
の場合にも応用でき利点がある。
The embodiment shown in FIG. 2 has an advantage that it can be applied to the case where the current source for control is of a bare type.

〔発明の効果〕 以上説明したように、本発明は従来に比べ2本の抵抗を
追加するだけで平衡増幅器の入力端電位変動を小さくす
ることができ、平衡増幅器の同相入力電圧範囲が小さく
て済むだけでなく、その結果この平衡増幅器のCMRR特性
による誤差を小さくできるという効果がある。又この平
衡増幅器の入力端に接続される電流源の出力ダイナミッ
クレンジが小さくて済み、ひいては上記電流源の内部等
価抵抗(出力インピーダンス)による誤差を小さくでき
るという効果もある。
[Effects of the Invention] As described above, according to the present invention, the fluctuation of the input terminal potential of the balanced amplifier can be reduced by adding two resistors, and the common-mode input voltage range of the balanced amplifier can be reduced. Not only is this done, but as a result, the error due to the CMRR characteristics of this balanced amplifier can be reduced. In addition, the output dynamic range of the current source connected to the input terminal of the balanced amplifier can be small, and the error due to the internal equivalent resistance (output impedance) of the current source can be reduced.

【図面の簡単な説明】[Brief description of drawings]

第1図は本発明の一実施例の回路図、第2図は本発明の
他の実施例の回路図、第3図は従来の平衡増幅器のバイ
アス回路図である。 1……正電源端子、2……負電源端子、3……正転出力
端、4……反転出力端、A1……平衡増幅器、I0……制御
電流源、Vref……基準電圧源、R1〜R4……抵抗、5,5′
……電流源。
FIG. 1 is a circuit diagram of an embodiment of the present invention, FIG. 2 is a circuit diagram of another embodiment of the present invention, and FIG. 3 is a bias circuit diagram of a conventional balanced amplifier. 1 ...... positive power supply terminal, 2 ...... negative power supply terminal, 3 ...... noninverting output terminal, 4 ...... inverting output terminal, A 1 ...... balanced amplifier, I 0 ...... controlled current source, V ref ...... reference voltage Source, R 1 to R 4 ... Resistance, 5,5 ′
...... Current source.

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】正および負の入力端子と正転および反転出
力端子とをもつ増幅器と、前記増幅器の前記負入力端子
と前記正転出力端子との間に接続された第1の抵抗と前
記増幅器の前記正入力端子と前記反転出力端子との間に
接続された第2の抵抗と、一端が前記増幅器の前記負入
力端子に接続された第3の抵抗と、一端が前記増幅器の
前記正入力端子に接続された第4の抵抗と、前記増幅器
の前記正転又は反転入力端子に接続された電流源と、前
記第3と第4の抵抗の他端を相互接続して基準電圧を与
える手段とを有し、前記電流源から前記入力端子に電流
を入力し、前記増幅器の前記正転および反転出力端子か
ら電圧を出力することを特徴とする平衡増幅器。
1. An amplifier having positive and negative input terminals and non-inverted and inverted output terminals; a first resistor connected between the negative input terminal and the non-inverted output terminal of the amplifier; A second resistor connected between the positive input terminal and the inverting output terminal of the amplifier, a third resistor having one end connected to the negative input terminal of the amplifier, and one end of the positive resistor of the amplifier. A fourth resistor connected to the input terminal, a current source connected to the non-inverting or inverting input terminal of the amplifier, and the other ends of the third and fourth resistors are interconnected to provide a reference voltage. Means for inputting a current from the current source to the input terminal and outputting a voltage from the non-inverting and inverting output terminals of the amplifier.
JP62107404A 1987-04-28 1987-04-28 Balanced amplifier Expired - Lifetime JPH07105671B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62107404A JPH07105671B2 (en) 1987-04-28 1987-04-28 Balanced amplifier

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62107404A JPH07105671B2 (en) 1987-04-28 1987-04-28 Balanced amplifier

Publications (2)

Publication Number Publication Date
JPS63269813A JPS63269813A (en) 1988-11-08
JPH07105671B2 true JPH07105671B2 (en) 1995-11-13

Family

ID=14458289

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62107404A Expired - Lifetime JPH07105671B2 (en) 1987-04-28 1987-04-28 Balanced amplifier

Country Status (1)

Country Link
JP (1) JPH07105671B2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2684837B2 (en) * 1990-10-08 1997-12-03 日本電気株式会社 Differential amplifier circuit

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS546355B2 (en) * 1974-07-13 1979-03-27
JPS5616310A (en) * 1979-07-19 1981-02-17 Matsushita Electric Ind Co Ltd Differential amplifier

Also Published As

Publication number Publication date
JPS63269813A (en) 1988-11-08

Similar Documents

Publication Publication Date Title
US7064535B2 (en) Measurement circuit with improved accuracy
GB2122831A (en) Voltage to current converting amplifiers
JPH07105671B2 (en) Balanced amplifier
JP2710507B2 (en) Amplifier circuit
JPH11186859A (en) Voltage-current conversion circuit
JP3129071B2 (en) Voltage controlled amplifier
SU1478292A2 (en) Amplifier
JPS582085A (en) Hall element device
JPS59815Y2 (en) Voltage/current conversion circuit
JPH01213578A (en) Resistance voltage converting circuit
JPS6214727Y2 (en)
JP3043044B2 (en) D / A conversion circuit
SU1335965A1 (en) Voltage-to-current converter
JPH0122400Y2 (en)
RU2054790C1 (en) Measuring operational amplifier
JPH0233387Y2 (en)
JPH0611625Y2 (en) Amplifier for strain gauge
JPS61226882A (en) Voltage synthesizing circuit
JPH0518677Y2 (en)
JPS63138270A (en) Difference voltage detecting circuit
SU1714335A1 (en) Strain sensor
SU851423A1 (en) Logarithmic amplifier
JPH04328905A (en) Differential amplifier circuit
JPS6114173Y2 (en)
SU1101851A1 (en) Function generator

Legal Events

Date Code Title Description
EXPY Cancellation because of completion of term
FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20071113

Year of fee payment: 12