JPS6114173Y2 - - Google Patents
Info
- Publication number
- JPS6114173Y2 JPS6114173Y2 JP14483979U JP14483979U JPS6114173Y2 JP S6114173 Y2 JPS6114173 Y2 JP S6114173Y2 JP 14483979 U JP14483979 U JP 14483979U JP 14483979 U JP14483979 U JP 14483979U JP S6114173 Y2 JPS6114173 Y2 JP S6114173Y2
- Authority
- JP
- Japan
- Prior art keywords
- voltage
- resistor
- load
- input terminal
- inverting
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 230000008054 signal transmission Effects 0.000 claims description 9
- 238000006243 chemical reaction Methods 0.000 claims description 5
- 230000005540 biological transmission Effects 0.000 description 7
- 238000010586 diagram Methods 0.000 description 7
- 230000003321 amplification Effects 0.000 description 2
- 238000003199 nucleic acid amplification method Methods 0.000 description 2
- 230000002238 attenuated effect Effects 0.000 description 1
Landscapes
- Amplifiers (AREA)
- Cable Transmission Systems, Equalization Of Radio And Reduction Of Echo (AREA)
Description
【考案の詳細な説明】
本考案は負性出力抵抗をもつた信号伝送回路に
係り、極めて簡単な回路構成で増幅器の出力抵抗
を負荷抵抗としうる信号伝送回路を提供すること
を目的とする。[Detailed Description of the Invention] The present invention relates to a signal transmission circuit having a negative output resistance, and an object thereof is to provide a signal transmission circuit that can use the output resistance of an amplifier as a load resistance with an extremely simple circuit configuration.
第１図は従来の信号伝送回路の一例の回路図を
示す。同図中、入力端子１に入来した入力電圧ｅ
i1は演算増幅器２の非反転入力端子に印加され、
ここで非反転増幅された後、伝送路インピーダン
スZ1，Z2の伝送路を通して負荷３に供給される。
抵抗r1，r2は演算増幅器２の利得を決定する抵抗
である。 FIG. 1 shows a circuit diagram of an example of a conventional signal transmission circuit. In the figure, the input voltage e entering the input terminal 1
i1 is applied to the non-inverting input terminal of operational amplifier 2,
After being non-invertingly amplified here, the signal is supplied to the load 3 through a transmission line with transmission line impedances Z 1 and Z 2 .
Resistors r 1 and r 2 are resistors that determine the gain of the operational amplifier 2.
上記の構成の従来回路によれば、第１図に，
で夫々示す演算増幅器２の出力端子と、伝送路
インピーダンスZ2の伝送路及び接地間の接続点と
の間の電圧ｅp1は、伝送路インピーダンスZ1，Z2
の影響を受けないが、負荷３に印加される電圧ｅ
pL1は伝送路インピーダンスZ1，Z2の影響を受
け、次式のようになる。 According to the conventional circuit with the above configuration, as shown in FIG.
The voltage e p1 between the output terminal of the operational amplifier 2 and the connection point between the transmission line and the ground of the transmission line impedance Z 2 is equal to the transmission line impedance Z 1 , Z 2 .
is not affected by the voltage e applied to the load 3
pL1 is affected by the transmission path impedances Z 1 and Z 2 and is expressed as follows.
ｅpL1＝ＺＬ１／Ｚ１＋Ｚ２＋ＺＬ１・ｅp1(1)
但し、(1)式中ＺL1は負荷３のインピーダンスで
ある。 e pL1 =Z L1 /Z 1 +Z 2 +Z L1 ·e p1 (1) However, in formula (1), Z L1 is the impedance of the load 3.
従つて、上記の従来回路によれば、ＺL1に対し
てZ1，Z2が無視し得る程度に小さくない場合、入
力電圧波形が負荷３に正確に伝送されないので、
何らかの方法でZ1，Z2による影響を取り除かなけ
ればならなかつた。 Therefore, according to the above conventional circuit, if Z 1 and Z 2 are not negligibly small with respect to Z L1 , the input voltage waveform will not be accurately transmitted to the load 3.
The influence of Z 1 and Z 2 had to be removed in some way.
そこで、従来より第２図に示す如く伝送路イン
ピーダンスZ1，Z2のうち直流抵抗分の影響を無く
す信号伝送回路が知られている。同図中、第１図
と同一構成部分には同一符号を付してその説明を
省略する。第２図において、負荷３に流れる電流
は抵抗ｒsにより電圧に変換された後抵抗r3を介
して帰還抵抗r4を有する演算増幅器４の反転入力
端子に印加され、ここで反転増幅される。この演
算増幅器４の出力電圧は抵抗r5を介して演算増幅
器２の反転入力端子へ供給され、正帰還ループを
形成する。これにより、演算増幅器２の出力端子
より見た出力抵抗は負性抵抗を示す。従つて、入
力端子１に入来した入力電圧ｅi1は略正確に負荷
３に伝送される。 Therefore, as shown in FIG. 2, a signal transmission circuit that eliminates the influence of the direct current resistance of the transmission path impedances Z 1 and Z 2 has been known. In the figure, the same components as those in FIG. 1 are given the same reference numerals, and the explanation thereof will be omitted. In Figure 2, the current flowing through a load 3 is converted into a voltage by a resistor r s and then applied to an inverting input terminal of an operational amplifier 4 having a feedback resistor r 4 via a resistor r 3 where it is inverted and amplified. . The output voltage of the operational amplifier 4 is supplied to the inverting input terminal of the operational amplifier 2 via a resistor r5 , forming a positive feedback loop. As a result, the output resistance seen from the output terminal of the operational amplifier 2 exhibits negative resistance. Therefore, the input voltage e i1 entering the input terminal 1 is transmitted to the load 3 almost exactly.
しかるに、上記の第２図示の従来回路は、反転
増幅のための演算増幅器４及びその帰還抵抗r4等
を必要とし、回路構成が複雑であるという欠点が
あつた。 However, the conventional circuit shown in FIG. 2 requires an operational amplifier 4 for inverting amplification, its feedback resistor r4, etc., and has a drawback that the circuit configuration is complicated.
本考案は上記の欠点を除去したものであり、以
下第３図及び第４図と共にその一実施例について
説明する。 The present invention eliminates the above-mentioned drawbacks, and an embodiment thereof will be described below with reference to FIGS. 3 and 4.
第３図は本考案になる信号伝送回路の一実施例
の回路図を示す。同図中、入力端子５は抵抗値
R1の抵抗を介して演算増幅器６の反転入力端子
に接続されている。この演算増幅器６の出力端子
は抵抗値R2の抵抗を介して演算増幅器６の反転
入力端子に接続される一方、インピーダンスＺL
の負荷７及び抵抗値Ｒsの抵抗を夫々直列に介し
て接地されている。また抵抗値Ｒsの抵抗と並列
に抵抗値R3，R4の抵抗よりなる直列回路が接続
されており、更にR3，R4の接続点は演算増幅器
６の非反転入力端子に接続されている。なお、Ｒ
s≪R3＋R4なる関係に選定されている。 FIG. 3 shows a circuit diagram of an embodiment of the signal transmission circuit according to the present invention. In the same figure, input terminal 5 has a resistance value
It is connected to the inverting input terminal of the operational amplifier 6 via the resistor R1 . The output terminal of this operational amplifier 6 is connected to the inverting input terminal of the operational amplifier 6 via a resistor with a resistance value R 2 , while the impedance Z L
is connected to the ground through a load 7 and a resistor having a resistance value R s in series. Further, a series circuit consisting of resistors with resistance values R 3 and R 4 is connected in parallel with the resistance value R s , and the connection point of R 3 and R 4 is connected to the non-inverting input terminal of the operational amplifier 6. ing. In addition, R
The relationship is selected as s ≪R 3 + R 4 .
上記の構成回路において、演算増幅器６は理想
的な増幅器で、無負荷時の利得Ａvpが
Ａvp＝−Ｒ２／Ｒ１ (2)
で与えられることは周知の通りである。またＲs
の抵抗は負荷７に流れる電流をそれに比例した電
圧に変換するための抵抗であり、R3，R4の抵抗
値をもつ抵抗は、Ｒsの抵抗に発生した電圧を分
圧して演算増幅器６の非反転入力端子に加えるた
めの減衰器の作用を行なう。ここで、演算増幅器
６の非反転入力端子の入力インピーダンスは
R3，R4に比し充分高いので、Ｒsに発生した電圧
はR3，R4のみで減衰され演算増幅器６の非反転
入力端子に印加される。 In the above configuration circuit, it is well known that the operational amplifier 6 is an ideal amplifier, and the gain A vp at no load is given by A vp =-R 2 /R 1 (2). Also R s
The resistor 7 is a resistor for converting the current flowing through the load 7 into a voltage proportional to it, and the resistors having resistance values R 3 and R 4 divide the voltage generated in the resistor R s and apply it to the operational amplifier 6. It acts as an attenuator to be applied to the non-inverting input terminal of . Here, the input impedance of the non-inverting input terminal of the operational amplifier 6 is
Since it is sufficiently higher than R 3 and R 4 , the voltage generated at R s is attenuated only by R 3 and R 4 and applied to the non-inverting input terminal of the operational amplifier 6.
いま、入力端子５に入来する電圧をｅi、負荷
７に印加される電圧をｅpとすると、第３図示の
回路の伝達関数Ａvは次式で表わされる。 Now, assuming that the voltage entering the input terminal 5 is e i and the voltage applied to the load 7 is e p , the transfer function A v of the circuit shown in FIG. 3 is expressed by the following equation.
Ａv＝ｅｐ／ｅｉ (3)
ここで、第３図に示す如く電流ｉa，ｉp、電圧
ｅa，ｅbを規定すると、
ｉp＝ｅｐ／ＺＬ (4)
ｅb＝Ｒs・ｉp・Ｒ４／Ｒ３＋Ｒ４ (5)
ｉa＝ｅｉ−ｅｂ／Ｒ１ (6)
ｅa＝ｅb−ｉaR2 (7)
ｅp＝ｅa−ｉpR3 (8)
＝ｅb−ｉaR2−ｉpＲs
＝ｅｐ／ＺＬ｛ＲsＲ４／Ｒ３＋Ｒ４＋Ｒｓ／Ｒ１
Ｒ２Ｒ４／（Ｒ３＋Ｒ４）
−Ｒs｝−Ｒ２ｅｉ／Ｒ１ (9)
従つて、(9)式を整理すると、Ａvは
で表わされる。 A v =e p /e i (3) Here, if the currents i a , i p and the voltages e a , e b are defined as shown in Fig. 3, then i p =e p /Z L (4) e b =R s・i p・R 4 /R 3 +R 4 (5) i a =e i −e b /R 1 (6) e a =e b −i a R 2 (7) e p =e a − i p R 3 (8) = e b −i a R 2 − i p R s = e p /Z L {R s R 4 /R 3 +R 4 +R s /R 1
R 2 R 4 /(R 3 +R 4 ) −R s }−R 2 e i /R 1 (9) Therefore, rearranging equation (9), A v is It is expressed as
次に(2)式に示す無負荷時の伝達関数Ａv0と(10)式
に示す負荷７を接続したときの伝達関数Ａvとに
より、負荷端より見た出力抵抗Ｒpを導く。Ａvと
Ａv0との間には
Ａv＝Ａv0ＺＬ／Ｒｐ＋ＺＬ (11)
なる関係があるので、出力抵抗Ｒpは(11)式より次
式で表わされる。 Next, the output resistance R p seen from the load end is derived from the transfer function A v0 at no load shown in equation (2) and the transfer function A v when the load 7 is connected shown in equation (10). Since there is a relationship between A v and A v0 as follows: A v =A v0 Z L /R p +Z L (11), the output resistance R p is expressed by the following equation from equation (11).
Ｒp＝Ａｖ０−Ａｖ／ＡｖＺL (12)
従つて、〓式に(2)式，(10)式を代入すると
Ｒp＝−｛（Ｒ１＋Ｒ２）／Ｒ１・Ｒ４／（Ｒ３＋Ｒ
４）−１｝Ｒs(13)
を得る。すなわち、出力抵抗ＲpはＲ４（Ｒ１＋Ｒ２）
／Ｒ１（Ｒ３＋Ｒ４）＞
１の条件で負荷抵抗を示す。 R p =A v0 -A v /A v Z L (12) Therefore, by substituting equations (2) and (10) into the formula, R p =-{(R 1 + R 2 )/R 1・R 4 /(R 3 +R
4 )-1} Obtain R s (13). That is, the output resistance R p is R 4 (R 1 + R 2 )
The load resistance is shown under the condition of /R 1 (R 3 +R 4 )>1.
第４図は出力抵抗Ｒpに着目した第３図の等価
回路図で、Ｅpは無負荷時の出力電圧を示す。 FIG. 4 is an equivalent circuit diagram of FIG. 3 focusing on the output resistance R p , where E p indicates the output voltage under no load.
Ｅp＝Ａv0×ｅi＝−Ｒ２／Ｒ１ｅi (14) なる関係がある。 There is the following relationship: E p =A v0 ×e i =−R 2 /R 1 e i (14).
（13）式から明らかなように、出力抵抗Ｒpは
R3とR4とを夫々適当に選択することにより、−Ｒ２／Ｒ
１
ＲsからＲsまでの間で任意の値を選ぶことができ
る。すなわち、分圧比Ｒ４／Ｒ３＋Ｒ４をＫとすると、
Ｋ
＝Ｒ１／Ｒ１＋Ｒ２のときＲpが０となり、これを境に
Ｋ＞
Ｒ１／Ｒ１＋Ｒ２とするとＲp＜０となり、第３図示の
回路
は負性出力抵抗を持つこととなる。 As is clear from equation (13), the output resistance R p is
By appropriately selecting R 3 and R 4 , −R 2 /R
Any value between 1Rs and Rs can be selected. That is, if the partial pressure ratio R 4 /R 3 +R 4 is K,
When K = R 1 /R 1 +R 2 , R p becomes 0, and if K > R 1 /R 1 + R 2 from this point, R p <0, and the circuit shown in the third figure has a negative output resistance. That will happen.
本実施例によれば、反転増幅用の演算増幅器４
を不要にでき、回路構成が簡単で低コストにでき
る。 According to this embodiment, the operational amplifier 4 for inverting amplification
This eliminates the need for circuit configuration, making the circuit configuration simple and low cost.
上述の如く、本考案になる信号伝送回路は、反
転増幅器と、この反転増幅器の負荷に流れる電流
に比例した電圧を得る電流−電圧変換用抵抗と、
この電流−電圧変換用抵抗の出力電圧を所定の範
囲内の分圧比で分圧して上記反転増幅器の非反転
入力端子に印加する分圧用抵抗とより構成したた
め、極めて簡単な回路構成で出力抵抗を負性抵抗
とすることができ、また安価に構成しえ、負性出
力抵抗をもつので反転増幅器と負荷との間の信号
伝送路インピーダンスの影響を殆ど受けることな
く入力信号波形を略正確に負荷に伝送できる等の
特長を有するものである。 As described above, the signal transmission circuit according to the present invention includes an inverting amplifier, a current-voltage conversion resistor that obtains a voltage proportional to the current flowing through the load of the inverting amplifier,
Since the output voltage of this current-voltage conversion resistor is divided by a voltage division ratio within a predetermined range and is then applied to the non-inverting input terminal of the inverting amplifier, the output resistance can be adjusted with an extremely simple circuit configuration. It can be made into a negative resistance, and can be constructed at low cost.Since it has a negative output resistance, the input signal waveform can be loaded almost accurately without being affected by the signal transmission path impedance between the inverting amplifier and the load. It has features such as being able to transmit data to
第１図及び第２図は夫々従来回路の各例を示す
回路図、第３図は本考案回路の一実施例を示す回
路図、第４図は第３図示回路の出力抵抗に着目し
た等価回路図である。
１，５……入力端子、２……非反転増幅器用演
算増幅器、３，７……負荷、４，６……反転増幅
器用演算増幅器、Ｒs……電流−電圧変換用抵抗
の抵抗値、R3，R4……分圧用抵抗の抵抗値。
1 and 2 are circuit diagrams showing respective examples of conventional circuits, FIG. 3 is a circuit diagram showing an example of the circuit of the present invention, and FIG. 4 is an equivalent circuit diagram focusing on the output resistance of the circuit shown in FIG. 3. It is a circuit diagram. 1, 5... Input terminal, 2... Operational amplifier for non-inverting amplifier, 3, 7... Load, 4, 6... Operational amplifier for inverting amplifier, R s ... Resistance value of current-voltage conversion resistor, R 3 , R 4 ...Resistance value of voltage dividing resistor.
Claims (1)
転増幅器の負荷に流れる電流に比例した電圧を
得る電流−電圧変換用抵抗と、該電流−電圧変
換用抵抗の出力電圧を所定の範囲内の分圧比で
分圧して該反転増幅器の非反転入力端子に印加
する分圧用抵抗とよりなり、負荷出力抵抗を持
たせるよう構成した信号伝送回路。 ２ 前記反転増幅器は、前記入力信号が入力され
る一の入力端子と反転入力端子との間に接続し
た抵抗値R1なる第１の抵抗と、出力端子と前
記反転入力端子との間に接続した抵抗値R2な
る第２の抵抗とを備えて構成され、前記所定の
範囲内の分圧比は、前記反転増幅器の無負荷時
の利得が−（R2／R1）であるとき、R1／（R1＋
R2）より大なる範囲の分圧比である実用新案登
録請求の範囲第１項記載の信号伝送回路。[Claims for Utility Model Registration] 1. An inverting amplifier that inverts and amplifies an input signal, a current-voltage conversion resistor that obtains a voltage proportional to the current flowing through the load of the inverting amplifier, and an output of the current-voltage conversion resistor. A signal transmission circuit comprising a voltage dividing resistor that divides a voltage at a voltage dividing ratio within a predetermined range and applies the divided voltage to a non-inverting input terminal of the inverting amplifier, and is configured to have a load output resistance. 2 The inverting amplifier has a first resistor having a resistance value R1 connected between one input terminal to which the input signal is input and the inverting input terminal, and a first resistor connected between the output terminal and the inverting input terminal. and a second resistor having a resistance value R2 , and the voltage division ratio within the predetermined range is R2 when the gain of the inverting amplifier at no load is -( R2 / R1 ). 1 / (R 1 +
R2 ) The signal transmission circuit according to claim 1, which has a voltage division ratio in a larger range.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14483979U JPS6114173Y2 (en) | 1979-10-19 | 1979-10-19 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14483979U JPS6114173Y2 (en) | 1979-10-19 | 1979-10-19 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5663155U JPS5663155U (en) | 1981-05-27 |
| JPS6114173Y2 true JPS6114173Y2 (en) | 1986-05-02 |
Family
ID=29376026
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14483979U Expired JPS6114173Y2 (en) | 1979-10-19 | 1979-10-19 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6114173Y2 (en) |
-
1979
- 1979-10-19 JP JP14483979U patent/JPS6114173Y2/ja not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5663155U (en) | 1981-05-27 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JPS626722Y2 (en) | ||
| JPS6114173Y2 (en) | ||
| JP3404209B2 (en) | Transimpedance amplifier circuit | |
| JPH0344103A (en) | Voltage/obsolute value current converter circuit | |
| JPH01318308A (en) | Logarithmic amplifier | |
| JPH06103328B2 (en) | Ratio measuring circuit and device | |
| US6580317B1 (en) | Low-noise broadband amplifier device having negative feedback via a controlled current source, and use of the amplifier device | |
| JPS6228606B2 (en) | ||
| JPH0635540Y2 (en) | Differential amplifier | |
| US4035738A (en) | Low noise amplifier | |
| JPH0310243B2 (en) | ||
| JPS6121866Y2 (en) | ||
| KR20000010922A (en) | Voltage-to-current converter with error correction | |
| JP2542245B2 (en) | Voltage output circuit | |
| RU2054790C1 (en) | Measuring operational amplifier | |
| JPS6238336Y2 (en) | ||
| JPS58117707A (en) | Common mode signal reducing circuit | |
| KR0135461B1 (en) | Amplifying circuit with high input impedance | |
| JPH054049Y2 (en) | ||
| JPH0233387Y2 (en) | ||
| JPH0611625Y2 (en) | Amplifier for strain gauge | |
| JPH06109678A (en) | Humidity detection circuit | |
| JPS584327Y2 (en) | amplifier circuit | |
| JPH0222739Y2 (en) | ||
| JPH0494203A (en) | Amplifier circuit |