JPS6243561B2 - - Google Patents

Info

Publication number
JPS6243561B2
JPS6243561B2 JP54134031A JP13403179A JPS6243561B2 JP S6243561 B2 JPS6243561 B2 JP S6243561B2 JP 54134031 A JP54134031 A JP 54134031A JP 13403179 A JP13403179 A JP 13403179A JP S6243561 B2 JPS6243561 B2 JP S6243561B2
Authority
JP
Japan
Prior art keywords
signal
balanced
modulation circuit
level
balanced modulation
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP54134031A
Other languages
Japanese (ja)
Other versions
JPS5657313A (en
Inventor
Kenzo Tanabe
Masashi Sugano
Junji Suzuki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP13403179A priority Critical patent/JPS5657313A/en
Priority to DE19803038995 priority patent/DE3038995A1/en
Priority to CA000362445A priority patent/CA1155927A/en
Publication of JPS5657313A publication Critical patent/JPS5657313A/en
Publication of JPS6243561B2 publication Critical patent/JPS6243561B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03GCONTROL OF AMPLIFICATION
    • H03G3/00Gain control in amplifiers or frequency changers without distortion of the input signal
    • H03G3/20Automatic control
    • H03G3/30Automatic control in amplifiers having semiconductor devices
    • H03G3/3036Automatic control in amplifiers having semiconductor devices in high-frequency amplifiers or in frequency-changers
    • H03G3/3042Automatic control in amplifiers having semiconductor devices in high-frequency amplifiers or in frequency-changers in modulators, frequency-changers, transmitters or power amplifiers
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03CMODULATION
    • H03C1/00Amplitude modulation
    • H03C1/52Modulators in which carrier or one sideband is wholly or partially suppressed
    • H03C1/54Balanced modulators, e.g. bridge type, ring type or double balanced type
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03DDEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
    • H03D7/00Transference of modulation from one carrier to another, e.g. frequency-changing
    • H03D7/14Balanced arrangements
    • H03D7/1408Balanced arrangements with diodes
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03DDEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
    • H03D7/00Transference of modulation from one carrier to another, e.g. frequency-changing
    • H03D7/14Balanced arrangements
    • H03D7/1425Balanced arrangements with transistors
    • H03D7/1433Balanced arrangements with transistors using bipolar transistors
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03DDEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
    • H03D7/00Transference of modulation from one carrier to another, e.g. frequency-changing
    • H03D7/14Balanced arrangements
    • H03D7/1425Balanced arrangements with transistors
    • H03D7/145Balanced arrangements with transistors using a combination of bipolar transistors and field-effect transistors
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03DDEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
    • H03D7/00Transference of modulation from one carrier to another, e.g. frequency-changing
    • H03D7/14Balanced arrangements
    • H03D7/1425Balanced arrangements with transistors
    • H03D7/1458Double balanced arrangements, i.e. where both input signals are differential
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03DDEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
    • H03D7/00Transference of modulation from one carrier to another, e.g. frequency-changing
    • H03D7/14Balanced arrangements
    • H03D7/1425Balanced arrangements with transistors
    • H03D7/1491Arrangements to linearise a transconductance stage of a mixer arrangement
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03DDEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
    • H03D2200/00Indexing scheme relating to details of demodulation or transference of modulation from one carrier to another covered by H03D
    • H03D2200/0001Circuit elements of demodulators
    • H03D2200/0033Current mirrors
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03DDEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
    • H03D2200/00Indexing scheme relating to details of demodulation or transference of modulation from one carrier to another covered by H03D
    • H03D2200/0041Functional aspects of demodulators
    • H03D2200/0043Bias and operating point

Description

【発明の詳細な説明】 本発明は信号受信機のフロントエンド部のミキ
サー段に使用する平衡変調器に関するものであ
り、その目的とするところは信号受信機の広範囲
の入力信号レベルに応じて混変調ひずみ、相互変
調ひずみの発生が少なく、かつ、小さい入力信号
レベルに対して低ノイズ特性を有する二重平衡型
の平衡変調器を提供することにある。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a balanced modulator for use in a mixer stage in the front end of a signal receiver, the purpose of which is to provide a balanced modulator for use in a mixer stage in the front end of a signal receiver. It is an object of the present invention to provide a double-balanced balanced modulator that generates little modulation distortion and intermodulation distortion and has low noise characteristics for small input signal levels.

一般によく知られている二重平衡変調回路を第
1図に示す。第1図において、トランジスタ
Q1,Q2、トランジスタQ3,Q4、トランジスタ
Q5,Q6はエミツタ結合型の差動対トランジスタ
であり、二重平衡変調回路の基本部を構成する。
また、トランジスタQ7,Q8はトランジスタQ5
Q6に対する定電流用トランジスタであり、その
電流値はカレントミラー用ダイオードD1の電流
値から定められる。抵抗R1,R2,R3は上記カレ
ントミラーの動作をより安定化するためのもので
ある。入力端子1,2は通常局部発振信号の差動
入力端子であり、3,4は受信信号の差動入力端
子、5は差動対トランジスタQ5,Q6のバイアス
電流を定めるための外部抵抗および電源の接続端
子、6はアース端子、7,8はこの平衡変調回路
の差動出力端子、そして、9,10はこの平衡変
調回路の周波数変換コンダクタンスを調整するた
めの外部抵抗接続端子である。第1図における平
衡変調回路の主要な特性は周波数変換コンダクタ
ンス、雑音指数、および最大許容信号入力である
が、これらのは、端子9,10に接続する外部抵
抗の抵抗値、差動対トランジスタQ5,Q6のバイ
アス電流値、および端子1,2に加えられる局部
発振信号のレベルにより決定される。すなわち、
周波数変換コンダクタンスgmは、端子9,10
間に接続する外部抵抗の抵抗値をREとすれば、
ほぼ次式で与えられる。
A generally well-known double balanced modulation circuit is shown in FIG. In Figure 1, the transistor
Q 1 , Q 2 , transistor Q 3 , Q 4 , transistor
Q 5 and Q 6 are emitter-coupled differential pair transistors and constitute the basic part of the double-balanced modulation circuit.
Also, transistors Q 7 and Q 8 are transistors Q 5 ,
It is a constant current transistor for Q 6 , and its current value is determined from the current value of the current mirror diode D 1 . The resistors R 1 , R 2 , and R 3 are used to further stabilize the operation of the current mirror. Input terminals 1 and 2 are normally differential input terminals for local oscillation signals, 3 and 4 are differential input terminals for received signals, and 5 is an external resistor for determining the bias current of differential pair transistors Q 5 and Q 6 . and a power supply connection terminal, 6 is a ground terminal, 7 and 8 are differential output terminals of this balanced modulation circuit, and 9 and 10 are external resistance connection terminals for adjusting the frequency conversion conductance of this balanced modulation circuit. . The main characteristics of the balanced modulation circuit in FIG. 5 and Q6 , and the level of the local oscillation signal applied to terminals 1 and 2. That is,
Frequency conversion conductance gm is terminal 9, 10
If the resistance value of the external resistor connected between is R E ,
It is approximately given by the following equation.

gm=k1/R ………(1) ただし、kは、局部発振信号の差動入力端子
1,2に加えられる局部注入信号レベルに依存す
る定数であるが、この注入信号レベルが十分大き
な値であれば一定値に収れんし、4/πとなる。ま
た雑音指数は上記の局発注入信号レベル、端子
9,10間に接続する外部抵抗および端子3,4
に接続される受信信号の信号源インピーダンスな
どにも影響されるが、差動対トランジスタQ5
Q6のバイアス電流に大きく影響され、通常、大
きなバイアス電流を採用すると雑音指数が劣化す
ることが知られている。さらに、この平衡変調回
路への最大許容信号入力のレベルは差動対トラン
ジスタQ5,Q6のバイアス電流および端子9,1
0間に接続される外部抵抗により定められ、差動
対トランジスタQ5,Q6が飽和またはカツトオフ
という非線形領域に入らない状態で動作しうる場
合の差動端子3,4に加えうる信号入力レベル、
すなわち最大許容信号入力レベルの振幅値Vsnax
は次式で与えられる。
gm=k1/R E ......(1) However, k is a constant that depends on the local injection signal level applied to the differential input terminals 1 and 2 of the local oscillation signal, but this injection signal level is sufficiently large. value, it converges to a constant value and becomes 4/π. In addition, the noise figure is the above local injection signal level, the external resistance connected between terminals 9 and 10, and the terminals 3 and 4.
Although it is affected by the signal source impedance of the received signal connected to the differential pair transistor Q 5 ,
It is greatly affected by the bias current of Q6 , and it is known that the noise figure usually deteriorates when a large bias current is used. Furthermore, the maximum allowable signal input level to this balanced modulation circuit is determined by the bias current of the differential pair transistors Q 5 and Q 6 and the terminals 9 and 1.
The signal input level that can be applied to the differential terminals 3 and 4 when the differential pair transistors Q 5 and Q 6 can operate without entering the nonlinear region of saturation or cut-off, determined by the external resistor connected between ,
In other words, the amplitude value of the maximum allowable signal input level V snax
is given by the following equation.

snax=RE・IB ………(2) ただし、REは(1)式と同じもの IBは差動対トランジスタQ5、およびQ6のバイ
アス電流値であり、ここではトランジスタQ5
Q6に等しいバイアス電流IBが流れているものと
する。
V snax = R E · I B ......(2) However, R E is the same as in equation (1). I B is the bias current value of the differential pair transistors Q 5 and Q 6 , and here, the transistor Q Five ,
Assume that a bias current I B equal to Q 6 is flowing.

以上で二重平衡変調回路を信号受信機のフロン
トエンド部ミキサーとして利用した場合の主要な
特性について説明した。
The main characteristics when the double-balanced modulation circuit is used as a front-end mixer of a signal receiver have been explained above.

ところで、信号受信機フロントエンド部のミキ
サーとして要望される性能は受信機の感度をよく
するために周波数変数コンダクタンスが大きく雑
音指数が低いこと、および混変調ひずみ、相互変
調ひずみを小さくするためにできるだけ最大許容
信号入力が大きいことであるが、上述の平衡変調
回路の諸特性から判断すれば上述の要望される性
能をすべて満足させることは困難であることがわ
かる。すなわち、周波数変換コンダクタンスを大
きくしようとすれば(1)式より明らかなようにRE
を小さくすることが必要となるが、この時、(2)式
で明らかなように最大許容信号入力レベルが劣化
する。したがつて、周波数変換コンダクタンスを
小さくしないで、最大許容信号入力レベルを増加
させるためには、(2)式で示すバイアス電流を増加
させることが望ましいが、この場合、雑音指数を
一般には劣化させてしまうという問題があつた。
By the way, the required performance for a mixer in the front end section of a signal receiver is to have a large frequency variable conductance and a low noise figure in order to improve the sensitivity of the receiver, and to minimize intermodulation distortion and intermodulation distortion as much as possible. Although the maximum allowable signal input is large, judging from the various characteristics of the balanced modulation circuit described above, it is clear that it is difficult to satisfy all of the above-mentioned desired performances. In other words, if we try to increase the frequency conversion conductance, R E
It is necessary to reduce the value, but at this time, the maximum allowable signal input level deteriorates, as is clear from equation (2). Therefore, in order to increase the maximum allowable signal input level without reducing the frequency conversion conductance, it is desirable to increase the bias current shown in equation (2), but in this case, the noise figure will generally deteriorate. I had a problem with it.

本発明は受信機フロントエンド部のミキサーと
して二重平衡変調回路を用いた場合の上述の欠点
を除去することをねらいとするものであり、受信
機への信号入力レベルが小さなときは上述の周波
数変換コンダクタンス、雑音指数を重視してこれ
らの特性が良好な状態を維持するように(1)、(2)式
で示す諸パラメータを設定し、受信機への信号入
力レベルが大きなときは(2)式で示す最大許容信号
入力レベルを大きくするように諸パラメータを設
定し、同時に、大信号入力時に平衡変調回路の出
力端で周波数変換された中間周波信号の電圧振幅
の増大により生ずる混変調ひずみ、相互変調ひず
みを極力抑えるため局発注入レベルを小さくして
周波数変換コンダクタンスを減少させることを提
案するものである。
The present invention aims to eliminate the above-mentioned drawbacks when using a double-balanced modulation circuit as a mixer in the receiver front-end section, and when the signal input level to the receiver is small, the above-mentioned frequency The parameters shown in equations (1) and (2) are set to maintain good conditions with emphasis on conversion conductance and noise figure, and when the signal input level to the receiver is large, Parameters are set to increase the maximum allowable signal input level shown by the equation In order to suppress intermodulation distortion as much as possible, we propose reducing the local injection level and reducing the frequency conversion conductance.

以下本発明について実施例の図面と共に説明す
る。
The present invention will be described below with reference to drawings of embodiments.

第2図は本発明の平衡変調器を含めて受信機を
構成した場合の一実施例を示すブロツク図、そし
て第3図は本発明の諸機能を具備する二重平衡変
調回路を中心として構成した平衡変調器の一実施
例を示す回路図である。第2図において、受信信
号はアンテナ11を介して平衡変調器12の信号
入力端子に与えられる。(説明を簡単にするため
高周波増幅回路部、周波数選択回路部などは省略
している。)この平衡変調器12にはさらに局部
発振回路13からの発振信号が局発注入端子を通
して加えられている。また、この平衡変調器12
にはさらに中間周波レベル検出器16から得られ
る出力信号も加えられており、受信信号のレベル
が大きいときに中間周波レベル検出器16から得
られる出力信号が増大することを利用し、受信信
号レベルが大きいときに前述したように平衡変調
器12に含まれる二重平衡変調回路のバイアス電
流を増大させると共に二重平衡変調回路への局発
注入レベルを低下させている。上記平衡変調器1
2の出力は中間周波フイルタ14を通して中間周
波増幅器15に加えられ、中間周波増幅器15の
出力は上述の中間周波レベル検出器16および復
調器17に加えられる。復調器17の出力は端子
18を通して図示しないが後段の音声増幅部に加
えられ、最終的にはスピーカなどを用いて音声出
力が得られるようになされている。
FIG. 2 is a block diagram showing an embodiment of a receiver including the balanced modulator of the present invention, and FIG. 3 is a block diagram showing a configuration centered on a double balanced modulation circuit having various functions of the present invention. FIG. 2 is a circuit diagram showing an example of a balanced modulator according to the present invention. In FIG. 2, a received signal is applied to a signal input terminal of a balanced modulator 12 via an antenna 11. (In order to simplify the explanation, the high frequency amplifier circuit section, frequency selection circuit section, etc. are omitted.) An oscillation signal from a local oscillation circuit 13 is further applied to this balanced modulator 12 through a local oscillation injection terminal. . Moreover, this balanced modulator 12
Further, the output signal obtained from the intermediate frequency level detector 16 is added to the output signal, and by utilizing the fact that the output signal obtained from the intermediate frequency level detector 16 increases when the level of the received signal is high, the received signal level is When is large, as described above, the bias current of the double balanced modulation circuit included in the balanced modulator 12 is increased and the local injection level to the double balanced modulation circuit is decreased. The above balanced modulator 1
The output of 2 is applied to an intermediate frequency amplifier 15 through an intermediate frequency filter 14, and the output of the intermediate frequency amplifier 15 is applied to the above-mentioned intermediate frequency level detector 16 and demodulator 17. The output of the demodulator 17 is applied through a terminal 18 to a subsequent audio amplification section (not shown), and finally an audio output is obtained using a speaker or the like.

第2図に示す各ブロツクの中で平衡変調器12
については、その一実施例を第3図を用いて詳述
する。また、局部発振回路13、中間周波増幅回
路15、エンベロープ検波回路などで構成できる
中間周波レベル検出器16、およびAMまたは
FMなどの信号復調器17はそれぞれ周知の回路
技術で実現できるため、これ以上の詳述は省略す
る。
In each block shown in FIG.
An example of this will be described in detail with reference to FIG. In addition, an intermediate frequency level detector 16 that can be configured with a local oscillation circuit 13, an intermediate frequency amplification circuit 15, an envelope detection circuit, etc., and an AM or
Since the signal demodulator 17 for FM and the like can be realized using well-known circuit technology, further detailed description will be omitted.

次に、第2図と対応させて第3図に示す平衡変
調器12の各端子と第2図の各ブロツクとの接続
の関係を説明すると、第2図においてアンテナに
接続されている信号入力端子は第3図に示す端子
20に対応し、局部発振信号の注入される端子は
第3図の端子19に対応し、中間周波フイルタ1
4への周波数変換された信号出力端子は第3図に
示す端子21に対応する。そして、第3図に示す
端子23は第2図に示す中間周波レベル検出器1
6の出力端と接続される端子である。また、第3
図に示す端子22,24はそれぞれ直流電源接続
用端子、アース端子である。
Next, to explain the connection relationship between each terminal of the balanced modulator 12 shown in FIG. 3 and each block in FIG. 2 in correspondence with FIG. 2, the signal input connected to the antenna in FIG. The terminal corresponds to the terminal 20 shown in FIG. 3, and the terminal into which the local oscillation signal is injected corresponds to the terminal 19 in FIG.
The signal output terminal whose frequency has been converted to 4 corresponds to the terminal 21 shown in FIG. The terminal 23 shown in FIG. 3 is connected to the intermediate frequency level detector 1 shown in FIG.
This is a terminal connected to the output terminal of No.6. Also, the third
Terminals 22 and 24 shown in the figure are a DC power supply connection terminal and a ground terminal, respectively.

次に第3図に示す平衡変調器12の動作につい
て説明する。まず、トランジスタQ17,Q18
Q19,Q20,Q15,Q16および抵抗R14は第1図に示
す二重平衡変調回路と対応して同様の動作をする
二重平衡変調回路を構成する。トランジスタ
Q13,Q14はトランジスタQ15,Q16に対する定電
流源であり、カレントミラーの原理によりトラン
ジスタQ21、抵抗R15,R16および端子23に加え
られる中間周波レベル検出器16から得られる出
力信号により定められ、制御される。したがつ
て、(2)式から明らかなようにこの二重平衡変調回
路の最大許容信号入力レベルは中間周波レベルす
なわち入力信号レベルにより制御される。なお、
抵抗R14はいうまでもなく、この二重平衡変調回
路の周波数変換コンダクタンスを決定するための
ものである。次に、端子19に加えられた局部発
振信号は、まず、抵抗R4,R5、および電界効果
型トランジスタ(以下FETという)Q9で構成さ
れる逆L型減衰器を介してトランジスタQ10
Q11、抵抗R6,R7,R8,R9,R10で構成される差
動増幅器に加えられる。上記FETQ9はそのゲー
ト、ソース間電圧によりドレイン・ソース間の交
流インピーダンスが制御される可変インピーダン
ス素子として導入されたものであり、端子23に
加えられる中間周波レベル検出器16から得られ
る出力信号したがつて入力信号レベルにより、そ
のインピーダンスが制御され、端子23に加えら
れる直流的な変化を示す電圧が正方向に増大すれ
ば、そのインピーダンスが低下されるようになさ
れている。上述のトランジスタQ10,Q11を中心
として構成される差動増幅器は上述の二重平衡変
調回路に局発信号を伝送するためのものであり、
合わせて直流バイアス電流も同時に供給してい
る。また、トランジスタQ12、抵抗R11,R12,R13
で構成されるエミツタフオロワ回路は上述のトラ
ンジスタQ10,Q11を中心として構成される差動
増幅器にベースバイアス電圧を供給するためのも
のである。また、第3図に示すコンデンサC1
局発信号の結合用である。
Next, the operation of the balanced modulator 12 shown in FIG. 3 will be explained. First, transistors Q 17 , Q 18 ,
Q 19 , Q 20 , Q 15 , Q 16 and resistor R 14 constitute a double-balanced modulation circuit that corresponds to and operates in the same manner as the double-balanced modulation circuit shown in FIG. transistor
Q 13 and Q 14 are constant current sources for transistors Q 15 and Q 16 , and the output obtained from transistor Q 21 , resistors R 15 and R 16 , and intermediate frequency level detector 16 applied to terminal 23 by the current mirror principle. Defined and controlled by signals. Therefore, as is clear from equation (2), the maximum allowable signal input level of this double-balanced modulation circuit is controlled by the intermediate frequency level, that is, the input signal level. In addition,
Needless to say, the resistor R14 is for determining the frequency conversion conductance of this double-balanced modulation circuit. Next, the local oscillation signal applied to the terminal 19 is first passed through an inverted L-type attenuator composed of resistors R 4 , R 5 and a field effect transistor (hereinafter referred to as FET) Q 9 to a transistor Q 10 .
It is added to a differential amplifier consisting of Q 11 , resistors R 6 , R 7 , R 8 , R 9 , and R 10 . The above FETQ 9 was introduced as a variable impedance element whose AC impedance between the drain and source is controlled by the voltage between its gate and source, and the output signal obtained from the intermediate frequency level detector 16 applied to the terminal 23 is The impedance is controlled by the input signal level, and as the voltage applied to the terminal 23 that shows a direct current change increases in the positive direction, the impedance is reduced. The differential amplifier mainly composed of the above-mentioned transistors Q 10 and Q 11 is for transmitting a local oscillator signal to the above-mentioned double balanced modulation circuit,
A DC bias current is also supplied at the same time. Also, transistor Q 12 , resistors R 11 , R 12 , R 13
The emitter follower circuit is for supplying a base bias voltage to the differential amplifier mainly composed of the above-mentioned transistors Q 10 and Q 11 . Further, the capacitor C1 shown in FIG. 3 is for coupling the local oscillator signal.

ここで、第2図に示す中間周波レベル検出器1
6の出力電圧はその入力電圧の増加に従つて正方
向に増大する特性を付与しておくものとすれば、
第3図に示す入力端子23に加えられる直流的に
変化する電圧はアンテナ11よりの信号入力電圧
の増大につれて正方向に増大する。したがつて、
この場合、アンテナ11よりの信号入力電圧の増
大につれてトランジスタQ15,Q16のバイアス電
流が増大することにより第(2)式に示すように最大
許容信号入力レベルが増加し、また、FETQ9
交流インピーダンスが低下することにより二重平
衡変調回路への局発注入レベルが低下し、周波数
変換コンダクタンスを低下させて出力端子21で
の周波数変換された中間周波信号レベルの増大に
よる混変調ひずみ、相互変調ひずみを低下させ
る。
Here, the intermediate frequency level detector 1 shown in FIG.
Assuming that the output voltage of 6 is given the characteristic of increasing in the positive direction as the input voltage increases,
The DC-varying voltage applied to the input terminal 23 shown in FIG. 3 increases in the positive direction as the signal input voltage from the antenna 11 increases. Therefore,
In this case, as the signal input voltage from the antenna 11 increases, the bias current of the transistors Q 15 and Q 16 increases, and as a result, the maximum allowable signal input level increases as shown in equation ( 2 ). As the AC impedance decreases, the local injection level to the double-balanced modulation circuit decreases, which reduces the frequency conversion conductance and increases the level of the frequency-converted intermediate frequency signal at the output terminal 21, resulting in cross-modulation distortion and mutual interference. Reduce modulation distortion.

本発明ではFETQ9のかわりにバイポーラのト
ランジスタを導入したり、あるいはもつと複雑な
マルチプライヤーなどを利用した信号の可変減衰
回路を導入したりしてもよいことはいうまでもな
い。
It goes without saying that in the present invention, a bipolar transistor may be introduced in place of the FETQ 9 , or a variable signal attenuation circuit using a complicated multiplier or the like may be introduced.

また、アンテナ11よりの受信信号レベルが十
分小さい場合には、第3図に示す二重平衡変調回
路のトランジスタQ15,Q16のバイアス電流、お
よび二重平衡変調回路に加えられる局発信号の注
入レベルは雑音指数を考慮し、最適なレベルに設
定しておくことが望ましいのは云うまでもない。
Furthermore, when the received signal level from the antenna 11 is sufficiently small, the bias current of transistors Q 15 and Q 16 of the double-balanced modulation circuit shown in FIG. 3 and the local oscillation signal applied to the double-balanced modulation circuit It goes without saying that it is desirable to set the injection level to an optimal level in consideration of the noise figure.

以上に詳述したように本発明によれば、受信信
号レベルの広い範囲にわたつて混変調ひずみ、相
互変調ひずみの発生も少なく、かつ、小さな受信
信号レベルに対して低ノイズ特性を有する平衡変
調回路を得ることができるものである。
As described in detail above, according to the present invention, balanced modulation is achieved that has little generation of cross-modulation distortion and intermodulation distortion over a wide range of received signal levels, and has low noise characteristics for small received signal levels. It is possible to obtain a circuit.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来例の二重平衡変調回路を示す回路
図、第2図は本発明の平衡変調回路を用いて信号
受信機を構成した場合のブロツク図、第3図は本
発明平衡変調回路の一実施例を示す回路図であ
る。 12……平衡変調器、13……局部発振回路、
15……中間周波増幅回路、16……中間周波レ
ベル検出器、17……復調器、Q10〜Q21……ト
ランジスタ、R4〜R16……抵抗。
Fig. 1 is a circuit diagram showing a conventional dual balanced modulation circuit, Fig. 2 is a block diagram of a signal receiver configured using the balanced modulation circuit of the present invention, and Fig. 3 is a balanced modulation circuit of the present invention. FIG. 2 is a circuit diagram showing one embodiment of the present invention. 12...Balanced modulator, 13...Local oscillation circuit,
15...Intermediate frequency amplifier circuit, 16...Intermediate frequency level detector, 17...Demodulator, Q10 to Q21 ...Transistor, R4 to R16 ...Resistor.

Claims (1)

【特許請求の範囲】[Claims] 1 エミツタ結合型差動対トランジスタを複数組
用いた二重平衡型のトランジスタ平衡変調回路
と、信号の入力レベルの増加に応じて上記平衡変
調回路のバイアス電流を増加させる手段と、信号
の入力レベルの増加に応じて上記平衡変調回路に
加える局部発振信号のレベルを減少させる手段を
具備し、信号の入力レベルの広い範囲にわたつて
上記平衡変調回路のひずみを低減するようにした
ことを特徴とする平衡変調器。
1. A double-balanced transistor balanced modulation circuit using a plurality of pairs of emitter-coupled differential pair transistors, means for increasing the bias current of the balanced modulation circuit in accordance with an increase in the input level of a signal, and an input level of a signal. The balanced modulation circuit is characterized by comprising means for reducing the level of the local oscillation signal applied to the balanced modulation circuit in response to an increase in the level of the local oscillation signal, thereby reducing distortion in the balanced modulation circuit over a wide range of signal input levels. Balanced modulator.
JP13403179A 1979-10-16 1979-10-16 Balanced modulator Granted JPS5657313A (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP13403179A JPS5657313A (en) 1979-10-16 1979-10-16 Balanced modulator
DE19803038995 DE3038995A1 (en) 1979-10-16 1980-10-15 Balanced mixer for radio receiver - reduces distortion in modulator over wide range of signal amplitudes using emitter-coupled transistor pairs
CA000362445A CA1155927A (en) 1979-10-16 1980-10-15 Balanced modulator

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13403179A JPS5657313A (en) 1979-10-16 1979-10-16 Balanced modulator

Publications (2)

Publication Number Publication Date
JPS5657313A JPS5657313A (en) 1981-05-19
JPS6243561B2 true JPS6243561B2 (en) 1987-09-16

Family

ID=15118750

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13403179A Granted JPS5657313A (en) 1979-10-16 1979-10-16 Balanced modulator

Country Status (3)

Country Link
JP (1) JPS5657313A (en)
CA (1) CA1155927A (en)
DE (1) DE3038995A1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63294822A (en) * 1987-05-27 1988-12-01 求 政治 Automatic tableware washer

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
IT1211106B (en) * 1981-09-16 1989-09-29 Ates Componenti Elettron TRANSISTOR AMPLIFIER AND MIXER INPUT STAGE FOR A RADIO RECEIVER.
JPS58171105A (en) * 1982-03-31 1983-10-07 Toshiba Corp Amplitude modulator
JPS61105912A (en) * 1984-10-30 1986-05-24 Mitsubishi Electric Corp Mixer circuit
NL8503435A (en) * 1985-12-13 1987-07-01 Philips Nv UHF AMPLIFIER MIXING CIRCUIT.
DE10239856A1 (en) * 2002-08-29 2004-03-11 Infineon Technologies Ag Circuit arrangement with frequency converter
US7865157B2 (en) 2003-11-03 2011-01-04 Thomson Licensing Controllable mixer
DE10351115A1 (en) * 2003-11-03 2005-05-25 Deutsche Thomson-Brandt Gmbh Controllable mixer e.g. for suppression of signals in receiver, has transistor, oscillator signal and input signal with input signal covers information signal and further signals where output of mixer is supplied

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63294822A (en) * 1987-05-27 1988-12-01 求 政治 Automatic tableware washer

Also Published As

Publication number Publication date
JPS5657313A (en) 1981-05-19
CA1155927A (en) 1983-10-25
DE3038995A1 (en) 1981-05-14

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