JPS63289994A - Manufacture of printed multilayer interconnection substrate - Google Patents
Manufacture of printed multilayer interconnection substrateInfo
- Publication number
- JPS63289994A JPS63289994A JP12627287A JP12627287A JPS63289994A JP S63289994 A JPS63289994 A JP S63289994A JP 12627287 A JP12627287 A JP 12627287A JP 12627287 A JP12627287 A JP 12627287A JP S63289994 A JPS63289994 A JP S63289994A
- Authority
- JP
- Japan
- Prior art keywords
- hole
- copper oxide
- paste
- copper
- printed
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000758 substrate Substances 0.000 title claims abstract description 13
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 9
- QPLDLSVMHZLSFG-UHFFFAOYSA-N Copper oxide Chemical compound [Cu]=O QPLDLSVMHZLSFG-UHFFFAOYSA-N 0.000 claims abstract description 28
- 239000005751 Copper oxide Substances 0.000 claims abstract description 18
- 229910000431 copper oxide Inorganic materials 0.000 claims abstract description 18
- 239000000203 mixture Substances 0.000 claims abstract description 15
- 238000000034 method Methods 0.000 claims abstract description 13
- 239000004020 conductor Substances 0.000 claims abstract description 12
- 239000010949 copper Substances 0.000 claims abstract description 12
- 239000012298 atmosphere Substances 0.000 claims abstract description 9
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims abstract description 8
- 229910052802 copper Inorganic materials 0.000 claims abstract description 8
- 238000005245 sintering Methods 0.000 claims abstract 4
- 230000001590 oxidative effect Effects 0.000 claims abstract 3
- 238000007639 printing Methods 0.000 claims description 4
- 238000010438 heat treatment Methods 0.000 claims 1
- 238000010030 laminating Methods 0.000 claims 1
- 239000012212 insulator Substances 0.000 abstract description 9
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 abstract description 4
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 abstract description 2
- 239000007789 gas Substances 0.000 abstract 1
- 239000001257 hydrogen Substances 0.000 abstract 1
- 229910052739 hydrogen Inorganic materials 0.000 abstract 1
- 239000002075 main ingredient Substances 0.000 abstract 1
- 229910052757 nitrogen Inorganic materials 0.000 abstract 1
- 238000010304 firing Methods 0.000 description 6
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 5
- 239000011230 binding agent Substances 0.000 description 5
- 229920002037 poly(vinyl butyral) polymer Polymers 0.000 description 4
- WVDDGKGOMKODPV-UHFFFAOYSA-N Benzyl alcohol Chemical compound OCC1=CC=CC=C1 WVDDGKGOMKODPV-UHFFFAOYSA-N 0.000 description 3
- 239000002904 solvent Substances 0.000 description 3
- WUOACPNHFRMFPN-UHFFFAOYSA-N alpha-terpineol Chemical compound CC1=CCC(C(C)(C)O)CC1 WUOACPNHFRMFPN-UHFFFAOYSA-N 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- SQIFACVGCPWBQZ-UHFFFAOYSA-N delta-terpineol Natural products CC(C)(O)C1CCC(=C)CC1 SQIFACVGCPWBQZ-UHFFFAOYSA-N 0.000 description 2
- 229910001873 dinitrogen Inorganic materials 0.000 description 2
- 239000002245 particle Substances 0.000 description 2
- 239000000843 powder Substances 0.000 description 2
- 229940116411 terpineol Drugs 0.000 description 2
- POAOYUHQDCAZBD-UHFFFAOYSA-N 2-butoxyethanol Chemical compound CCCCOCCO POAOYUHQDCAZBD-UHFFFAOYSA-N 0.000 description 1
- LFQSCWFLJHTTHZ-UHFFFAOYSA-N Ethanol Chemical compound CCO LFQSCWFLJHTTHZ-UHFFFAOYSA-N 0.000 description 1
- ZZSNKZQZMQGXPY-UHFFFAOYSA-N Ethyl cellulose Chemical compound CCOCC1OC(OC)C(OCC)C(OCC)C1OC1C(O)C(O)C(OC)C(CO)O1 ZZSNKZQZMQGXPY-UHFFFAOYSA-N 0.000 description 1
- 229920003171 Poly (ethylene oxide) Polymers 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 150000005215 alkyl ethers Chemical class 0.000 description 1
- 235000019445 benzyl alcohol Nutrition 0.000 description 1
- 239000005388 borosilicate glass Substances 0.000 description 1
- 125000000484 butyl group Chemical group [H]C([*])([H])C([H])([H])C([H])([H])C([H])([H])[H] 0.000 description 1
- 239000003153 chemical reaction reagent Substances 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 238000010924 continuous production Methods 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 230000007935 neutral effect Effects 0.000 description 1
- -1 polyoxyethylene Polymers 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 238000007650 screen-printing Methods 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 239000004094 surface-active agent Substances 0.000 description 1
Landscapes
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明はスルーホール孔を有する印刷多層配線基板の製
造方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a method of manufacturing a printed multilayer wiring board having through holes.
従来の技術
近年、導体配線材料にＣｕを使用した印刷多層配線基板
は厚膜ペーストが手軽に入手できることや、工法そのも
のが筒車なため、比較的容易に作製ができるので、現在
多くの方面で実用されている。しかし、この厚膜印刷法
のほとんどの場合は、導体層および絶縁体層の印刷後、
その都度中性雰囲気中で焼成を行なうので、脱バインダ
が困難となりブリスタの発生や、絶縁性の劣化につなが
っている。また、設備コストのアンプそしてリートタイ
ムが長くなる等の欠点がある。そこで上記欠点を解決し
たのが、導体配線にＣｕＯを使用する方法である。これ
により大気中で容易に脱バインダを行なうことができ、
印刷後その都度焼成を繰り返す必要がなく、１回の還元
−焼成の連続工程を行なうだけで良い。しかしながら、
この方法で得たＣｕ配線は基板との接着強度や半田の濡
れ性がやや劣るので最上層配線には使用できない。しか
し内層配線では絶縁体層で被覆することにより表面には
露出させないので実用上充分である。この多層方法は、
特願昭５９−１４７８３３．特願昭５９−１４７８３２
に、そして酸化銅ペーストは、特願昭６０−２３８４６
．特願昭６０−１４０８１６にそれぞれ述べられている
。Conventional technology In recent years, printed multilayer wiring boards using Cu as the conductor wiring material are relatively easy to manufacture because thick film paste is easily available and the construction method itself is hour wheel, so it is currently being used in many fields. It is put into practical use. However, in most cases of this thick film printing method, after printing the conductive and insulating layers,
Since firing is performed in a neutral atmosphere each time, it is difficult to remove the binder, leading to the generation of blisters and deterioration of insulation properties. Additionally, there are drawbacks such as increased equipment costs and longer REIT time. Therefore, a method of using CuO for the conductor wiring has solved the above-mentioned drawbacks. This makes it possible to easily remove the binder in the atmosphere.
There is no need to repeat firing each time after printing, and only one continuous process of reduction and firing is sufficient. however,
Cu wiring obtained by this method cannot be used as the top layer wiring because its adhesive strength with the substrate and solder wettability are somewhat inferior. However, since the inner layer wiring is covered with an insulating layer and is not exposed to the surface, it is sufficient for practical use. This multilayer method is
Patent application No. 59-147833. Patent application 1987-147832
And the copper oxide paste is patented in Japanese Patent Application No. 60-23846.
．． Each is described in Japanese Patent Application No. 140816/1983.
以下図面を参照しながら、上述した従来の方法によるス
ルーホール孔を存する印刷多層配線基板の製造方法の一
例について説明する。第２図は従来のスルーホール孔を
存する印刷多層基板の断面を示すものである。第２図に
おいて、１はスルーホール孔６を有するアルミナ基板で
ある。前記基板上に内層導体の配線パターンを形成する
が、スルーホール孔６をＣｕＯペーストで埋めるように
して配線パターンを形成すると、ＣｕＯペーストによる
印刷、乾燥の時点ではスルーホール孔内にＣｕＯ膜を作
るが、後の還元−焼成工程時に起こるＣｕＯの体積収縮
のためスルーホール孔の工。An example of a method for manufacturing a printed multilayer wiring board having through-holes by the above-described conventional method will be described below with reference to the drawings. FIG. 2 shows a cross section of a conventional printed multilayer board with through holes. In FIG. 2, reference numeral 1 denotes an alumina substrate having through holes 6. As shown in FIG. A wiring pattern of the inner layer conductor is formed on the substrate, and when the wiring pattern is formed by filling the through-hole holes 6 with CuO paste, a CuO film is formed in the through-hole holes when the CuO paste is printed and dried. However, due to the volumetric shrinkage of CuO that occurs during the subsequent reduction and firing process, a through-hole was required.
ジ部分に亀裂が発生する。したがって内層導体２は第２
図のようにスルーホール孔６を避けるようにパターン形
成を行なう。そして絶縁体３を内層導体２上およびアル
ミナ基Ｆｉｅ上の所望領域に形成し、最後に最上層導体
４でスルーホール孔６とバイアホール孔５を埋めるよう
に形成し、スルーホール孔６内にＣｕ導電膜を形成する
。Cracks occur in the area. Therefore, the inner layer conductor 2
The pattern is formed so as to avoid the through holes 6 as shown in the figure. Then, the insulator 3 is formed in desired areas on the inner layer conductor 2 and the alumina base Fie, and finally, the uppermost layer conductor 4 is formed so as to fill the through hole hole 6 and the via hole hole 5. A Cu conductive film is formed.
発明が解決しようとする問題点
しかしながら、上記のような構成ではスルーホール孔６
内に導電膜を形成するには配線パターンの設計でバイア
ホール５を設け、しかも最上層導体４を使用しなければ
ならないので、作業が煩雑になるという問題がある。本
発明は、上記問題点を解決するためになされたもので、
簡単な手順によりスルーホール孔内面にＣｕ導電膜を有
する印刷多層配線基板の製造方法を提供するものである
。Problems to be Solved by the Invention However, in the above configuration, the through hole hole 6
In order to form a conductive film therein, a via hole 5 must be provided in the wiring pattern design and the top layer conductor 4 must be used, which makes the work complicated. The present invention was made to solve the above problems, and
The present invention provides a method for manufacturing a printed multilayer wiring board having a Cu conductive film on the inner surface of a through hole using a simple procedure.
問題点を解決するための手段
本発明は上記問題点を解決するために、スルーホール孔
内にＣｕＯ膜を形成し、さらにその上から絶縁体膜を被
覆することにより還元−焼成工程でスルーホール孔エツ
ジ部分に発生する内層導体の亀裂を抑え、かつ多層配線
を形成するとともにスルーホール孔内にＣｕｄ電膜が形
成するようにしたものである。Means for Solving the Problems In order to solve the above-mentioned problems, the present invention forms a CuO film inside the through-hole, and further covers the insulating film on top of the CuO film, thereby forming a through-hole in the reduction and firing process. This suppresses cracks in the inner layer conductor that occur at the edge of the hole, forms multilayer wiring, and forms a Cud electrical film inside the through hole.
作用
本発明は上記した構成によって、スルーホール孔内に形
成したＣｕＯ膜は絶縁体層に被覆されるので、還元−焼
成工程を行なっても、得られる導電膜はＣｕＯの体積収
縮による断線がなくスルーホール孔内に形成される。According to the present invention, the CuO film formed inside the through-hole is covered with an insulating layer, so that even if the reduction and firing process is performed, the resulting conductive film will not be disconnected due to the volumetric shrinkage of CuO. Formed within a through hole.
実施例
以下本発明の一実施例の印刷多層配線基板の製造方法に
ついて図面を参照しながら説明する。第１図は本発明の
実施例における印刷多層配線基板の断面を示すものであ
る。第１図において、１はスルーホール孔６を有するア
ルミナ基板である。EXAMPLE Hereinafter, a method for manufacturing a printed multilayer wiring board according to an example of the present invention will be described with reference to the drawings. FIG. 1 shows a cross section of a printed multilayer wiring board in an embodiment of the present invention. In FIG. 1, reference numeral 1 denotes an alumina substrate having through holes 6. As shown in FIG.
前記７５板上に酸化銅ペーストによりスクリーン印刷を
施しながら、基板のスルーホール孔６がら上記ペースト
を吸引して孔内面に酸化銅層７を形成する。この時に使
用される酸化ｔＭ（ｃｕ□）は試薬特級の平均粒径５μ
ｍのものを用いた。ペースト作製のためのビヒクル組成
は、溶剤としてターピネオールとベンジルアルコールの
混合液を用い、を機バインダであるポリビニルブチラー
ルを溶かしたものを用い、上記酸化銅粉末と混練したも
のをペーストとした。一方絶縁体ペーストは、ホウケイ
酸鉛ガラス粉末とアルミナ粉末を重量比で５０対５０と
なるように配合した無機組成物（平均粒径２μｍ）を用
い、ビヒクル組成は溶剤としてＤｕｐｏｎｔ社製シンナ
ー９４５０を用い、有機バインダであるポリビニルブチ
ラールを用い、上記無機組成物を混練したものをペース
トとした。While screen printing is performed using copper oxide paste on the board 75, the paste is sucked into the through-hole hole 6 of the substrate to form a copper oxide layer 7 on the inner surface of the hole. The oxidized tM (cu□) used at this time is a reagent grade with an average particle size of 5μ.
m was used. The vehicle composition for preparing the paste was as follows: A mixture of terpineol and benzyl alcohol was used as the solvent, and polyvinyl butyral as a binder was dissolved therein, and the mixture was kneaded with the above-mentioned copper oxide powder to form a paste. On the other hand, the insulating paste used was an inorganic composition (average particle size 2 μm) containing lead borosilicate glass powder and alumina powder in a weight ratio of 50:50, and the vehicle composition used Dupont thinner 9450 as a solvent. The above inorganic composition was kneaded using polyvinyl butyral as an organic binder to form a paste.
前記酸化銅ペーストを基板ｌの両面にスクリーン印刷し
く第１図［ａｌ） 、乾燥の後、絶縁体ペーストを酸化
銅配線７上および基板１上の所望領域にスクリーン印刷
を施しながら、基板１のスルーホール孔６から上記絶縁
体ペーストを吸引して孔内面の酸化銅膜７を被覆した（
第１図（ｂ））。The copper oxide paste is screen printed on both sides of the substrate 1, as shown in FIG. The insulating paste was sucked from the through-hole hole 6 to cover the copper oxide film 7 on the inner surface of the hole (
Figure 1(b)).
なお、前記酸化銅ペースト、絶縁体ペーストの作製にタ
ーピネオール、ヘンシルアルコール。Note that terpineol and Hensyl alcohol are used to prepare the copper oxide paste and insulator paste.
Ｄｕｐｏｎｔ社製シンナー、ポリビニルブチラールを用
いたが、有機バインダとしては、ブチラール系樹脂の代
わりにエトセル系樹脂、溶剤にはブチルカルピトール、
ブチルセルソルブのようなセルソルブ類を用いても良く
、さらにソルビタンアルキルエステル、ポリオキシエチ
レンアルキエーテル等の界面活性剤を用いることも有効
な手段である。DuPont thinner and polyvinyl butyral were used, but the organic binder was ethocel resin instead of butyral resin, and the solvent was butyl calpitol,
Cellosolves such as butyl cellosolve may be used, and it is also an effective means to use surfactants such as sorbitan alkyl ester and polyoxyethylene alkyl ether.
次に印刷を完了した配線基板を空気中で５００℃に加熱
し、ペースト中の有機成分を完全に除去（脱バインダを
行なった。続いて、水素ガスを３０％含む窒素ガス雰囲
気中３００℃で酸化銅を金属銅に還元した後、窒素ガス
雰囲気中９００℃で金属銅と絶縁体を焼成した（第１図
（Ｃ））。Next, the printed wiring board was heated in air to 500°C to completely remove the organic components in the paste (debinding was performed).Then, the printed wiring board was heated at 300°C in a nitrogen gas atmosphere containing 30% hydrogen gas. After reducing the copper oxide to metallic copper, the metallic copper and the insulator were fired at 900° C. in a nitrogen gas atmosphere (FIG. 1(C)).
上記の操作により、得られた印刷配線基板は第１図（Ｃ
）に示すように、スルーホール孔６内に導電膜２が絶縁
体層３に被覆され、断線な（形成されたものとなる。The printed wiring board obtained by the above operation is shown in Figure 1 (C
), the conductive film 2 is covered with the insulating layer 3 in the through-hole hole 6, so that no disconnection occurs.
発明の効果
本発明の構成および製造方法によれば、＋１１ スル
ーホール孔内に形成した酸化銅膜の上から絶縁体層を被
覆しているので、酸化銅を還元−焼成した際に生じる体
積収縮による配線の断線を抑えられる。Effects of the Invention According to the configuration and manufacturing method of the present invention, since the insulating layer is coated over the copper oxide film formed in the +11 through hole, the volume shrinkage that occurs when the copper oxide is reduced and fired is reduced. This prevents wiring breakage caused by wire breakage.
（２） スルーホール孔を絶縁体層で埋めるので、ス
ルーホール上にも配線が可能となり、多層化。(2) Since the through-hole hole is filled with an insulator layer, it is possible to conduct wiring even on the through-hole, resulting in multilayer design.
高密度化に向いている。Suitable for high density.
第１図は本発明における印刷多層配線基板のスルーホー
ル孔部の断面図、第２図は従来方法によるスルーホール
孔部の断面図である。
ｌ・・・・・・アルミナ基板、２・・・・・・内層導体
層、３・・・・・・絶縁体層、４・・・・・・最上層導
体層、５・・・・・・バイアホール孔、６・・・・・・
スルーホール孔、７・・・・・・酸化銅層。FIG. 1 is a cross-sectional view of a through-hole portion of a printed multilayer wiring board according to the present invention, and FIG. 2 is a cross-sectional view of a through-hole portion according to a conventional method. l...Alumina substrate, 2...Inner conductor layer, 3...Insulator layer, 4...Top conductor layer, 5...・Via hole hole, 6...
Through-hole hole, 7...Copper oxide layer.
Claims (1)
ンを載せ、このスクリーンパターン上の銅の酸化物を主
成分とするペースト組成物により前記基板上に配線層の
印刷を施しながら基板のスルーホール孔から上記ペース
ト組成物を吸引して孔内面に膜を形成すること、および
前記配線層上および基板上の所望領域に厚膜絶縁体層を
形成し前記酸化銅ペーストと、絶縁ペーストを所望の回
数積層印刷し多層化して、大気または酸化性雰囲気中で
、かつ内部の有機成分を熱分解させるに充分な温度で熱
処理を行ない、しかる後、水素と窒素の混合ガス雰囲気
中で前記絶縁体層組成物が焼結する温度以下で、かつ酸
化銅が金属銅に還元される温度以上で熱処理を行ない、
さらに銅に対して非酸化性となる雰囲気とし、前記絶縁
体組成物の焼結を行なわしめることによってスルーホー
ル孔内に銅導体膜を形成することを特徴とする印刷多層
配線基板の製造方法。A screen pattern is placed on a wiring board having through-holes, and while a wiring layer is printed on the board using a paste composition containing copper oxide as a main component on the screen pattern, the wiring layer is printed from the through-holes of the board. Suctioning the paste composition to form a film on the inner surface of the hole, and forming a thick insulating layer on the wiring layer and the desired area on the substrate, and laminating and printing the copper oxide paste and the insulating paste a desired number of times. The insulating layer composition is formed into multiple layers and heat-treated in the air or an oxidizing atmosphere at a temperature sufficient to thermally decompose the organic components therein. Heat treatment is performed at a temperature below the sintering temperature and above the temperature at which the copper oxide is reduced to metallic copper,
A method for manufacturing a printed multilayer wiring board, further comprising forming a copper conductor film in the through-hole by sintering the insulating composition in an atmosphere that is non-oxidizing to copper.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12627287A JPS63289994A (en) | 1987-05-22 | 1987-05-22 | Manufacture of printed multilayer interconnection substrate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12627287A JPS63289994A (en) | 1987-05-22 | 1987-05-22 | Manufacture of printed multilayer interconnection substrate |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63289994A true JPS63289994A (en) | 1988-11-28 |
Family
ID=14931090
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12627287A Pending JPS63289994A (en) | 1987-05-22 | 1987-05-22 | Manufacture of printed multilayer interconnection substrate |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63289994A (en) |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60214591A (en) * | 1984-04-10 | 1985-10-26 | 松下電器産業株式会社 | Screen printing machine |
| JPS61113298A (en) * | 1984-11-08 | 1986-05-31 | 松下電器産業株式会社 | Through hole printing |
| JPS62129A (en) * | 1985-06-26 | 1987-01-06 | Oki Electric Ind Co Ltd | Input and output circuit |
| JPS622597A (en) * | 1985-06-27 | 1987-01-08 | 松下電器産業株式会社 | Manufacture of ceramic wiring substrate |
-
1987
- 1987-05-22 JP JP12627287A patent/JPS63289994A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60214591A (en) * | 1984-04-10 | 1985-10-26 | 松下電器産業株式会社 | Screen printing machine |
| JPS61113298A (en) * | 1984-11-08 | 1986-05-31 | 松下電器産業株式会社 | Through hole printing |
| JPS62129A (en) * | 1985-06-26 | 1987-01-06 | Oki Electric Ind Co Ltd | Input and output circuit |
| JPS622597A (en) * | 1985-06-27 | 1987-01-08 | 松下電器産業株式会社 | Manufacture of ceramic wiring substrate |
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