JPH02277279A - Simultaneously baked ceramic circuit board - Google Patents

Simultaneously baked ceramic circuit board

Info

Publication number
JPH02277279A
JPH02277279A JP9853189A JP9853189A JPH02277279A JP H02277279 A JPH02277279 A JP H02277279A JP 9853189 A JP9853189 A JP 9853189A JP 9853189 A JP9853189 A JP 9853189A JP H02277279 A JPH02277279 A JP H02277279A
Authority
JP
Japan
Prior art keywords
conductor
ceramic
circuit board
sb2o3
cracks
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP9853189A
Other languages
Japanese (ja)
Other versions
JPH0738493B2 (en
Inventor
Junzo Fukuda
福田 順三
Kazuo Sugimoto
杉本 一男
Kuniharu Noda
野田 邦治
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Narumi China Corp
Original Assignee
Narumi China Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Narumi China Corp filed Critical Narumi China Corp
Priority to JP9853189A priority Critical patent/JPH0738493B2/en
Publication of JPH02277279A publication Critical patent/JPH02277279A/en
Publication of JPH0738493B2 publication Critical patent/JPH0738493B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/09Use of materials for the conductive, e.g. metallic pattern
    • H05K1/092Dispersed materials, e.g. conductive pastes or inks
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/40Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/4038Through-connections; Vertical interconnect access [VIA] connections
    • H05K3/4053Through-connections; Vertical interconnect access [VIA] connections by thick-film techniques
    • H05K3/4061Through-connections; Vertical interconnect access [VIA] connections by thick-film techniques for via connections in inorganic insulating substrates

Landscapes

  • Parts Printed On Printed Circuit Boards (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)

Abstract

PURPOSE:To see that cracks do not occur at and around a through hole conductor by using Ag, Rh, Sb2O3 for a through hole filling conductor, and specifying the composition ratio. CONSTITUTION:Through hole filling conductor consists of Ag, Rh, Sb2O3, and when the parts of Rh and Sb2O3 are defined respectively as X and Y to 100 weight parts of Ag being main composition, the composition ratio is so determined that values X and Y meet the following formula, (-5/2)X+10.0>=Y>=(-5)X+0.05 (when X>=0, and Y>=0). Hereby, Ag sintered body is made porous, and discord of thermal expansion coefficient between Ag and ceramic is prevented, whereby crack generation around the conductor or in the conductor can be prevented.

Description

【発明の詳細な説明】 七二九1へ1吐 E産業上の利用分野] 本発明は電子機器に使用されるセラミック多層回路基板
に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Use] The present invention relates to a ceramic multilayer circuit board used in electronic equipment.

[従来の技術] 一般に、セラミック多層回路基板はWまたはM。[Conventional technology] Generally, ceramic multilayer circuit boards are W or M.

を導体とする高アルミナ系の高温焼成<1500℃以上
)の多層回路基板を用いているが、アルミナは比誘電率
が高く、導体の導通抵抗も高いため、信号伝播遅延時間
も長くなりコンピュータ等の高速化、高性能化の障害と
なっていた。
A multilayer circuit board made of high alumina and fired at a high temperature <1500℃ or higher) is used as a conductor, but since alumina has a high dielectric constant and conductor resistance is high, the signal propagation delay time is also long, making it difficult for computers, etc. This has been an obstacle to increasing speed and performance.

このため、高温焼成多層回路基板に代わるものとして、
基板材料は、例えば特開昭60−260465号公報、
特開昭60−227311号公報等に、低融点ガラスに
アルミナを添加したセラミックやA1□0g−8iO□
CaO−MgO−B2O5系セラミック等を用い、さら
に導体は、例えばAg 、 Ag−Pd 、 Cu等の
低抵抗金属を用い、これらを多層に積層した後800〜
1100℃で焼成する同時焼成セラミック回路基板が発
表されている。ここで使用されているスルーホール用導
体ペーストは、Ag、 Ag−Pdが酸化雰囲気焼成で
使用されている。
Therefore, as an alternative to high-temperature fired multilayer circuit boards,
The substrate material is, for example, disclosed in Japanese Patent Application Laid-Open No. 60-260465,
JP-A No. 60-227311, etc., discloses ceramics made by adding alumina to low-melting glass and A1□0g-8iO□.
Using CaO-MgO-B2O5 ceramic, etc., the conductor is a low resistance metal such as Ag, Ag-Pd, Cu, etc., and after laminating these in multiple layers,
A co-fired ceramic circuit board that is fired at 1100°C has been announced. The through-hole conductor paste used here is made of Ag or Ag-Pd and is fired in an oxidizing atmosphere.

[発明が解決しようとする課題1 導体としてのAgおよびAg−Pdは、熱膨張係数がセ
ラミックに比較し、著しく大きく、急激な温度変化によ
ってスルーホール中のAgおよびAg−Pdとセラミッ
クとの間に大きな引張応力あるいは圧縮応力がかかり、
導体中やセラミック中にクラックが発生しやすい欠点が
ある。またAg−Pdの場合、焼成中にPdが酸化膨張
し、セラミック中へのクラックが発生しやすいという欠
点があった。即ち、同時焼成セラミック基板の焼成中に
基板にクラックを発生させないスルーホール導体の開発
が課題であった。
[Problem to be Solved by the Invention 1 Ag and Ag-Pd as conductors have significantly larger coefficients of thermal expansion than ceramics, and rapid temperature changes can cause damage between Ag or Ag-Pd in through holes and ceramics. is subjected to large tensile or compressive stress,
The drawback is that cracks are likely to occur in conductors and ceramics. In addition, in the case of Ag-Pd, Pd oxidizes and expands during firing, which tends to cause cracks in the ceramic. That is, the challenge was to develop a through-hole conductor that does not cause cracks in the substrate during firing of the co-fired ceramic substrate.

主−遣づFバI【 [課題を解決するための手段] 本発明は、スルーホール充填導体がAg、  Rh、S
b2O3よりなり、その組成割合がAg 100重量部
に対しRhとSb2O3をそれぞれ、Xおよび7重量部
としたとき、X、Yが下記式の範囲内 (−5/2)X+10.0≧Y ≧(−5)X +0.
05、X≧0、Y≧0を満足することを特徴とする同時
焼成セラミック回路基板である。
[Means for Solving the Problems] The present invention provides a through-hole filling conductor that is composed of Ag, Rh, and S.
When Rh and Sb2O3 are X and 7 parts by weight, respectively, relative to 100 parts by weight of Ag, X and Y are within the range of the following formula (-5/2): X+10.0≧Y≧ (-5)X +0.
05, a co-fired ceramic circuit board characterized by satisfying X≧0 and Y≧0.

[作用] 本発明は、その構成に示すように、同時焼成後のスルー
ホール導体組成の主組成であるAgに対しRh、 Sb
2O3を一定範囲量添加することで達成される。即ち、
本発明はペースト中のAg扮体に焼成後Sb2O.にな
るsb含有物を添加することによってAg焼結体をポー
ラス状としてAgとセラミック間の熱膨張係数の不一致
を防ぐことと、従来のペーストの欠点であるPdによる
焼成中の体積膨張を防ぐため、Pdを含有させないこと
で課題を解決したものと考えられる。
[Function] As shown in the configuration, the present invention has Rh and Sb in contrast to Ag, which is the main composition of the through-hole conductor composition after co-firing.
This is achieved by adding 2O3 in a certain amount. That is,
In the present invention, Sb2O. By adding sb-containing substances, the Ag sintered body is made porous to prevent mismatch in thermal expansion coefficient between Ag and ceramic, and to prevent volume expansion during firing due to Pd, which is a drawback of conventional pastes. It is thought that the problem was solved by not containing Pd.

第1図に、本発明のAg 100重量部に対するSb、
O,とRh成分の添加量を図示した。その添加量の組成
限定理由は、第1図の斜線部の左下部ではその添加効果
が見られず、また斜線部の左上部では、導通抵抗が上昇
することおよび焼成収縮量が少なくなるためセラミック
の収縮率と一致しなくなり、焼成時にセラミック中にク
ラックが発生し易くなるためである。本発明に用いる金
属ペースト中のAg粉は、通常市販されている沈澱法ま
たはアトマイズ法等で作製された0粒径0.01〜10
0μm程度の粉末であり、球状あるいは扁平状粉末でよ
い、また添加するsbは、Sb2O.無機粉やsbレジ
ネート等の有機アンチモン化合物を用い、焼成後Sb2
0gとなるものであればよい。Rhも同様にRh金属粉
体やRhレジネート等の有機Rh化合物等で焼成後Rh
となるものを使用すればよい。
FIG. 1 shows Sb for 100 parts by weight of Ag of the present invention,
The amounts of O, and Rh components added are illustrated. The reason why the amount of addition is limited to the composition is that the effect of its addition is not seen in the lower left part of the shaded area in Figure 1, and the conduction resistance increases and the amount of firing shrinkage decreases in the upper left part of the shaded area. This is because the shrinkage rate does not match the shrinkage rate of the ceramic, and cracks are likely to occur in the ceramic during firing. The Ag powder in the metal paste used in the present invention is prepared by a commercially available precipitation method or atomization method, etc., and has a particle size of 0.01 to 10.
It is a powder of about 0 μm, and may be a spherical or flat powder.The sb added is Sb2O. Using inorganic powder and organic antimony compounds such as sb resinate, Sb2
It is sufficient as long as it gives 0g. Rh is also treated with Rh metal powder or an organic Rh compound such as Rh resinate after firing.
You can use the one that becomes .

[実施例] 以下実施例で説明する。[Example] This will be explained below using examples.

同時焼成セラミック基板としてはCa0−Al□03−
5iO□−B203系ガラスとアルミナ粉の混合物を用
いた。
As a co-fired ceramic substrate, Ca0-Al□03-
A mixture of 5iO□-B203 glass and alumina powder was used.

セラミックグリンシートは前記混合物と有機バインダー
(アクリル樹脂)、可塑剤(フタル酸ジブチル)、溶剤
(トルエンとブタノール混合)をボールミルで混合し、
ドクターブレード法にて厚み0.4 mmのセラミック
グリンシートを作製した。導体ペーストは第1表に示し
たそれぞれの金属成分の金属粉末・添加物と有機バイン
ダー(エチルセルロース、またはアクリル樹脂)と溶剤
(テレピネオール)の混合物を三本ロールでよく混合混
練して作製した。
The ceramic green sheet is made by mixing the above mixture with an organic binder (acrylic resin), a plasticizer (dibutyl phthalate), and a solvent (a mixture of toluene and butanol) in a ball mill.
A ceramic green sheet with a thickness of 0.4 mm was produced using the doctor blade method. The conductor paste was prepared by thoroughly mixing and kneading a mixture of metal powders and additives of the respective metal components shown in Table 1, an organic binder (ethyl cellulose or acrylic resin), and a solvent (terpineol) using a three-roll roll.

スルーホールは穴径0.3mmφの大きさに金型を用い
て打ち抜き、導体ペーストをスクリン印刷法でスルーホ
ール内に充填した。
The through holes were punched out using a mold to have a hole diameter of 0.3 mm, and the through holes were filled with conductive paste using a screen printing method.

実施例1〜6は、第2図に示す同時焼成用グリーンシー
ト1.2.3を用いた本発明の実施例を示す、内部配線
用Ag導体ペースト4をグリーンシート2上に印刷し、
また外部に出るセラミックグリンシート1上には外部配
線用Ag−Pdペースト5を印刷しさらに、オーバーコ
ート8として外部配線用Ag−Pdペースト上にセラミ
ックグリーンシートと同一のセラミック材料を用いたペ
ーストを印刷した。こうして作製した配線印刷とスルー
ホール6内に本発明の導体となる導体ペースト7が充填
されたセラミックグリンシート1を第1層とし、2.3
層はスルーホールのないセラミックグリンシートとして
、この3枚を加熱圧着して積層した。
Examples 1 to 6 are examples of the present invention using the green sheet 1.2.3 for simultaneous firing shown in FIG.
Furthermore, an Ag-Pd paste 5 for external wiring is printed on the ceramic green sheet 1 exposed to the outside, and a paste made of the same ceramic material as the ceramic green sheet is printed on the Ag-Pd paste for external wiring as an overcoat 8. Printed. The printed wiring and the ceramic green sheet 1 filled with the conductive paste 7 which becomes the conductor of the present invention in the through holes 6 are used as the first layer, and 2.3
The layers were ceramic green sheets without through holes, and these three sheets were heat-pressed and laminated.

次いで、空気雰囲気中の900°Cで焼成して同時焼成
セラミック回路基板とした。こうして得た試験片を用い
て信頼性試験として、温度サイクル試験(条件は一40
℃〜+150℃、100サイクル)を行って、導通抵抗
の変化率、またセラミックおよび導体周辺のクラック発
生の有無を調べた。その結果を第1表に示した。
Then, it was fired at 900°C in an air atmosphere to obtain a co-fired ceramic circuit board. Using the test piece obtained in this way, a temperature cycle test (conditions were -40
C. to +150.degree. C. for 100 cycles) to examine the rate of change in conduction resistance and the presence or absence of cracks around the ceramic and conductor. The results are shown in Table 1.

第1表 実施例4のSb2O.はsbレジネートで添加し、その
ほかは5b2o、無機物で添加した。また、実施例1の
RhはRhレジネートで添加し、そのほかはRh金属粉
末で添加した。
Table 1 Example 4 Sb2O. was added as sb resinate, and the others were added as 5b2o and inorganic substances. Further, Rh in Example 1 was added as Rh resinate, and the others were added as Rh metal powder.

実施例では信頼性試験後、導体周辺および導体中にクラ
ックの発生は全くなく、また導通抵抗の変化率は±0.
9X以内であった。一方、比較例2は、焼成後には、ク
ラックの発生はみられなかったが、温度サイクル試験後
にクラックが発生し導通抵抗の変化率は+2%以上であ
った。比較例は焼成後にオーバコートにクラックの発生
がみられた。
In the example, after the reliability test, there were no cracks around or inside the conductor, and the rate of change in conduction resistance was ±0.
It was within 9X. On the other hand, in Comparative Example 2, no cracks were observed after firing, but cracks occurred after the temperature cycle test, and the rate of change in conduction resistance was +2% or more. In the comparative example, cracks were observed in the overcoat after firing.

なお、本発明はスルーホールと必要な配線を有する1層
の回路基板であっても良いことは当然であり、スルーホ
ール導体を形成する必要があるセラミック多層回路基板
を作製する全てに利用できる。また、セラミックグリン
シートの代わりにセラミック絶縁体ペーストを用いて多
層化する、いわゆる印刷積層多層回路基板にも応用でき
る。
It should be noted that the present invention can of course be applied to a single-layer circuit board having through holes and necessary wiring, and can be used for all productions of ceramic multilayer circuit boards that require the formation of through hole conductors. It can also be applied to so-called printed laminated multilayer circuit boards that are multilayered using ceramic insulating paste instead of ceramic green sheets.

ハ2発明の効果 本発明によれば、スルーホール導体およびその周辺にク
ラックの発生のない高信頼性の同時焼成セラミック回路
基板を低温焼成で得ることができる。
C.2 Effects of the Invention According to the present invention, a highly reliable co-fired ceramic circuit board free of cracks in through-hole conductors and their surroundings can be obtained by low-temperature firing.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明のRhとSb2O3の範囲を図示したも
ので斜線部が本発明の範囲を示す。 第2図は本発明の1実施例を示すセラミック多層配線基
板の断面図である。 1.2.3・・・セラミックグリンシート、4・・・内
層導体、5・・・外層導体、6・・・スルーホール、7
・・・スルーホール導体、8・・・オーバーコート。 特許出願人   鳴海製陶株式会社 第2図 手続補正書(自発) 1゜ 2゜ 3゜ 事件の表示 平成1年特許願第098531、 発明の名称 同時焼成セラミック回路基板 補正をする者 事件との関係  特許出願人 〒 458 住所 名古屋市緑区鳴海町字伝治山3番地4゜ 5゜ 6゜ 補正の命令の日付 補正の対象 図面の第1図 補正の内容 別紙のとおり 自発 X=Rh (重量部)
FIG. 1 illustrates the range of Rh and Sb2O3 of the present invention, and the shaded area indicates the range of the present invention. FIG. 2 is a sectional view of a ceramic multilayer wiring board showing one embodiment of the present invention. 1.2.3...Ceramic green sheet, 4...Inner layer conductor, 5...Outer layer conductor, 6...Through hole, 7
...Through-hole conductor, 8...Overcoat. Patent applicant: Narumi Seito Co., Ltd. Figure 2 Procedural amendment (voluntary) 1゜2゜3゜Indication of the case 1999 Patent Application No. 098531, Name of the invention Relationship to the person who amends the co-fired ceramic circuit board case Patent applicant: 458 Address: 3-4, Denjiyama, Narumi-cho, Midori-ku, Nagoya City

Claims (1)

【特許請求の範囲】[Claims] (1)スルーホール充填導体がAg、Rh、Sb_2O
_3よりなり、その組成割合がAg100重量部に対し
RhとSb_2O_3をそれぞれ、XおよびY重量部と
したとき、X、Yが下記式の範囲内 (−5/2)X+10.0≧Y≧(−5)X+0.05
、X≧0,Y≧0を満足することを特徴とする同時焼成
セラミック回路基板。
(1) Through-hole filling conductor is Ag, Rh, Sb_2O
When Rh and Sb_2O_3 are X and Y parts by weight, respectively, with respect to 100 parts by weight of Ag, X and Y are within the range of the following formula (-5/2) X+10.0≧Y≧( -5)X+0.05
, X≧0, Y≧0.
JP9853189A 1989-04-18 1989-04-18 Co-fired ceramic circuit board Expired - Lifetime JPH0738493B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9853189A JPH0738493B2 (en) 1989-04-18 1989-04-18 Co-fired ceramic circuit board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9853189A JPH0738493B2 (en) 1989-04-18 1989-04-18 Co-fired ceramic circuit board

Publications (2)

Publication Number Publication Date
JPH02277279A true JPH02277279A (en) 1990-11-13
JPH0738493B2 JPH0738493B2 (en) 1995-04-26

Family

ID=14222262

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9853189A Expired - Lifetime JPH0738493B2 (en) 1989-04-18 1989-04-18 Co-fired ceramic circuit board

Country Status (1)

Country Link
JP (1) JPH0738493B2 (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0584726A1 (en) * 1992-08-21 1994-03-02 Sumitomo Metal Ceramics Inc. Method of fabricating ceramic circuit substrate
JPH0669651A (en) * 1992-08-21 1994-03-11 Sumitomo Kinzoku Ceramics:Kk Manufacture of ceramic circuit board
JPH07235215A (en) * 1994-02-24 1995-09-05 Nikko Co Conductive paste for filling through hole
JPH08222852A (en) * 1995-02-14 1996-08-30 Nikko Co Manufacture of through hole filled up with conductor
US5723073A (en) * 1995-03-30 1998-03-03 Sumitomo Metal (Smi) Electronics Devices Inc. Conductive paste containing 2-tetradecanol and ceramic circuit substrate using the same

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0584726A1 (en) * 1992-08-21 1994-03-02 Sumitomo Metal Ceramics Inc. Method of fabricating ceramic circuit substrate
JPH0669651A (en) * 1992-08-21 1994-03-11 Sumitomo Kinzoku Ceramics:Kk Manufacture of ceramic circuit board
JPH07235215A (en) * 1994-02-24 1995-09-05 Nikko Co Conductive paste for filling through hole
JPH08222852A (en) * 1995-02-14 1996-08-30 Nikko Co Manufacture of through hole filled up with conductor
US5723073A (en) * 1995-03-30 1998-03-03 Sumitomo Metal (Smi) Electronics Devices Inc. Conductive paste containing 2-tetradecanol and ceramic circuit substrate using the same
DE19611239B4 (en) * 1995-03-30 2005-10-06 Murata Manufacturing Co. Ltd. Conductive paste

Also Published As

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