JPS63289941A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS63289941A JPS63289941A JP62125404A JP12540487A JPS63289941A JP S63289941 A JPS63289941 A JP S63289941A JP 62125404 A JP62125404 A JP 62125404A JP 12540487 A JP12540487 A JP 12540487A JP S63289941 A JPS63289941 A JP S63289941A
- Authority
- JP
- Japan
- Prior art keywords
- bonding
- semiconductor chip
- pad
- semiconductor
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 46
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 8
- 238000000034 method Methods 0.000 claims abstract description 15
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 claims abstract description 12
- 238000005530 etching Methods 0.000 claims abstract description 12
- 238000001020 plasma etching Methods 0.000 claims abstract description 5
- 239000000758 substrate Substances 0.000 abstract description 3
- 238000004140 cleaning Methods 0.000 abstract description 2
- 239000000356 contaminant Substances 0.000 abstract 3
- 239000007767 bonding agent Substances 0.000 abstract 1
- 238000012360 testing method Methods 0.000 description 7
- 239000000463 material Substances 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000000465 moulding Methods 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 238000007865 diluting Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 239000012778 molding material Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 230000003252 repetitive effect Effects 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/85009—Pre-treatment of the connector or the bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/85009—Pre-treatment of the connector or the bonding area
- H01L2224/8501—Cleaning, e.g. oxide removal step, desmearing
- H01L2224/85013—Plasma cleaning
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置に於けるボンディング工程に関し、
特にＡｕ線の半導体チップパッド上に於ける付き方に関
する。[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a bonding process in a semiconductor device,
In particular, it relates to how Au wires are attached on semiconductor chip pads.
従来、半導体装置に於ける組立工程は第２図の様にダイ
シングしてチップ化した半導体チップ１をタブ２上にグ
イボンド材３を用いて接着する。Conventionally, in the assembly process of a semiconductor device, as shown in FIG. 2, a semiconductor chip 1 that has been diced into chips is bonded onto a tab 2 using a bonding material 3.
これをボンディング装置により、リードフレーム側の電
極４を半導体側のＡρ電極（パッド）とをＡｕ線５を用
いて配線を施した。 更にこの後、モールド工程にてモ
ールド６を行ないパッケージして半導体装置としていた
。A bonding device was used to wire the electrode 4 on the lead frame side with the Aρ electrode (pad) on the semiconductor side using Au wire 5. Furthermore, after this, a mold 6 was performed in a molding process, and the semiconductor device was packaged.
しかしながら、この組立工程中のボンディング時に於い
て、ダイシングしチップ状態にした半導体チップを放置
した後（放置条件として低湿条件にて放置）低湿条件に
てチップを管理したのにもかかわらずボンディングを実
施すると、半導体チップのＡβバッド部は空気中の酸素
と結合し薄い酸化膜がＡ！Ｑパッド上に形成され、たび
たびソードフレーム電極部４と半導体チップ１上のＡ！
Ｑｆｌｉ（板部とのＡｕ配線５がうよ（ボンディングさ
れないきいう大きな間過が発生する。（っまりプアーボ
ンドが発生するｅ）また、ダイシング後、速ボンディン
グを実施し、Ａｕ線５のリードフレーム−半導体チップ
間の配線が外観上問題な（ボンディングされたとしても
、温度サイクル（冷却−加温の繰り返し）試験に於いて
モールド材の収縮、膨張の操り返しによりＡｕ！Ｉが半
導体チップのパッド上から断線してしまい半導体装置の
歩留りが低下するという大きな問題が発生している。However, at the time of bonding during this assembly process, bonding was performed even though the chips were managed under low humidity conditions after the diced semiconductor chips were left in the form of chips (left in low humidity conditions). Then, the Aβ pad portion of the semiconductor chip combines with oxygen in the air and a thin oxide film forms A! The A! pad is formed on the Q pad, and the A!
Qfli (Au wire 5 with the plate part is stuck (a large gap occurs when bonding is not done. - The wiring between semiconductor chips is visually problematic (even if they are bonded, Au!I is damaged by the shrinkage and expansion of the molding material during temperature cycle (repetitive cooling and heating) tests). A major problem has arisen in that wires break from above, reducing the yield of semiconductor devices.
本発明の目的はかかる従来技術の欠陥をなくして、半導
体チップをボンディングする際に於ケルプアーボンディ
ングをなくし信頼性の高い半導体を提供するものである
。SUMMARY OF THE INVENTION An object of the present invention is to eliminate the deficiencies of the prior art and to provide a highly reliable semiconductor that eliminates Kelper bonding when bonding semiconductor chips.
本発明による半導体装置の製造方法は先ず、ボンディン
グする前にプラズマエツチング及びそれに付随する装置
、またその他フッ酸等のエツチング液により半導体チッ
プのパッド表面とに付着している薄い酸化膜、及び汚れ
等をエツチングした後、ボンディングすることを特徴と
する。In the method of manufacturing a semiconductor device according to the present invention, first, before bonding, plasma etching and associated equipment, and other etching solutions such as hydrofluoric acid are used to remove thin oxide films and dirt attached to the pad surface of the semiconductor chip. It is characterized by bonding after etching.
本発明の実施例を、図面を用いて詳細に説明する。先ず
、第１図はウェハー上に形成されている数百個からなる
半導体チップの中の１個の断面図である。この半導体チ
ップを作製する方法を述べるとＳｉ基板７上に形成され
た能動素子上に５ｉＯ１膜を形成して成るフィールド酸
化膜８上にＡ℃の配線を施し、素子間のコンタクトをと
り次にＣＶＤ法によりパッジベージ９ン膜９を形成後Ａ
ρパッド部１０のみエツチングした。更にこのウェハー
状の半導体をダイシング装置を用いて縦、横にカットし
、半導体チップとしていた。この半導体チップをリード
フレームのグイ上に５〜６個程度直列にグイボンド材を
用いて表替した。この様にして半導体チップを配列して
できたリードフレームを２５枚１０ツトとしてプラズマ
ＨＭに入れ半導体装置のＡｆ！パッド上に若干薄（形成
された酸化膜をエツチング除去した。更にこの後、０゜
クリーニングにてＡ！２パッドの表面の汚れ等をクリー
ニングした。また、更にこのリードフレーム上の半導体
チップにあるパッド部上のＡ！２電極１０にＡｕ配線を
施した。次にこの半導体装置をパッケージングする為に
モールド樹脂を封入した。Embodiments of the present invention will be described in detail using the drawings. First, FIG. 1 is a cross-sectional view of one of several hundred semiconductor chips formed on a wafer. To describe the method for manufacturing this semiconductor chip, wiring at A° C. is formed on the field oxide film 8, which is made by forming a 5iO1 film on the active elements formed on the Si substrate 7, contacts between the elements are made, and then After forming the padding film 9 by CVD method A
Only the ρ pad portion 10 was etched. Furthermore, this wafer-shaped semiconductor was cut vertically and horizontally using a dicing device to obtain semiconductor chips. About 5 to 6 of these semiconductor chips were placed in series on the gougs of a lead frame using a goobond material. Twenty-five lead frames made by arranging semiconductor chips in this way are placed in a plasma HM to produce a semiconductor device. A slightly thin oxide film (formed on the pad) was removed by etching.Furthermore, after this, dirt etc. on the surface of the A!2 pad was cleaned using 0° cleaning. Au wiring was applied to the A!2 electrode 10 on the pad portion.Next, a molding resin was sealed in order to package this semiconductor device.
この後、最終工程であるメツキープレス工程を経て半導
体装置とした。この様にしてできた半導体装置を信頼性
試験評価する為に５０ケサンプルを作成し投入した。信
頼性評価として、バーンイン試験、プレッシャークツカ
ー試験、温度サイクル試験等あらゆる過酷な試験を長時
間実施した。この結果ワイヤーボンディングに起因した
ワイヤーオープン状態については皆無であった。従来こ
の様な試験を実施した場合ワイヤーオーブン状態となる
確率は２０％程度であり従来と比較し数段の向上となっ
た。Thereafter, a semiconductor device was obtained through a Metsky press process, which is the final process. In order to evaluate the reliability of the semiconductor device manufactured in this manner, 50 samples were prepared and used. To evaluate reliability, we conducted a variety of harsh tests over a long period of time, including burn-in tests, pressure stress tests, and temperature cycle tests. As a result, there were no wire open states caused by wire bonding. Conventionally, when such a test was carried out, the probability of a wire oven condition occurring was about 20%, which was an improvement of several orders of magnitude compared to the conventional method.
尚、以上本発明ではエツチング装置としてプラズマ装置
を用いて説明したが、この他にもそれと問答の効力のあ
る装置か、更にはフッ酸等の液体を希釈したエツチング
液を用いてエツチングを施してもよい。しかしこの時、
半導体チップのＡ！Ｑパッド以外にも影響を及ぼさない
様にマスクをかけてエツチングする。この様にしてでき
た半導体ＨＣを信願性試験に投入したがプラズマ装置を
用いてエツチングした物と何ら変わらない物が得られた
。Although the present invention has been explained above using a plasma device as an etching device, etching can also be performed using a device that has the same effect as a plasma device or an etching solution prepared by diluting a liquid such as hydrofluoric acid. Good too. But at this time,
A for semiconductor chips! Etching is done with a mask on so as not to affect anything other than the Q pad. When the semiconductor HC produced in this manner was subjected to reliability testing, it was obtained that was no different from that etched using a plasma device.
以上の如く本発明によれば、半導体チップのＡβバッド
部をボンディングする前にプラズマエツチング及びそれ
に付随する装置、またその他フッ酸等のエツチング液に
より若干薄く残っている酸化膜をエツチングすることに
よりボンディングの付きが良好となりモールド封入部の
ワイヤーオープン状態が、従来と比較して向上されるも
のである。As described above, according to the present invention, before bonding the Aβ pad portion of a semiconductor chip, bonding is performed by etching the slightly thin remaining oxide film using plasma etching and associated equipment, and an etching solution such as hydrofluoric acid. This improves the adhesion of wires and improves the open state of the wire in the molded part compared to the conventional method.
第１図は、本発明の半導体チップの構造図である。
第２図は従来から実施されている半導体装置組立工程に
於ける断固図である。
１・・・半導体チップ
２・・・ソードフレームのタブ
３・・・グイボンド材
４・・・リードフレーム側の電極
５・・・Ａｕ線
６・・・モールド
７・・・Ｓｉ基板
８・・・フィールド酸化膜
９・・・バッジベージ３ン膜
１０・・・Ａ！Ｑ電極部（パッド部）
以 上
第７図
と
第２１７FIG. 1 is a structural diagram of a semiconductor chip of the present invention. FIG. 2 is a schematic diagram of a conventional semiconductor device assembly process. 1... Semiconductor chip 2... Sword frame tab 3... Guibond material 4... Lead frame side electrode 5... Au wire 6... Mold 7... Si substrate 8... Field oxide film 9...badge base 3-in film 10...A! Q electrode part (pad part) Above Figure 7 and Figure 217
Claims (1)
導体チップをボンディングする半導体装置の製造方法に
於いて、該半導体チップをボンディングする前にプラズ
マエッチング装置及びそれに付随する装置、更にはフッ
酸等で半導体チップの、パッド表面の汚れ及び薄く残っ
ている酸化膜をエッチングした後、ボンディングを実施
することを特徴とする半導体装置の製造方法。 ２、エッチング時には半導体チップをリードフレーム上
にダイボンドした後、該チップのパツドをエッチングす
る特許請求の範囲第１項記載の半導体装置の製造方法。[Claims] 1. Process step - In a method for manufacturing a semiconductor device in which a semiconductor chip manufactured through a dicing step is bonded, a plasma etching device and associated devices are used before bonding the semiconductor chip; A method for manufacturing a semiconductor device, characterized in that bonding is performed after etching dirt and a thin remaining oxide film on the pad surface of a semiconductor chip with hydrofluoric acid or the like. 2. The method of manufacturing a semiconductor device according to claim 1, wherein during etching, the semiconductor chip is die-bonded onto the lead frame, and then the pad of the chip is etched.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62125404A JPS63289941A (en) | 1987-05-22 | 1987-05-22 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62125404A JPS63289941A (en) | 1987-05-22 | 1987-05-22 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63289941A true JPS63289941A (en) | 1988-11-28 |
Family
ID=14909281
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62125404A Pending JPS63289941A (en) | 1987-05-22 | 1987-05-22 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63289941A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1109213A2 (en) * | 1999-12-14 | 2001-06-20 | Infineon Technologies AG | Method for producing a semiconductor device |
-
1987
- 1987-05-22 JP JP62125404A patent/JPS63289941A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1109213A2 (en) * | 1999-12-14 | 2001-06-20 | Infineon Technologies AG | Method for producing a semiconductor device |
| US6436731B2 (en) | 1999-12-14 | 2002-08-20 | Infineon Technologies Ag | Method of producing a semiconductor device comprising a cleaning process for removing silicon-containing material |
| EP1109213A3 (en) * | 1999-12-14 | 2003-11-26 | Infineon Technologies AG | Method for producing a semiconductor device |
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