JP2772447B2 - Method for manufacturing optical semiconductor device - Google Patents

Method for manufacturing optical semiconductor device

Info

Publication number
JP2772447B2
JP2772447B2 JP4019010A JP1901092A JP2772447B2 JP 2772447 B2 JP2772447 B2 JP 2772447B2 JP 4019010 A JP4019010 A JP 4019010A JP 1901092 A JP1901092 A JP 1901092A JP 2772447 B2 JP2772447 B2 JP 2772447B2
Authority
JP
Japan
Prior art keywords
resin
wiring pattern
dimensional wiring
insulating substrate
optical semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP4019010A
Other languages
Japanese (ja)
Other versions
JPH05218508A (en
Inventor
弘文 進藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Consejo Superior de Investigaciones Cientificas CSIC
Original Assignee
Consejo Superior de Investigaciones Cientificas CSIC
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Consejo Superior de Investigaciones Cientificas CSIC filed Critical Consejo Superior de Investigaciones Cientificas CSIC
Priority to JP4019010A priority Critical patent/JP2772447B2/en
Publication of JPH05218508A publication Critical patent/JPH05218508A/en
Application granted granted Critical
Publication of JP2772447B2 publication Critical patent/JP2772447B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • BPERFORMING OPERATIONS; TRANSPORTING
    • B29WORKING OF PLASTICS; WORKING OF SUBSTANCES IN A PLASTIC STATE IN GENERAL
    • B29CSHAPING OR JOINING OF PLASTICS; SHAPING OF MATERIAL IN A PLASTIC STATE, NOT OTHERWISE PROVIDED FOR; AFTER-TREATMENT OF THE SHAPED PRODUCTS, e.g. REPAIRING
    • B29C45/00Injection moulding, i.e. forcing the required volume of moulding material through a nozzle into a closed mould; Apparatus therefor
    • B29C45/14Injection moulding, i.e. forcing the required volume of moulding material through a nozzle into a closed mould; Apparatus therefor incorporating preformed parts or layers, e.g. injection moulding around inserts or for coating articles
    • B29C45/14639Injection moulding, i.e. forcing the required volume of moulding material through a nozzle into a closed mould; Apparatus therefor incorporating preformed parts or layers, e.g. injection moulding around inserts or for coating articles for obtaining an insulating effect, e.g. for electrical components
    • B29C45/14655Injection moulding, i.e. forcing the required volume of moulding material through a nozzle into a closed mould; Apparatus therefor incorporating preformed parts or layers, e.g. injection moulding around inserts or for coating articles for obtaining an insulating effect, e.g. for electrical components connected to or mounted on a carrier, e.g. lead frame
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93Batch processes
    • H01L24/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B29WORKING OF PLASTICS; WORKING OF SUBSTANCES IN A PLASTIC STATE IN GENERAL
    • B29CSHAPING OR JOINING OF PLASTICS; SHAPING OF MATERIAL IN A PLASTIC STATE, NOT OTHERWISE PROVIDED FOR; AFTER-TREATMENT OF THE SHAPED PRODUCTS, e.g. REPAIRING
    • B29C45/00Injection moulding, i.e. forcing the required volume of moulding material through a nozzle into a closed mould; Apparatus therefor
    • B29C45/14Injection moulding, i.e. forcing the required volume of moulding material through a nozzle into a closed mould; Apparatus therefor incorporating preformed parts or layers, e.g. injection moulding around inserts or for coating articles
    • B29C45/14065Positioning or centering articles in the mould
    • B29C2045/14098Positioning or centering articles in the mould fixing or clamping inserts having variable dimensions
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144Gold (Au) as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Mechanical Engineering (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Led Device Packages (AREA)

Abstract

PURPOSE:To prevent resin from leaking during resin injection and 3-dimensional wiring pattern from being damaged by forming a resin leakage preventing wall in an armor part of an insulating substrate and by pressing a pressing part of a molding die to the resin leakage preventing wall by the use of a spring. CONSTITUTION:An insulating substrate 1 is formed with a plurality of devices in series integrally and a 3-dimensional wiring pattern P is formed thereon. In the process, a resin leakage preventing wall is formed in an armor part of the insulating substrate 1 as thick as the 3-dimensional wiring pattern P. Then, resin is injected once from a runner part through a gate for a plurality of devices by using dies 10, 11 and then sealed to form a package 8 having a lens 6. In the process, pressing parts 10a, 11a of the dies 10, 11 are pressed floatably to the 3-dimensional wiring pattern P and the resin leakage preventing wall by a spring 14. Thereafter, dicing is performed by a dicing line to remove the runner part and the gate. Thereby, it is possible to prevent resin from leaking during resin injection.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【産業上の利用分野】本発明は、リードレスタイプの樹
脂封止型光半導体装置の製造方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a leadless type resin-sealed optical semiconductor device.

【0002】[0002]

【従来の技術】従来のリードレスタイプの光半導体装置
における面実装デバイス(以下、SMDと称す)は、図
7の如く、電極を形成するためのスルーホールS(貫通
穴)を有する樹脂製絶縁基板1に、光半導体素子2(光
電変換素子)を搭載するためのヘツダー部3と、光半導
体素子2の電極と電気的にワイヤボンデイング接続する
結線部4とを有する立体配線パターンPが立体配線パタ
ーン形成されている。この絶縁基板1の材質としては、
ガラスエポキシ樹脂等が用いられている。
2. Description of the Related Art As shown in FIG. 7, a conventional surface mount device (hereinafter referred to as SMD) in a leadless type optical semiconductor device has a resin insulation having a through hole S (through hole) for forming an electrode. A three-dimensional wiring pattern P having a header part 3 for mounting an optical semiconductor element 2 (photoelectric conversion element) on a substrate 1 and a connection part 4 electrically connected to the electrodes of the optical semiconductor element 2 by wire bonding is formed by three-dimensional wiring. The pattern is formed. As a material of the insulating substrate 1,
Glass epoxy resin or the like is used.

【0003】図7に示す光半導体素子2は絶縁基板1上
に積層されたヘツダー部3に導電性ペーストにてダイボ
ンドされ、さらに、この光半導体素子2は、結線部4と
金線等のボンデイングワイヤ5により結線される。
The optical semiconductor device 2 shown in FIG. 7 is die-bonded with a conductive paste to a header portion 3 laminated on an insulating substrate 1, and furthermore, the optical semiconductor device 2 is bonded to a connection portion 4 and a gold wire or the like. The wires 5 are connected.

【0004】そして、光半導体素子2は、図8の如く、
透光性樹脂を用いてトランスフアー成型法にて樹脂封止
され、レンズ6が有せしめられる。トランスフアーモー
ルドの方法としては、図8の如く、ランナー部7をパツ
ケージ8となる部分以外に設け、ランナー部7からゲー
ト9を介して、樹脂を注入して封止し、その後、ランナ
ー部7およびゲート9を除去すべく、ダイシングライン
Dでダイシングし、単独のSMD光半導体装置を製造す
る(図2〜3参照)。
[0004] The optical semiconductor element 2 is, as shown in FIG.
Using a translucent resin, resin sealing is performed by a transfer molding method, and the lens 6 is provided. As a method of transfer molding, as shown in FIG. 8, a runner portion 7 is provided in a portion other than a portion to be a package 8, a resin is injected from the runner portion 7 through a gate 9, and the resin is sealed. Then, dicing is performed at a dicing line D to remove the gate 9 to manufacture a single SMD optical semiconductor device (see FIGS. 2 and 3).

【0005】なお、図9〜11は、成形金型10,11
を用いて樹脂封止した状態を示す図である。図11中、
10a,11aは成形金型10,11の押さえ部、12
は樹脂注入口、13はプランジー(ピストン)を示して
いる。
FIGS. 9 to 11 show molding dies 10 and 11.
FIG. 3 is a view showing a state in which resin sealing is performed by using FIG. In FIG.
10a and 11a are holding portions of the molding dies 10 and 11;
Denotes a resin inlet, and 13 denotes a plunge (piston).

【0006】[0006]

【発明が解決しようとする課題】従来の光半導体装置の
製造方法において、トランスフアー成型を行なう際、図
9,10の如く、成形金型10,11で絶縁基板1をク
ランプして成形する。
In the conventional method of manufacturing an optical semiconductor device, when performing transfer molding, as shown in FIGS. 9 and 10, the insulating substrate 1 is clamped and molded by molding dies 10 and 11. As shown in FIG.

【0007】ここで、絶縁基板1上の立体配線パターン
Pは、片側約20μmの厚さを有するため、この立体配
線パターンPの配されていない部分について絶縁基板1
と成形金型10,11との間に隙間d(図9)が生じ
る。この隙間dから樹脂が漏れないようにするには、モ
ールド金型10,11で立体配線パターンPをつぶして
でも隙間dを塞がなければならない。このため、成形金
型10,11の当たる領域と樹脂封止される領域の境界
部分で、立体配線パターンPが切れてしまうといつた現
象が発生する。
Here, the three-dimensional wiring pattern P on the insulating substrate 1 has a thickness of about 20 μm on one side.
A gap d (FIG. 9) is generated between the mold and the molding dies 10, 11. In order to prevent the resin from leaking from the gap d, the gap d must be closed even if the three-dimensional wiring pattern P is crushed by the mold dies 10 and 11. For this reason, a phenomenon occurs when the three-dimensional wiring pattern P is cut at the boundary between the regions where the molding dies 10 and 11 are applied and the region to be sealed with resin.

【0008】なお、他の方法として、金属製リードフレ
ームを成形金型でクランプする方法もある。この場合、
金属製リードフレームの厚み公差は一般的に小さい。こ
れに対し、図9,10のような絶縁基板1を用いる場
合、光半導体装置全体を小型化できるといつた利点があ
るが、絶縁基板1の成形時の厚み公差は金属製リードフ
レームに比べて大となつてしまう。
As another method, there is a method of clamping a metal lead frame with a molding die. in this case,
The thickness tolerance of metal lead frames is generally small. On the other hand, when the insulating substrate 1 as shown in FIGS. 9 and 10 is used, there is an advantage that the entire optical semiconductor device can be reduced in size. And become big.

【0009】このため、絶縁基板1の厚み公差の最も薄
い状態を考慮して、成型金型10,11の押さえ部10
a,11aの厚み寸法を決めると、前述のように、絶縁
基板1がこの設計寸法より厚い場合に、立体配線パター
ンPを完全に切断してしまい、不良品発生の要因となつ
ていた。
For this reason, taking into account the state where the thickness tolerance of the insulating substrate 1 is the smallest, the pressing portions 10 of the molding dies 10 and 11 are considered.
When the thickness dimensions of a and 11a are determined, as described above, when the insulating substrate 1 is thicker than this design dimension, the three-dimensional wiring pattern P is completely cut, which is a cause of defective products.

【0010】逆に、この現象を防止するため、絶縁基板
1の厚み公差の最も厚い状態を考慮して、押さえ部10
a,11aの厚み寸法を決め、成形金型10,11の押
さえ圧力を小さくすることもできる。しかし、そうすれ
ば、基板1と金型との隙間dが大となり、この隙間dか
ら樹脂が漏れてしまい、樹脂コストを節約できないばか
りか、成形金型10,11から樹脂がはみ出して形状が
不定形となることから、取り扱いに手間取るといつた欠
点があつた。
Conversely, in order to prevent this phenomenon, taking into account the state where the thickness tolerance of the insulating substrate 1 is the largest, the holding portion 10
It is also possible to reduce the pressing pressure of the molding dies 10 and 11 by determining the thickness dimensions of a and 11a. However, in this case, the gap d between the substrate 1 and the mold becomes large, and the resin leaks from the gap d, so that the resin cost cannot be saved, and the resin protrudes from the molding dies 10, 11 to form the resin. Because of the irregular shape, there was a drawback when it took time to handle.

【0011】本発明は、上記課題に鑑み、成型時の樹脂
漏れを発生させず、かつ絶縁基板上の立体配線パターン
の損傷を小さくし、品質を向上し得る光半導体装置の製
造方法の提供を目的とする。
SUMMARY OF THE INVENTION In view of the above problems, the present invention provides a method of manufacturing an optical semiconductor device that does not cause resin leakage during molding, reduces damage to a three-dimensional wiring pattern on an insulating substrate, and improves quality. Aim.

【0012】[0012]

【課題を解決するための手段】本発明請求項1による課
題解決手段は、図1の如く、絶縁基板1に立体配線パタ
ーンPを設け、該立体配線パターンP上に複数の光半導
体素子2を搭載し、絶縁基板1を成形金型10,11の
押さえ部10a,11aで押さえながら複数の光半導体
素子2を透光性樹脂にてモールドして複数のパツケージ
8を形成する光半導体装置の製造方法において、前記絶
縁基板1の外郭部に、樹脂漏れ防止壁21を立体配線パ
ターンPと同厚に形成し、前記成形金型10,11の少
なくとも一方の押さえ部10aを遊動自在とし、該押さ
え部10aをばね14にて立体配線パターンPおよび樹
脂漏れ防止壁21に押圧し、押さえ部10aと樹脂漏れ
防止壁21との密着力により、樹脂注入時の樹脂漏れを
防止するものである。
According to the first aspect of the present invention, as shown in FIG. 1, a three-dimensional wiring pattern P is provided on an insulating substrate 1 and a plurality of optical semiconductor elements 2 are provided on the three-dimensional wiring pattern P. Manufacturing of an optical semiconductor device in which a plurality of optical semiconductor elements 2 are molded with a translucent resin while mounting the insulating substrate 1 with the holding portions 10a and 11a of the molding dies 10 and 11 to form a plurality of packages 8. In the method, a resin leakage preventing wall 21 is formed on the outer peripheral portion of the insulating substrate 1 to have the same thickness as the three-dimensional wiring pattern P, and at least one holding portion 10a of the molding dies 10, 11 is made freely movable. The portion 10a is pressed by the spring 14 against the three-dimensional wiring pattern P and the resin leakage prevention wall 21, and the adhesion between the holding portion 10a and the resin leakage prevention wall 21 prevents resin leakage during resin injection. .

【0013】本発明請求項2による課題解決手段は、請
求項1記載の樹脂漏れ防止壁21は、立体配線パターン
Pと同一材料を用いて同時にパターン形成するものであ
る。
According to a second aspect of the present invention, the resin leakage preventing wall 21 according to the first aspect is formed by using the same material as the three-dimensional wiring pattern P at the same time.

【0014】[0014]

【作用】上記請求項1による課題解決手段において、樹
脂成形時に、成形金型10,11の押さえ部10a,1
1aで絶縁基板1を押さえる際、押さえ部10aは成形
金型10,11に対して遊動自在であるから、ばね14
により絶縁基板1および立体配線パターンPに加わる圧
力を適正に調整できる。
According to the first aspect of the present invention, the pressing portions 10a, 1 of the molding dies 10, 11 are formed during resin molding.
When the insulating substrate 1 is pressed by 1a, the pressing portion 10a is freely movable with respect to the molding dies 10, 11, so that the spring 14
Thereby, the pressure applied to the insulating substrate 1 and the three-dimensional wiring pattern P can be appropriately adjusted.

【0015】この場合、絶縁基板1上の立体配線パター
ンPが配されていない部分について、樹脂注入時に押さ
え部10aと絶縁基板1との間の隙間dから樹脂が漏れ
ても、外郭部で樹脂漏れ防止壁21と押さえ部10aと
が密着するため、樹脂の流れを止めることができる。
In this case, even if the resin leaks from the gap d between the holding portion 10a and the insulating substrate 1 at the time of injecting the resin into the portion where the three-dimensional wiring pattern P on the insulating substrate 1 is not arranged, Since the leak prevention wall 21 and the holding portion 10a are in close contact with each other, the flow of the resin can be stopped.

【0016】請求項2では、絶縁基板1上の樹脂漏れ防
止壁21を立体配線パターンPと同一材料を用いて同時
にパターン形成し、部材追加による工程数の増加を防
ぐ。
According to the second aspect, the resin leakage preventing wall 21 on the insulating substrate 1 is simultaneously formed using the same material as the three-dimensional wiring pattern P to prevent an increase in the number of steps due to the addition of members.

【0017】[0017]

【実施例】図1は本発明の一実施例に使用する成形金型
の構造概念図、図2は光半導体素子の完成状態を示す平
面図、図3は図2のA−A断面図、図4は図2のB−B
断面図、図5は絶縁基板上の立体配線パターンおよび樹
脂漏れ防止壁を示す平面図、図6は絶縁基板の断面図で
ある。なお、従来と同一機能を有する部材は、同一符号
を付している。
FIG. 1 is a structural conceptual view of a molding die used in one embodiment of the present invention, FIG. 2 is a plan view showing a completed state of an optical semiconductor device, FIG. 3 is a sectional view taken along line AA of FIG. FIG. 4 is BB of FIG.
FIG. 5 is a plan view showing a three-dimensional wiring pattern and a resin leakage preventing wall on the insulating substrate, and FIG. 6 is a sectional view of the insulating substrate. Note that members having the same functions as those in the related art are denoted by the same reference numerals.

【0018】本実施例の光半導体装置は、リードレスタ
イプの面実装デバイス(以下、SMDと称す)であり、
図2〜4の如く、ガラスエポキシ樹脂等からなる絶縁基
板1の上面に、立体配線パターンPがメツキ法または金
属蒸着法にて形成され、そのヘツダー部3に光半導体素
子2(光電変換素子)が搭載され、光半導体素子2の電
極と立体配線パターンPの結線部4との間にボンデイン
グワイヤ5が結線され、さらに透光性樹脂を用いてトラ
ンスフアー成型法にて樹脂封止され、レンズ6を有する
パツケージ8が形成されてなる。
The optical semiconductor device of this embodiment is a leadless type surface mount device (hereinafter referred to as SMD).
As shown in FIGS. 2 to 4, a three-dimensional wiring pattern P is formed on the upper surface of an insulating substrate 1 made of a glass epoxy resin or the like by a plating method or a metal vapor deposition method. Is mounted, a bonding wire 5 is connected between the electrode of the optical semiconductor element 2 and the connection portion 4 of the three-dimensional wiring pattern P, and is further sealed with a resin using a translucent resin by a transfer molding method. 6 is formed.

【0019】また、本実施例で用いられる金型は、図1
の如く、上金型10と下金型11とからなり、プランジ
ー13にて押さえ付け可能な押さえ部10a,11aを
有している。そして、上金型10の押さえ部10aは、
上金型本体10bの収納室10c内に上下方向に遊動自
在とされ、ばね14にて下方に付勢されている。
The mold used in this embodiment is shown in FIG.
As shown in the figure, the upper die 10 and the lower die 11 have pressing portions 10a and 11a which can be pressed by the plunge 13. And the holding part 10a of the upper metal mold 10 is
The upper mold body 10b is freely movable up and down in a storage chamber 10c, and is urged downward by a spring 14.

【0020】上記SMD光半導体装置は、次のように製
造される。
The SMD optical semiconductor device is manufactured as follows.

【0021】まず、絶縁基板1を、図5または図6に示
すように、複数のデバイス分が一体的に連なつた状態で
成形し、その上面に立体配線パターンPを形成する。こ
の際、図5の如く、絶縁基板1の外郭部に、樹脂漏れ防
止壁21を立体配線パターンPと同厚に形成しておく。
First, as shown in FIG. 5 or FIG. 6, the insulating substrate 1 is formed in a state where a plurality of devices are integrally connected, and a three-dimensional wiring pattern P is formed on the upper surface thereof. At this time, as shown in FIG. 5, a resin leakage preventing wall 21 is formed in the outer peripheral portion of the insulating substrate 1 to have the same thickness as the three-dimensional wiring pattern P.

【0022】次に、金型10,11を用いて、図8の如
く、複数のデバイス分について、ランナー部7からゲー
ト9を介して、樹脂を一度に注入して封止し、レンズ6
を有するパツケージ8を形成する。
Next, as shown in FIG. 8, resin is injected at once from the runner portion 7 through the gate 9 to seal the lens 6 by using the molds 10 and 11.
Is formed.

【0023】この際、図1の如く、ばね14にて、金型
10,11の押さえ部10a,11aを、立体配線パタ
ーンPおよび樹脂漏れ防止壁21に対して遊動自在に押
圧する。
At this time, as shown in FIG. 1, the pressing portions 10a and 11a of the dies 10 and 11 are movably pressed against the three-dimensional wiring pattern P and the resin leakage preventing wall 21 by the spring 14.

【0024】そうすると、基板1の厚み寸法のいかんに
よらず、押さえ部10a,11aと樹脂漏れ防止壁21
とを確実に密着させることができ、樹脂注入時の外部へ
の樹脂漏れを防止できる。
Then, regardless of the thickness of the substrate 1, the holding portions 10a, 11a and the resin leakage preventing
Can be surely brought into close contact with each other, and leakage of resin to the outside during resin injection can be prevented.

【0025】また、樹脂漏れ防止壁21を設けたことに
より、図9に示す隙間dからパツケージ8内の空気およ
び樹脂を逃がしても、樹脂漏れを防止できるため、成型
金型に通常設ける空気抜き用凹部(エアーベント)の加
工を施す必要がなく、成型金型の加工も容易となり、安
い設備投資ですむ。
Further, by providing the resin leakage preventing wall 21, even if air and resin in the package 8 escape from the gap d shown in FIG. 9, resin leakage can be prevented. There is no need to process recesses (air vents), processing of molding dies is easy, and low capital investment is required.

【0026】その後、ランナー部7およびゲート9を除
去すべく、ダイシングラインDでダイシングして、図2
〜3の如く、単独のSMD光半導体装置は完成する。
Thereafter, in order to remove the runner portion 7 and the gate 9, dicing is performed at a dicing line D, and FIG.
As shown in (1) to (3), a single SMD optical semiconductor device is completed.

【0027】なお、本発明は、上記実施例に限定される
ものではなく、本発明の範囲内で上記実施例に多くの修
正および変更を加え得ることは勿論である。
It should be noted that the present invention is not limited to the above-described embodiment, and it goes without saying that many modifications and changes can be made to the above-described embodiment within the scope of the present invention.

【0028】例えば、上記実施例では、上側の金型10
の押さえ部10aにばね14を設けていたが、下側の金
型11の押さえ部11aにばね14を設け、下側から押
圧してもよい。
For example, in the above embodiment, the upper mold 10
Although the spring 14 is provided on the holding portion 10a of the mold 11, the spring 14 may be provided on the holding portion 11a of the lower mold 11, and the pressing may be performed from below.

【0029】[0029]

【発明の効果】以上の説明から明らかな通り、本発明請
求項1によると、絶縁基板の外郭部に樹脂漏れ防止壁を
形成し、成形金型の押さえ部をばねにて樹脂漏れ防止壁
に押圧するので、押さえ部と樹脂漏れ防止壁との密着力
により、樹脂注入時の樹脂漏れを防止できる。
As is apparent from the above description, according to the first aspect of the present invention, the resin leakage preventing wall is formed on the outer peripheral portion of the insulating substrate, and the pressing portion of the molding die is formed on the resin leakage preventing wall by the spring. Since the pressing is performed, it is possible to prevent the resin from leaking at the time of injecting the resin due to the adhesion between the pressing portion and the resin leakage preventing wall.

【0030】したがつて、基板の厚み寸法のいかんによ
らず、押さえ部と樹脂漏れ防止壁とを確実に密着させる
ことができ、立体配線パターンを損傷して信頼性を損な
うことなく、樹脂注入時の外部への樹脂漏れを防止で
き、経費を節減できると同時に、形状を定形化でき、取
り扱いを容易にできる。
Therefore, regardless of the thickness of the substrate, the pressing portion and the resin leakage preventing wall can be securely brought into close contact with each other, and the resin injection can be performed without damaging the three-dimensional wiring pattern and impairing the reliability. In addition, it is possible to prevent the resin from leaking to the outside at the time, thereby reducing the cost, and at the same time, the shape can be fixed and the handling can be facilitated.

【0031】本発明請求項2によると、樹脂漏れ防止壁
を立体配線パターンと同一材料を用いて同時にパターン
形成するので、新たな部材を設けることによる作業工程
の増加を防止できるといつた優れた効果がある。
According to the second aspect of the present invention, since the resin leakage preventing wall is formed simultaneously with the three-dimensional wiring pattern by using the same material, it is possible to prevent an increase in the number of working steps due to the provision of new members. effective.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の一実施例に使用する成形金型の構造概
念図
FIG. 1 is a schematic structural view of a molding die used in one embodiment of the present invention.

【図2】光半導体素子の完成状態を示す平面図FIG. 2 is a plan view showing a completed state of the optical semiconductor element.

【図3】図2のA−A断面図FIG. 3 is a sectional view taken along line AA of FIG. 2;

【図4】図2のB−B断面図FIG. 4 is a sectional view taken along line BB of FIG. 2;

【図5】絶縁基板上の立体配線パターンおよび樹脂漏れ
防止壁を示す平面図
FIG. 5 is a plan view showing a three-dimensional wiring pattern and a resin leakage prevention wall on an insulating substrate.

【図6】絶縁基板の断面図FIG. 6 is a sectional view of an insulating substrate.

【図7】絶縁基板上の立体配線パターンを示す一部平面
FIG. 7 is a partial plan view showing a three-dimensional wiring pattern on an insulating substrate;

【図8】光半導体素子の樹脂封止状態を示す一部平面図FIG. 8 is a partial plan view showing a resin-sealed state of the optical semiconductor element.

【図9】図8のC−C断面図9 is a sectional view taken along the line CC in FIG.

【図10】図8のD−D断面図FIG. 10 is a sectional view taken along line DD of FIG. 8;

【図11】従来に使用する成形金型の構造概念図FIG. 11 is a structural conceptual view of a molding die used conventionally.

【符号の説明】[Explanation of symbols]

1 絶縁基板 2 光半導体素子 8 パツケージ 10,11 成形金型 10a,11a 押さえ部 14 ばね 21 樹脂漏れ防止壁 P 立体配線パターン REFERENCE SIGNS LIST 1 insulating substrate 2 optical semiconductor element 8 package 10, 11 molding die 10 a, 11 a holding part 14 spring 21 resin leakage prevention wall P three-dimensional wiring pattern

Claims (2)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】 絶縁基板に立体配線パターンを設け、該
立体配線パターン上に複数の光半導体素子を搭載し、絶
縁基板を成形金型の押さえ部で押さえながら複数の光半
導体素子を透光性樹脂にてモールドして複数のパツケー
ジを形成する光半導体装置の製造方法において、前記絶
縁基板の外郭部に、樹脂漏れ防止壁を立体配線パターン
と同厚に形成し、前記成形金型の少なくとも一方の押さ
え部を遊動自在とし、該押さえ部をばねにて立体配線パ
ターンおよび樹脂漏れ防止壁に押圧し、押さえ部と樹脂
漏れ防止壁との密着力により、樹脂注入時の樹脂漏れを
防止することを特徴とする光半導体装置の製造方法。
1. A three-dimensional wiring pattern is provided on an insulating substrate, a plurality of optical semiconductor elements are mounted on the three-dimensional wiring pattern, and the plurality of optical semiconductor elements are translucent while holding the insulating substrate with a pressing part of a molding die. In a method of manufacturing an optical semiconductor device, wherein a plurality of packages are formed by molding with a resin, a resin leakage prevention wall is formed on an outer portion of the insulating substrate to have the same thickness as a three-dimensional wiring pattern, and at least one of the molding dies is formed. The holding part is freely movable, and the holding part is pressed against the three-dimensional wiring pattern and the resin leakage prevention wall by a spring, and the resin is prevented from leaking at the time of injecting the resin by the adhesion between the holding part and the resin leakage prevention wall. A method for manufacturing an optical semiconductor device, comprising:
【請求項2】 請求項1記載の樹脂漏れ防止壁は、立体
配線パターンと同一材料を用いて同時にパターン形成す
ることを特徴とする光半導体装置の製造方法。
2. The method of manufacturing an optical semiconductor device according to claim 1, wherein the resin leakage prevention wall according to claim 1 is formed simultaneously with the three-dimensional wiring pattern using the same material.
JP4019010A 1992-02-04 1992-02-04 Method for manufacturing optical semiconductor device Expired - Fee Related JP2772447B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4019010A JP2772447B2 (en) 1992-02-04 1992-02-04 Method for manufacturing optical semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4019010A JP2772447B2 (en) 1992-02-04 1992-02-04 Method for manufacturing optical semiconductor device

Publications (2)

Publication Number Publication Date
JPH05218508A JPH05218508A (en) 1993-08-27
JP2772447B2 true JP2772447B2 (en) 1998-07-02

Family

ID=11987536

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4019010A Expired - Fee Related JP2772447B2 (en) 1992-02-04 1992-02-04 Method for manufacturing optical semiconductor device

Country Status (1)

Country Link
JP (1) JP2772447B2 (en)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
NL9500238A (en) * 1995-02-09 1996-09-02 Fico Bv Casing device with compensation element.
KR100789951B1 (en) * 2006-06-09 2008-01-03 엘지전자 주식회사 Apparatus and method for manufacturing Light Emitting Unit
JP2008205149A (en) * 2007-02-20 2008-09-04 Towa Corp Luminous member formation method and mold
DE102007017855A1 (en) 2007-04-16 2008-10-23 Osram Opto Semiconductors Gmbh Method for producing an optoelectronic component and optoelectronic component

Also Published As

Publication number Publication date
JPH05218508A (en) 1993-08-27

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