JPH05335442A - Resin molding method for semiconductor - Google Patents

Resin molding method for semiconductor

Info

Publication number
JPH05335442A
JPH05335442A JP4134643A JP13464392A JPH05335442A JP H05335442 A JPH05335442 A JP H05335442A JP 4134643 A JP4134643 A JP 4134643A JP 13464392 A JP13464392 A JP 13464392A JP H05335442 A JPH05335442 A JP H05335442A
Authority
JP
Japan
Prior art keywords
resin
space
lead frame
seal space
semiconductor element
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4134643A
Other languages
Japanese (ja)
Inventor
Yasuo Oka
靖夫 岡
Takashi Hara
孝 原
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sharp Corp
Original Assignee
Sharp Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Corp filed Critical Sharp Corp
Priority to JP4134643A priority Critical patent/JPH05335442A/en
Publication of JPH05335442A publication Critical patent/JPH05335442A/en
Pending legal-status Critical Current

Links

Landscapes

  • Lead Frames For Integrated Circuits (AREA)
  • Led Device Packages (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

PURPOSE:To restrain generation of burr to a minimum, and prevent generation of void, by forming a metal-plated layer in the manner in which the layer thickness in a resin seal space and a specified region exceeding the space is made larger than the layer in a tip region protruding from the specified region. CONSTITUTION:After a space containing a semiconductor element is formed by making a punch 1 abut against a lower die 2, resin is injected in a resin seal space 5 and cured. Metal-plated layers 10a, 10b are formed in the manner in which the layer thickness in the resin seal space 5 and a specified region exceeding the resin seal space 5 is made larger than the layer in a tip region protruding from the specified region. That is, a step-difference is formed in the parts of the metal plated layers 10a, 10b of the upper surface and the lower surface of an outside lead frame 7 exceeding the resin seal space 5 to be resin sealed. By the effect of the step-difference, a gap is formed between the punch 1 and the lower die 2, and gas generated from sealing resin is discharged from the gap to the outside.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は半導体装置の樹脂モール
ド方法に関し、更に詳しくは、透明樹脂や着色樹脂を用
いて発光ダイオード等の樹脂モールドを行うトランスフ
ァーモールド法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a resin molding method for semiconductor devices, and more particularly to a transfer molding method for molding a resin such as a light emitting diode using a transparent resin or a colored resin.

【0002】[0002]

【従来の技術】図4は従来例の模式的断面図、図5はそ
の模式的平面図である。リードフレーム17上の載置台
(図示せず)に発光ダイオード等の半導体素子(図示せ
ず)を載置し、その半導体素子とリード端子との配線が
施された状態で、樹脂モールドがなされる。まず、上パ
ッケージ13が形成されている上金型11および下パッ
ケージ14が形成されている下金型12を上記したリー
ドフレーム17を挟んで合体することにより、樹脂注入
ゲート16およびモールド樹脂が注入される樹脂封止空
間19を形成する。また、上パッケージ13にはエアー
ベント18が形成されており、このエアーベント18を
介して、樹脂封止空間19に注入された樹脂中のガスが
排出されるようになっている。
2. Description of the Related Art FIG. 4 is a schematic sectional view of a conventional example, and FIG. 5 is a schematic plan view thereof. A semiconductor element (not shown) such as a light emitting diode is placed on a mounting table (not shown) on the lead frame 17, and resin molding is performed in a state in which the semiconductor element and the lead terminal are wired. .. First, the resin injection gate 16 and the molding resin are injected by joining the upper mold 11 having the upper package 13 and the lower mold 12 having the lower package 14 with the lead frame 17 interposed therebetween. The resin sealed space 19 is formed. Further, an air vent 18 is formed in the upper package 13, and the gas in the resin injected into the resin sealing space 19 is exhausted through the air vent 18.

【0003】以上の構造の金型を用いて樹脂封止を行
う。すなわち、樹脂をランナー15を介して樹脂注入ゲ
ート16から、樹脂封止空間19に注入する。この時、
樹脂封止空間19すなわち、製品部に入った気泡は樹脂
加圧によりエアーベント18内を通って排出される。こ
のようにして、製品部に気泡が入ることを防止できる。
従来ではこのような方法により、製品内のボイドの発生
を防止し、品質の向上を図っていた。
Resin sealing is performed using the mold having the above structure. That is, the resin is injected into the resin sealing space 19 from the resin injection gate 16 via the runner 15. At this time,
The air bubbles that have entered the resin-sealed space 19, that is, the product portion, are discharged through the air vent 18 by the resin pressure. In this way, it is possible to prevent air bubbles from entering the product section.
Conventionally, such a method has been used to prevent the occurrence of voids in the product and improve the quality.

【0004】また図6に示すように、リードフレーム1
7の上面及び下面にそれぞれ金属メッキ層60を一様な
厚さに形成し、その金属メッキ層60上に半導体素子を
載置して、上記と同様に樹脂封止を行う方法も行われて
いる。
Further, as shown in FIG. 6, the lead frame 1
A method of forming a metal plating layer 60 on each of the upper surface and the lower surface of 7 with a uniform thickness, mounting a semiconductor element on the metal plating layer 60, and performing resin sealing in the same manner as above is also performed. There is.

【0005】[0005]

【発明が解決しようとする課題】ところで、従来の技術
はボイドの発生を防止する方法としては有効であるが、
樹脂バリの発生を招くという点では問題であった。つま
り、流れにくい樹脂を用いる場合は有効であるが、流れ
やすく、しかも小さい隙間にまで入り込む樹脂を用いる
場合は、樹脂バリが発生しやすいという問題もあった。
さらに、モールド金型が新しい時期には、樹脂バリを十
分防止できても、老朽化に伴い金型の磨耗や金型面圧の
ばらつきが生じるため、樹脂バリが発生し易くなるとい
う問題もある。
Although the conventional technique is effective as a method for preventing the occurrence of voids,
This is a problem in that it causes the generation of resin burr. In other words, it is effective when a resin that does not flow easily is used, but there is a problem that resin burr is likely to occur when a resin that flows easily and that enters even a small gap is used.
Further, even if the resin burrs can be sufficiently prevented when the molding dies are new, there is a problem that resin burrs are likely to occur due to wear of the dies and variations in the die surface pressure due to aging. ..

【0006】本発明はこれらの点に鑑みてなされたもの
であり、樹脂バリの発生を最小限に止め、また、ボイド
の発生を防止することができる半導体装置の樹脂モール
ド法を提供することを目的とする。
The present invention has been made in view of these points, and it is an object of the present invention to provide a resin molding method for a semiconductor device capable of minimizing the generation of resin burrs and preventing the generation of voids. To aim.

【0007】[0007]

【課題を解決するための手段】上記の目的を達成するた
めに、本発明の半導体装置の樹脂モールド方法では、リ
ードフレーム上に半導体素子を載置し、その半導体素子
とリード端子とを接続した状態で、その半導体素子を含
む空間を上金型及び下金型を突き合わせることにより形
成した後、その樹脂封止空間に樹脂を注入し、硬化する
ことにより樹脂封止する半導体装置の樹脂モールド方法
において、樹脂封止前に、上記リードフレーム上面及び
下面に形成すべき金属メッキ層を、上記樹脂封止空間及
びその樹脂封止空間を超える所定領域における厚さより
も、その所定領域から突出した先端領域における厚さを
薄く形成することによって特徴付けられる。
In order to achieve the above object, in the resin molding method for a semiconductor device of the present invention, a semiconductor element is placed on a lead frame and the semiconductor element and the lead terminal are connected. In this state, a space containing the semiconductor element is formed by abutting an upper die and a lower die, and then a resin is injected into the resin encapsulation space and the resin is encapsulated by curing the resin mold of a semiconductor device. In the method, before the resin sealing, the metal plating layer to be formed on the upper surface and the lower surface of the lead frame is projected from the predetermined region beyond the thickness of the resin sealing space and the predetermined region exceeding the resin sealing space. Characterized by making the thickness in the tip region thin.

【0008】[0008]

【作用】樹脂封止される樹脂封止空間を超える外側のリ
ードフレーム上面及び下面の金属メッキ層部分には段差
が形成され、この段差により、金型とリードフレーム間
に隙間が形成される。封止される樹脂から生じるガスは
この隙間から外部に排出される。
A step is formed in the metal plating layer portion on the upper surface and the lower surface of the lead frame outside the resin-sealed space to be resin-sealed, and the step forms a gap between the die and the lead frame. The gas generated from the resin to be sealed is discharged to the outside through this gap.

【0009】[0009]

【実施例】図1は本発明実施例を説明するための要部断
面図であり、図2は本発明実施例を説明するための平面
図である。また、図3は本発明実施例の方法を説明する
ための断面図で、リードフレームに金属メッキ層が形成
された状態を示す。
DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a sectional view of an essential part for explaining an embodiment of the present invention, and FIG. 2 is a plan view for explaining an embodiment of the present invention. 3 is a sectional view for explaining the method of the embodiment of the present invention, showing a state in which a metal plating layer is formed on the lead frame.

【0010】これらの図面に基づいて、以下に本発明実
施例を説明する。まず、図3に示すように、リードフレ
ーム7の上面及び下面に金属メッキを施す。この金属メ
ッキは、半導体素子がモールドされる部分を含む樹脂封
止空間5内部及びその外側部分のリードフレーム7の上
面及び下面に厚く施し、またその外側部分のリードフレ
ーム7の上面及び下面に薄く施すことにより、それぞれ
厚メッキ層M1と、薄メッキ層M2とが形成される。従
って、この厚メッキ層M1と、薄メッキ層M2との境界
は段差が生じた構造が形成される。
Embodiments of the present invention will be described below with reference to these drawings. First, as shown in FIG. 3, metal plating is applied to the upper surface and the lower surface of the lead frame 7. This metal plating is applied thickly on the top and bottom surfaces of the lead frame 7 inside and outside the resin-sealed space 5 including the portion where the semiconductor element is molded, and on the top and bottom surfaces of the lead frame 7 outside thereof. By applying, the thick plating layer M1 and the thin plating layer M2 are formed, respectively. Therefore, the boundary between the thick plated layer M1 and the thin plated layer M2 has a stepped structure.

【0011】次に、この厚メッキ層M1上にLED等の
半導体素子を載置し(図示せず)、その半導体素子とリ
ード端子(図示せず)との内部結線を施す。その後、以
下に説明するように、この状態の半導体素子の樹脂封止
を行う。
Next, a semiconductor element such as an LED is mounted on the thick plated layer M1 (not shown), and the semiconductor element and a lead terminal (not shown) are internally connected. Thereafter, as described below, the semiconductor element in this state is sealed with resin.

【0012】まず、図1に示すように、樹脂封止空間5
を形成する上パッケージ3及び下パッケージ4がそれぞ
れ形成された上金型1及び下金型2を、金属メッキ層1
0a,10bが形成されたリードフレーム7を挟み込ん
だ状態で突き合わせる。このように両金型1,2を突き
合わせることにより、薄メッキ層M2と上金型1との
間、薄メッキ層M2と下金型2との間にはそれぞれ隙間
10a,10bを形成する。この状態で樹脂封止空間5
内に、樹脂をランナー15を介して樹脂注入ゲート16
から樹脂を注入し、樹脂封止する。この樹脂封止の際、
樹脂封止空間5内の樹脂は外部のリードフレーム7間の
間隙に滲み出し、フレーム厚樹脂バリ21が発生する。
一方、この樹脂内のガスは、高い樹脂耐圧によりフレー
ム厚樹脂バリ21を介し、さらに隙間10a,10bを
通って徐々に排出される。
First, as shown in FIG. 1, a resin sealing space 5 is formed.
Forming an upper package 3 and a lower package 4, respectively, and forming a metal plating layer 1 on the upper mold 1 and the lower mold 2.
The lead frames 7 on which 0a and 10b are formed are abutted with each other in a sandwiched state. By abutting the two molds 1 and 2 in this manner, gaps 10a and 10b are formed between the thin plating layer M2 and the upper mold 1 and between the thin plating layer M2 and the lower mold 2, respectively. .. In this state, the resin sealing space 5
The resin is injected through the runner 15 into the resin injection gate 16
The resin is injected from above and the resin is sealed. At the time of this resin sealing,
The resin in the resin sealing space 5 oozes into the gap between the external lead frames 7, and a frame thickness resin burr 21 is generated.
On the other hand, the gas in the resin is gradually discharged through the frame thickness resin burr 21 due to the high resin pressure resistance and further through the gaps 10a and 10b.

【0013】このように、本発明実施例では樹脂バリが
発生するものの、リードフレーム上には発生しないの
で、後工程で行われるバリ除去は容易であり、その際、
製品に傷をつけたりするなどの品質低下を招くこともな
い。
As described above, although resin burrs are generated in the embodiment of the present invention, they are not generated on the lead frame. Therefore, it is easy to remove burrs in a later step.
It does not cause quality deterioration such as scratching the product.

【0014】また、この実施例で適用される樹脂は透明
樹脂等の流れ性の良い樹脂を用いた樹脂封止に有効であ
るため、特に発光ダイオード、受光素子に応用できる。
Further, the resin applied in this embodiment is effective for resin encapsulation using a resin having a good flowability such as a transparent resin, so that it can be applied particularly to a light emitting diode and a light receiving element.

【0015】[0015]

【発明の効果】以上説明したように、本発明の樹脂モー
ルド方法によれば、樹脂封止される樹脂封止空間の外部
側の金属メッキ層には段差が形成され、この段差によ
り、金型とリードフレーム間に隙間を形成し、この隙間
を介して樹脂から生じるガスを外部に排出するようにし
たので、樹脂封止の際樹脂がリードフレーム上に滲み出
すことがなく、樹脂バリが大幅に低減できる。従って、
その樹脂バリの除去等の作業が軽減されく、工程を簡略
化することができる。また、樹脂バリが原因の搬送系の
トラブルも回避できる。さらに、金型の製作の際、エア
ベントを設けるための加工工程の必要がないため、その
加工費は削減され、さらに、差厚メッキをリードフレー
ムに施すことにより、リードフレームのコストの低減も
でき、全体として製造コストを低減できる。
As described above, according to the resin molding method of the present invention, a step is formed in the metal plating layer on the outer side of the resin-sealed space to be resin-sealed. Since a gap is formed between the lead frame and the lead frame and the gas generated from the resin is discharged to the outside through this gap, the resin does not seep out onto the lead frame during resin encapsulation and the resin burr is greatly removed. Can be reduced to Therefore,
The work such as the removal of the resin burr is not reduced, and the process can be simplified. Further, it is possible to avoid troubles in the transfer system due to resin burr. In addition, when manufacturing the mold, there is no need for a processing step to provide an air vent, so the processing cost is reduced, and by applying differential thickness plating to the lead frame, the cost of the lead frame can also be reduced. The manufacturing cost can be reduced as a whole.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明実施例を説明するための要部断面図FIG. 1 is a sectional view of an essential part for explaining an embodiment of the present invention.

【図2】本発明実施例を説明するための要部平面図FIG. 2 is a plan view of a main part for explaining an embodiment of the present invention.

【図3】本発明実施例に用いるリードフレームに金属メ
ッキ層が形成された状態を示す断面図
FIG. 3 is a cross-sectional view showing a state where a metal plating layer is formed on the lead frame used in the example of the present invention.

【図4】従来例を説明するための要部断面図FIG. 4 is a sectional view of a main part for explaining a conventional example.

【図5】従来例を説明するための要部平面図FIG. 5 is a plan view of a main part for explaining a conventional example.

【図6】他の従来例を説明するための要部断面図FIG. 6 is a sectional view of an essential part for explaining another conventional example.

【符号の説明】[Explanation of symbols]

1・・・・上金型 2・・・・下金型 3・・・・上パッケージ 4・・・・下パッケージ 5・・・・樹脂封止空間 7,9・・・・リードフレーム 10a,10b・・・・金属メッキ層 1 ... ・ Upper mold 2 ・ ・ ・ ・ Lower mold 3 ・ ・ ・ ・ Upper package 4 ・ ・ ・ ・ Lower package 5 ・ ・ ・ ・ Resin-sealed space 7, 9 10b ... Metal plating layer

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】リードフレーム上に半導体素子を載置し、
その半導体素子とリード端子とを接続した状態で、その
半導体素子を含む空間を上金型及び下金型を突き合わせ
ることにより形成した後、その樹脂封止空間に樹脂を注
入し、硬化することにより樹脂封止する半導体装置の樹
脂モールド方法において、樹脂封止前に、上記リードフ
レーム上面及び下面に形成すべき金属メッキ層を、上記
樹脂封止空間及びその樹脂封止空間を超える所定領域に
おける厚さよりも、その所定領域から突出した先端領域
における厚さを薄く形成することを特徴とする半導体装
置の樹脂モールド方法。
1. A semiconductor element is mounted on a lead frame,
After the semiconductor element and the lead terminal are connected, a space containing the semiconductor element is formed by abutting the upper die and the lower die, and then a resin is injected into the resin-sealed space and cured. In a resin molding method for a semiconductor device which is resin-sealed by means of the above, before the resin-sealing, a metal plating layer to be formed on the upper and lower surfaces of the lead frame is formed in the resin-sealing space and a predetermined region exceeding the resin-sealing space. A resin molding method for a semiconductor device, characterized in that a thickness in a tip region protruding from a predetermined region is formed thinner than a thickness.
JP4134643A 1992-05-27 1992-05-27 Resin molding method for semiconductor Pending JPH05335442A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4134643A JPH05335442A (en) 1992-05-27 1992-05-27 Resin molding method for semiconductor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4134643A JPH05335442A (en) 1992-05-27 1992-05-27 Resin molding method for semiconductor

Publications (1)

Publication Number Publication Date
JPH05335442A true JPH05335442A (en) 1993-12-17

Family

ID=15133164

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4134643A Pending JPH05335442A (en) 1992-05-27 1992-05-27 Resin molding method for semiconductor

Country Status (1)

Country Link
JP (1) JPH05335442A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6943433B2 (en) 2002-03-06 2005-09-13 Nichia Corporation Semiconductor device and manufacturing method for same
CN111031674A (en) * 2019-11-21 2020-04-17 惠州美锐电子科技有限公司 Method for removing selective plating edge at specific position on PCB
JP2020088228A (en) * 2018-11-28 2020-06-04 日亜化学工業株式会社 Multi-row type lead frame, multi-row type led lead frame, and manufacturing method of them, and manufacturing method of led package

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55118661A (en) * 1979-03-05 1980-09-11 Nec Corp Lead frame for semiconductor device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55118661A (en) * 1979-03-05 1980-09-11 Nec Corp Lead frame for semiconductor device

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6943433B2 (en) 2002-03-06 2005-09-13 Nichia Corporation Semiconductor device and manufacturing method for same
JP2020088228A (en) * 2018-11-28 2020-06-04 日亜化学工業株式会社 Multi-row type lead frame, multi-row type led lead frame, and manufacturing method of them, and manufacturing method of led package
CN111031674A (en) * 2019-11-21 2020-04-17 惠州美锐电子科技有限公司 Method for removing selective plating edge at specific position on PCB
CN111031674B (en) * 2019-11-21 2023-04-21 惠州美锐电子科技有限公司 Method for removing selective electroplating edge at specific position on PCB

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