JPH0574999A - Semiconductor device and its manufacture - Google Patents
Semiconductor device and its manufactureInfo
- Publication number
- JPH0574999A JPH0574999A JP3233175A JP23317591A JPH0574999A JP H0574999 A JPH0574999 A JP H0574999A JP 3233175 A JP3233175 A JP 3233175A JP 23317591 A JP23317591 A JP 23317591A JP H0574999 A JPH0574999 A JP H0574999A
- Authority
- JP
- Japan
- Prior art keywords
- resin
- lead
- lead frame
- semiconductor device
- semiconductor chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は半導体装置及びその製造
方法に関する。詳しくは、プラスチックによる封止工程
において生ずるパーティングフラッシュを防止した半導
体装置及びその製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and its manufacturing method. More specifically, the present invention relates to a semiconductor device in which parting flash that occurs in a plastic sealing process is prevented and a method for manufacturing the same.
【０００２】[0002]
【従来の技術】半導体装置の製造に用いるリードフレー
ムの１例を図５に示す。これは枠状のタイバー１と、該
タイバーに４本のピンチバー２を介して支持されたダイ
ステージ部３と、該ダイバー１にそれぞれ一端を接続し
た複数のリード４と、該リード間を接続するダムバー５
とからなり、薄い金属板からプレス加工又はエッチング
加工により形成されたものである。2. Description of the Related Art One example of a lead frame used for manufacturing a semiconductor device is shown in FIG. This connects a frame-shaped tie bar 1, a die stage section 3 supported by the tie bar via four pinch bars 2, a plurality of leads 4 each having one end connected to the diver 1, and the leads. Dam bar 5
And is formed by pressing or etching a thin metal plate.
【０００３】このリードフレームを用いた従来の半導体
装置の製造方法を図６により説明する。先ず（ａ）図の
如くリードフレーム６のダイステージ部３に半導体チッ
プ７を接着剤又は半田等でダイボンディングする。次に
（ｂ）図の如く半導体チップ７の電極とリードフレーム
のインナーリード４ａ間をワイヤ８でワイヤボンディン
グする。次いで（ｃ）図の如く樹脂モールド金型の上型
９と下型９′との間にリードフレーム６を挟み、キャビ
ティの中に樹脂１０を注入して半導体チップ７、ダイス
テージ部３、インナーリード４ａを樹脂封止した後、リ
ードフレーム６に半田めっきを施し、最後に（ｄ）図の
如くリードフレーム６のダイバー及びダムバーを切断除
去した後アウターリード４ｂを所定の形状に折曲成形し
て完成する。A conventional method of manufacturing a semiconductor device using this lead frame will be described with reference to FIG. First, as shown in FIG. 3A, the semiconductor chip 7 is die-bonded to the die stage portion 3 of the lead frame 6 with an adhesive or solder. Next, as shown in FIG. 3B, the electrode of the semiconductor chip 7 and the inner lead 4a of the lead frame are wire-bonded with the wire 8. Next, as shown in (c), the lead frame 6 is sandwiched between the upper mold 9 and the lower mold 9'of the resin mold, and the resin 10 is injected into the cavity to form the semiconductor chip 7, the die stage portion 3, the inner After the leads 4a are resin-sealed, the lead frame 6 is solder-plated, and finally the diver and the dam bar of the lead frame 6 are cut and removed as shown in (d), and then the outer leads 4b are bent and formed into a predetermined shape. Complete.
【０００４】なお図７は前記樹脂モールド用の金型を示
す図で、図８はその一部拡大図である。両図において、
９は上型、９′は下型、１１は上型に設けられたポッ
ト、１２はスプルー、１３は下型に設けられたキャビテ
ィブロック、１４はキャビティ、１６はランナ、１７は
ゲートである。FIG. 7 is a view showing the resin mold and FIG. 8 is a partially enlarged view thereof. In both figures,
Reference numeral 9 is an upper mold, 9'is a lower mold, 11 is a pot provided in the upper mold, 12 is a sprue, 13 is a cavity block provided in the lower mold, 14 is a cavity, 16 is a runner, and 17 is a gate.
【０００５】[0005]
【発明が解決しようとする課題】上記従来の半導体装置
の製造方法では、その樹脂封止工程において、図９
（ａ）及び（ｂ）に示すようにリードフレーム６を上下
の樹脂モールド金型９，９′の間に挟み込んで樹脂１０
を注入した場合、どうしてもリードフレーム６と金型
９，９′の間から厚さ２〜５μｍ程度の薄いバリ（パー
ティングフラッシュ）１１が発生する。このバリは後工
程のめっき付着の妨害となるためめっき前に除去してお
く必要があり、特殊なバリ除去工程を設けなくてはなら
ない。またこの工程でも除去できない様なバリが生じた
場合にはめっきが施せないため不良品となる。In the conventional method of manufacturing a semiconductor device described above, in the resin encapsulation step, as shown in FIG.
As shown in (a) and (b), the lead frame 6 is sandwiched between the upper and lower resin mold dies 9, 9 ', and the resin 10
In the case of injecting, a thin burr (parting flash) 11 having a thickness of about 2 to 5 μm is inevitably generated between the lead frame 6 and the molds 9 and 9 ′. Since this burr interferes with the adhesion of the plating in the subsequent process, it must be removed before plating, and a special burr removal process must be provided. In addition, if burr that cannot be removed occurs even in this step, plating cannot be performed and the product becomes a defective product.
【０００６】本発明は、樹脂封止工程においてバリの発
生がない様にした半導体装置及びその製造方法を実現し
ようとする。The present invention is intended to realize a semiconductor device and a method of manufacturing the same in which no burr is generated in the resin sealing step.
【０００７】[0007]
【課題を解決するための手段】本発明の半導体装置に於
いては、図１に示したように半導体チップ７が搭載され
たリードフレーム６の該半導体チップ７及びダイステー
ジ部３及びインナーリード４ａが樹脂１０により封止さ
れアウターリード（４ｂ）が該樹脂（１０）で封止され
た領域より外側に延出されて成る半導体装置において、
上記リードフレーム６のインナーリード４ａとアウター
リード４ｂとの境に板厚の薄い部分１８を設け、該薄い
部分の一方の段差部１８ａが封止樹脂１０より僅かに外
部に出ていることを特徴とする。In the semiconductor device of the present invention, as shown in FIG. 1, the semiconductor chip 7 of the lead frame 6 on which the semiconductor chip 7 is mounted, the die stage portion 3, and the inner leads 4a are provided. In a semiconductor device in which the outer lead (4b) is sealed by a resin 10 and extends outside the region sealed by the resin (10),
A thin plate portion 18 is provided at a boundary between the inner lead 4a and the outer lead 4b of the lead frame 6, and one step portion 18a of the thin portion is slightly outside the sealing resin 10. And
【０００８】また、本発明の半導体装置の製造方法に於
いては、リードフレーム６のダイステージ部３に半導体
チップ７を搭載し、次いで該半導体チップ７の電極とリ
ードフレーム６のインナーリード４ａ間をワイヤ８でワ
イヤボンディングし、その後、前記半導体チップ７とリ
ードフレーム６のダイステージ部３及びインナーリード
４ａを樹脂１０にてモールドして封止する諸工程よりな
る半導体装置の製造方法において、上記樹脂封止工程
は、アウターリード４ｂの樹脂モールド金型９，９′に
接触する面で且つキャビティ１４に近接した位置に、も
しくは樹脂モールド金型９，９′の合わせ面のキャビテ
ィ１４に近接した部分にゴム系物質１９を塗布しておく
ことを特徴とする。この構成を採ることにより、樹脂封
止工程においてバリの発生がない様にした半導体装置及
びその製造方法が得られる。Further, in the method of manufacturing a semiconductor device of the present invention, the semiconductor chip 7 is mounted on the die stage portion 3 of the lead frame 6, and then between the electrode of the semiconductor chip 7 and the inner lead 4a of the lead frame 6. Wire bonding with a wire 8, and thereafter, the semiconductor chip 7 and the die stage portion 3 of the lead frame 6 and the inner lead 4a are molded with resin 10 and sealed. In the resin sealing step, the surface of the outer lead 4b that contacts the resin molds 9 and 9'and close to the cavity 14, or the cavity 14 on the mating surface of the resin molds 9 and 9 '. It is characterized in that the rubber substance 19 is applied to the portion. By adopting this configuration, it is possible to obtain a semiconductor device and its manufacturing method in which burr is not generated in the resin sealing step.
【０００９】[0009]
【作用】本発明の半導体装置では、リードフレーム６の
金型で挟み込まれる位置に板厚の薄い部分１８を作り、
段差部１８ａを形成しておくことにより、該段差部１８
ａで樹脂モールド時に発生するバリの進行を止めること
ができる。In the semiconductor device of the present invention, the thin plate portion 18 is formed at the position where the lead frame 6 is sandwiched by the molds.
By forming the step portion 18a, the step portion 18a
With a, it is possible to stop the progress of burrs generated during resin molding.
【００１０】また本発明の半導体装置の製造方法では、
リードフレーム６を金型で挟み込む部分の、リードフレ
ーム側又は金型側にゴム系物質１９を塗布しておくこと
により、該部でバリの発生を抑えることができる。According to the method of manufacturing a semiconductor device of the present invention,
By applying the rubber substance 19 to the lead frame side or the die side of the portion where the lead frame 6 is sandwiched by the die, it is possible to suppress the occurrence of burrs at the portion.
【００１１】[0011]
【実施例】図１は本発明の半導体装置の実施例を示す図
であり、（ａ）は断面図、（ｂ）は（ａ）図のＢ部拡大
図である。本実施例は、リードフレーム６のダイステー
ジ部３に半導体チップ７が搭載され、該半導体チップ７
の電極とインナーリード４ａ間がワイヤ８でワイヤボン
ディングされ、該半導体チップ７とダイステージ部３及
びインナーリード４ａが樹脂１０でモールド封止されて
いることは図６で説明した従来例と同様であり、本実施
例の要点は、図１（ｂ）の拡大断面図に示すように、イ
ンナーリード４ａとアウターリード４ｂとの境に板厚の
薄い部分１８を設け、その一方の段差部１８ａが封止樹
脂１０より外側に僅かに（０．５mm程度）出るようにし
たことである。なお段差部１８ａの段差は０．１５〜
０．２５mm程度が好ましい。1A and 1B are views showing an embodiment of a semiconductor device of the present invention. FIG. 1A is a sectional view, and FIG. 1B is an enlarged view of a portion B in FIG. In this embodiment, the semiconductor chip 7 is mounted on the die stage portion 3 of the lead frame 6, and the semiconductor chip 7 is
The electrode 8 and the inner lead 4a are wire-bonded with the wire 8, and the semiconductor chip 7, the die stage portion 3 and the inner lead 4a are molded and sealed with the resin 10 as in the conventional example described in FIG. Therefore, the main point of this embodiment is, as shown in the enlarged cross-sectional view of FIG. 1B, that a thin plate portion 18 is provided at the boundary between the inner lead 4a and the outer lead 4b, and one of the step portions 18a is That is, it is slightly (about 0.5 mm) outside the sealing resin 10. The step 18a has a step of 0.15
It is preferably about 0.25 mm.
【００１２】このように構成された本実施例は、その樹
脂１０による封止工程において、図２に示すように、ア
ウターリード４ｂとモールド金型との間からバリ１１が
発生するが、該バリ１１は、板厚の薄い部分１８と厚い
部分との間に形成されている段差１８ａによって進行を
止められるため、それ以上の大きさにはならない。In this embodiment having the above-mentioned structure, in the sealing step with the resin 10, as shown in FIG. 2, a burr 11 is generated between the outer lead 4b and the molding die. Since the step 11a is formed by the step 18a formed between the thin plate portion 18 and the thick plate portion 11, the size of the plate 11 does not become larger than that.
【００１３】図３は本発明の半導体装置の製造方法の第
１の実施例を説明するための図である。本実施例は、リ
ードフレーム６に半導体チップ７を搭載し、該半導体チ
ップ７の電極とインナーリード４ａ間をワイヤ８でワイ
ヤボンディングするまでの工程は図６で説明した従来例
と同様であり、次の樹脂によるモールド工程が異なる。FIG. 3 is a diagram for explaining the first embodiment of the method for manufacturing a semiconductor device of the present invention. In this embodiment, the steps up to mounting the semiconductor chip 7 on the lead frame 6 and wire-bonding the electrode of the semiconductor chip 7 and the inner lead 4a with the wire 8 are the same as those of the conventional example described in FIG. The following resin molding process is different.
【００１４】本実施例の樹脂封止工程は、先ず図３
（ａ）に示すように、チップ搭載及びワイヤボンディン
グしたリードフレーム６のアウターリード４ｂの一部に
シリコンゴム等のゴム系物質１９を塗布する。その位置
は、モールド金型のキャビティの縁部に接触する部分と
する。次いでこのようにゴム系物質を塗布したリードフ
レーム６を同図（ｂ）の如くモールド金型９，９′で挟
みキャビティ１４内に樹脂を注入するのである。この
後、めっき、タイバー、ダムバーの切断除去、アウター
リードの折曲整形を行なうことは従来例と同様である。The resin encapsulation process of this embodiment will be described with reference to FIG.
As shown in (a), a rubber-based substance 19 such as silicon rubber is applied to a part of the outer lead 4b of the lead frame 6 on which the chip is mounted and wire-bonded. The position is a portion that contacts the edge of the cavity of the molding die. Next, the lead frame 6 thus coated with the rubber-based substance is sandwiched between the molding dies 9 and 9'as shown in FIG. 2B, and the resin is injected into the cavity 14. Thereafter, plating, cutting and removal of tie bars and dam bars, and bending of outer leads are performed in the same manner as in the conventional example.
【００１５】本実施例によれば、リードフレーム６に塗
布したゴム系物質１９が、リードフレーム６と金型９，
９′との間にできる微小なすきまを塞ぐため、バリの発
生を防止することができる。According to the present embodiment, the rubber-based substance 19 applied to the lead frame 6 causes the lead frame 6 and the mold 9,
Since a minute gap formed with the 9'is closed, burr can be prevented from occurring.
【００１６】図４は本発明の半導体装置の製造方法の第
２の実施例を説明するための図である。本実施例は、基
本的には前実施例と同様であり、異なるところは、前実
施例ではゴム系物質１９をリードフレーム６に塗布した
のを、本実施例では図４（ａ）に示すようにゴム系物質
１９をモールド型９，９′のリードフレーム６に接する
キャビティ１４の縁部に塗布したことである。FIG. 4 is a diagram for explaining a second embodiment of the method of manufacturing a semiconductor device of the present invention. This example is basically the same as the previous example, except that the rubber-based substance 19 is applied to the lead frame 6 in the previous example, which is shown in FIG. That is, the rubber-based substance 19 is applied to the edge portion of the cavity 14 which is in contact with the lead frame 6 of the molding dies 9 and 9 '.
【００１７】本実施例によれば図４（ｂ）の如くリード
フレーム６を金型９，９′で挟み込み、樹脂１０を注入
したときゴム系物質１９が前実施例と同様な作用をなし
バリの発生を防止することができる。According to this embodiment, as shown in FIG. 4 (b), when the lead frame 6 is sandwiched by the molds 9 and 9'and the resin 10 is injected, the rubber material 19 has the same function as in the previous embodiment, and the burr is not formed. Can be prevented.
【００１８】[0018]
【発明の効果】本発明に依れば、樹脂モールド工程にお
いて、予めリードフレームの金型に接触する部分の一部
に板厚の薄い部分を設けておくか、又はゴム系物質を塗
布しておくことによりバリの発生を抑えることができ、
バリ取り工程の省略、及び歩留りの向上に寄与すること
ができる。According to the present invention, in the resin molding process, a thin plate portion is provided in advance in a portion of the lead frame which comes into contact with the mold, or a rubber substance is applied. By setting it, you can suppress the occurrence of burr,
This can contribute to the omission of the deburring step and the improvement of the yield.
【図１】本発明の半導体装置の実施例を示す図である。FIG. 1 is a diagram showing an embodiment of a semiconductor device of the present invention.
【図２】本発明の半導体装置の実施例の効果を説明する
ための図である。FIG. 2 is a diagram for explaining the effect of the embodiment of the semiconductor device of the present invention.
【図３】本発明の半導体装置の製造方法の第１の実施例
を説明するための図である。FIG. 3 is a drawing for explaining the first embodiment of the method for manufacturing a semiconductor device of the present invention.
【図４】本発明の半導体装置の製造方法の第２の実施例
を説明するための図である。FIG. 4 is a drawing for explaining the second embodiment of the method for manufacturing a semiconductor device of the present invention.
【図５】従来のリードフレームの１例を示す図である。FIG. 5 is a diagram showing an example of a conventional lead frame.
【図６】従来の半導体装置の製造方法を説明するための
図である。FIG. 6 is a diagram for explaining a conventional method for manufacturing a semiconductor device.
【図７】従来の樹脂モールド金型を示す図である。FIG. 7 is a diagram showing a conventional resin mold die.
【図８】図７の一部拡大図である。FIG. 8 is a partially enlarged view of FIG. 7.
【図９】発明が解決しようとする課題を説明するための
図である。FIG. 9 is a diagram for explaining a problem to be solved by the invention.
３…ダイステージ部 ４ａ…インナーリード ４ｂ…アウターリード ６…リードフレーム ７半導体チップ ８…ワイヤ ９，９′…金型 １０…樹脂 １１…バリ １４…キャビティ １８板厚の薄い部分 １８ａ…段差 １９…ゴム系物質 3 ... Die stage part 4a ... Inner lead 4b ... Outer lead 6 ... Lead frame 7 Semiconductor chip 8 ... Wire 9,9 '... Mold 10 ... Resin 11 ... Burr 14 ... Cavity 18 Thin portion 18a ... Step 19 ... Rubber material
───────────────────────────────────────────────────── フロントページの続き (72)発明者 小林 均 宮城県柴田郡村田町大字村田字西ケ丘１番 地の１ 株式会社富士通宮城エレクトロニ クス内 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Hitoshi Kobayashi 1st in Nishigaoka, Murata-cho, Shibata-gun, Miyagi Prefecture
Claims (2)
フレーム（６）の該半導体チップ（７）及びダイステー
ジ部（３）及びインナーリード（４ａ）が樹脂（１０）
により封止されアウターリード（４ｂ）が該樹脂（１
０）で封止された領域より外側に延出されて成る半導体
装置において、 上記リードフレーム（６）のインナーリード（４ａ）と
アウターリード（４ｂ）との境に板厚の薄い部分（１
８）を設け、該薄い部分の一方の段差部（１８ａ）が封
止樹脂（１０）より僅かに外部に出ていることを特徴と
する半導体装置。1. A lead frame (6) having a semiconductor chip (7) mounted thereon, wherein the semiconductor chip (7), the die stage portion (3) and the inner lead (4a) are made of resin (10).
The outer lead (4b) is sealed by the resin (1
In a semiconductor device formed by extending outside the region sealed by (0), the thin portion (1) at the boundary between the inner lead (4a) and the outer lead (4b) of the lead frame (6).
8) is provided, and one step portion (18a) of the thin portion is slightly exposed from the sealing resin (10) to the outside.
（３）に半導体チップ（７）を搭載し、次いで該半導体
チップ（７）の電極とリードフレーム（６）のインナー
リード（４ａ）間をワイヤ（８）でワイヤボンディング
し、その後、前記半導体チップ（７）とリードフレーム
（６）のダイステージ部（３）及びインナーリード（４
ａ）を樹脂（１０）にてモールドして封止する諸工程よ
りなる半導体装置の製造方法において、 上記樹脂封止工程は、アウターリード（４ｂ）の樹脂モ
ールド金型（９，９′）に接触する面で且つキャビティ
（１４）に近接した位置に、もしくは樹脂モールド金型
（９，９′）の合わせ面のキャビティ（１４）に近接し
た部分にゴム系物質（１９）を塗布しておくことを特徴
とする半導体装置の製造方法。2. A semiconductor chip (7) is mounted on the die stage part (3) of the lead frame (6), and then the electrode of the semiconductor chip (7) and the inner lead (4a) of the lead frame (6) are connected. Wire bonding is performed with a wire (8), and then the semiconductor chip (7), the die stage part (3) of the lead frame (6) and the inner lead (4).
In the method of manufacturing a semiconductor device, which comprises the steps of molding a) with a resin (10) and sealing the resin molding step (a), the resin molding die (9, 9 ') of the outer lead (4b) is used. The rubber substance (19) is applied to the contact surface and the position close to the cavity (14) or to the part of the mating surface of the resin mold (9, 9 ') close to the cavity (14). A method of manufacturing a semiconductor device, comprising:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3233175A JPH0574999A (en) | 1991-09-12 | 1991-09-12 | Semiconductor device and its manufacture |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3233175A JPH0574999A (en) | 1991-09-12 | 1991-09-12 | Semiconductor device and its manufacture |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0574999A true JPH0574999A (en) | 1993-03-26 |
Family
ID=16950908
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3233175A Pending JPH0574999A (en) | 1991-09-12 | 1991-09-12 | Semiconductor device and its manufacture |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0574999A (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6069406A (en) * | 1997-05-20 | 2000-05-30 | Shinko Electric Industries Co., Ltd. | Wiring patterned film and production thereof |
| US7321208B2 (en) | 2005-06-20 | 2008-01-22 | Toyoda Gosei Co., Ltd. | Driving apparatus |
| JP2010002427A (en) * | 2006-08-09 | 2010-01-07 | Epson Toyocom Corp | Inertial sensor, inertial sensor device and its manufacturing method |
| WO2017133941A1 (en) * | 2016-02-05 | 2017-08-10 | Robert Bosch Gmbh | Molded module, method for producing a molded module, and molding tool for the overmolding of a molded module |
| US10262948B2 (en) | 2016-02-16 | 2019-04-16 | Fuji Electric Co., Ltd. | Semiconductor module having outflow prevention external terminals |
| WO2024002466A1 (en) * | 2022-06-28 | 2024-01-04 | Hitachi Energy Ltd | Housing unit and method for manufacturing a housing unit for a semiconductor power module and semiconductor power module |
-
1991
- 1991-09-12 JP JP3233175A patent/JPH0574999A/en active Pending
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6069406A (en) * | 1997-05-20 | 2000-05-30 | Shinko Electric Industries Co., Ltd. | Wiring patterned film and production thereof |
| US6248615B1 (en) | 1997-05-20 | 2001-06-19 | Shinko Electric Industries Co., Ltd. | Wiring patterned film and production thereof |
| US7321208B2 (en) | 2005-06-20 | 2008-01-22 | Toyoda Gosei Co., Ltd. | Driving apparatus |
| JP2010002427A (en) * | 2006-08-09 | 2010-01-07 | Epson Toyocom Corp | Inertial sensor, inertial sensor device and its manufacturing method |
| WO2017133941A1 (en) * | 2016-02-05 | 2017-08-10 | Robert Bosch Gmbh | Molded module, method for producing a molded module, and molding tool for the overmolding of a molded module |
| US10262948B2 (en) | 2016-02-16 | 2019-04-16 | Fuji Electric Co., Ltd. | Semiconductor module having outflow prevention external terminals |
| WO2024002466A1 (en) * | 2022-06-28 | 2024-01-04 | Hitachi Energy Ltd | Housing unit and method for manufacturing a housing unit for a semiconductor power module and semiconductor power module |
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