JPH05129352A - Semiconductor device and manufacturing method thereof - Google Patents
Semiconductor device and manufacturing method thereofInfo
- Publication number
- JPH05129352A JPH05129352A JP3291075A JP29107591A JPH05129352A JP H05129352 A JPH05129352 A JP H05129352A JP 3291075 A JP3291075 A JP 3291075A JP 29107591 A JP29107591 A JP 29107591A JP H05129352 A JPH05129352 A JP H05129352A
- Authority
- JP
- Japan
- Prior art keywords
- resin
- semiconductor chip
- die
- packing
- stage
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
Landscapes
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は半導体装置およびその製
造方法に係り，特に樹脂封止半導体装置および樹脂封止
方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly to a resin-sealed semiconductor device and a resin-sealed method.
【０００２】近年，半導体装置は，パッケージの小型
化，チップの高集積化の要求に伴い，パッケージに対す
るチップの専有面積が大きくなり，半導体装置の実装時
に吸水管理や開梱後の放置時間管理や，また実装方法の
指定等の制限が設けられているため，高い強度のモール
ドコンパウンドが提供されているが，これを使用すると
粘度が高いためモールドの際にダイステージの変位を発
生し，その対策が要求されている。In recent years, with the demand for miniaturization of packages and high integration of chips in semiconductor devices, the area occupied by the chips with respect to the package has increased, and water absorption management during mounting of the semiconductor device and management of time left after unpacking and Also, because there are restrictions such as the specification of the mounting method, a high-strength mold compound is provided, but when this is used, the die stage displacement occurs during molding due to the high viscosity, and measures against it Is required.
【０００３】[0003]
【従来の技術】図３(A),(B) は従来の樹脂封止方法の説
明図である。図３(A) はA-A 断面図, 図３(B) は平面図
で，１は上金型，２は下金型，３はリードフレームのサ
ポートバー，４はリードフレームのダイステージ，５は
半導体チップ，６はワイヤである。2. Description of the Related Art FIGS. 3A and 3B are explanatory views of a conventional resin sealing method. 3A is a sectional view taken along the line AA, FIG. 3B is a plan view, 1 is an upper die, 2 is a lower die, 3 is a lead frame support bar, 4 is a lead frame die stage, and 5 is The semiconductor chip 6 is a wire.
【０００４】従来の樹脂封止方法では，リードフレーム
に２本ないし４本のサポートバー３が設けられ，これに
より半導体チップ５がダイボンディングされたダイステ
ージ４を宙吊りにした状態で上下の金型１，２内に保持
され，ここに樹脂を注入していた。In the conventional resin encapsulation method, two or four support bars 3 are provided on the lead frame, and the die stage 4 to which the semiconductor chip 5 is die-bonded is suspended from the upper and lower molds. It was held in the inside of 1 and 2, and the resin was injected here.
【０００５】[0005]
【発明が解決しようとする課題】従来例では，樹脂が高
粘度になると金型内に高圧で注入しなければならず，そ
の結果ステージが傾く等の変位を起こしていた。従っ
て，配線のワイヤ６に疲労を与えたり，最悪の場合はワ
イヤを断線させたり，また，薄型パッケージにおいては
ワイヤが露出するといった障害が発生した。In the prior art example, when the resin became highly viscous, it had to be injected into the mold at a high pressure, resulting in displacement such as tilting of the stage. Therefore, the wire 6 of the wiring is fatigued, the wire is broken in the worst case, and the wire is exposed in the thin package.
【０００６】本発明は高粘度樹脂を用いてもダイステー
ジに変位を与えない樹脂封止方法の提供を目的とする。An object of the present invention is to provide a resin encapsulation method which does not give displacement to a die stage even when a high viscosity resin is used.
【０００７】[0007]
【課題を解決するための手段】上記課題の解決は，１）
半導体チップ５を樹脂封止した半導体装置であって，該
樹脂に形成され，該半導体チップ５の裏面あるいは該半
導体チップを搭載したダイステージ４の裏面に到達する
貫通口と，該貫通口にはめ込まれたパッキン８と，該パ
ッキンに形成され，該半導体チップ５の裏面あるいは該
半導体チップを搭載したダイステージ４の裏面に到達す
る孔とを有する半導体装置，あるいは２）モールド用金
型内において半導体チップ５の裏面あるいは半導体チッ
プを搭載したダイステージ４の裏面を前記パッキン８を
介して該金型に設けられた排気口７より真空吸引して金
型に固定した状態で樹脂を注入する半導体装置の製造方
法により達成される。[Means for Solving the Problems] 1)
A semiconductor device in which a semiconductor chip 5 is sealed with a resin, the through hole being formed of the resin and reaching the back surface of the semiconductor chip 5 or the back surface of a die stage 4 on which the semiconductor chip is mounted, and a through hole fitted into the through hole. A semiconductor device having a sealed packing 8 and a hole formed in the packing and reaching the back surface of the semiconductor chip 5 or the back surface of the die stage 4 on which the semiconductor chip is mounted, or 2) a semiconductor in a molding die. A semiconductor device in which the back surface of the chip 5 or the back surface of the die stage 4 on which the semiconductor chip is mounted is vacuum-sucked from the exhaust port 7 provided in the mold through the packing 8 and is fixed to the mold to inject the resin. It is achieved by the manufacturing method of.
【０００８】[0008]
【作用】図１は本発明の原理説明図である。本発明で
は，樹脂封止時に金型内においてダイステージ４の裏面
をパッキン８を介して金型２に設けられた排気口７より
真空引きしてダイステージを金型２に固定した状態で樹
脂を注入するためダイステージは変位を起こさない。FIG. 1 is a diagram for explaining the principle of the present invention. According to the present invention, when the resin is sealed, the back surface of the die stage 4 is evacuated from the exhaust port 7 provided in the die 2 through the packing 8 in the die to fix the die stage to the die 2. Therefore, the die stage does not cause displacement.
【０００９】また，このパッキンはそのままパッケージ
内に埋め込まれるため，パッキンを金属等熱伝導率の高
い材料で作製すれぱパッケージの放熱特性はよくなる。
また，樹脂が吸湿した水分はステージ裏面に留まること
が多く，バーンイン工程等の加熱により膨張してクラッ
クの原因となる。これに対して，本発明ではパッキンの
内部には樹脂が入り込まないためステージの裏面が露出
することになり，ステージ裏面に留まる水分を抜くこと
ができる。Further, since this packing is embedded in the package as it is, the heat dissipation characteristic of the package is improved when the packing is made of a material having a high thermal conductivity such as metal.
In addition, the moisture absorbed by the resin often stays on the back surface of the stage, and expands due to heating in the burn-in process and causes cracks. On the other hand, in the present invention, since the resin does not enter the inside of the packing, the back surface of the stage is exposed, and the water remaining on the back surface of the stage can be removed.
【００１０】[0010]
【実施例】図１を用いて実施例を説明する。下金型２に
排気口７を開け，リードフレームをセットする前にパッ
キン８をセットし，排気口７より真空引きしてダイステ
ージ４を下金型２に吸着させ，次いで金型内に樹脂を注
入する。EXAMPLE An example will be described with reference to FIG. Open the exhaust port 7 in the lower mold 2, set the packing 8 before setting the lead frame, evacuate from the exhaust port 7 to make the die stage 4 adsorb to the lower mold 2, and then resin in the mold. Inject.
【００１１】あるいは，ダイステージ４の裏面にパッキ
ン８を固着させた状態で，リードフレームを金型にセッ
トし，次いで，排気口７より真空引きして金型内に樹脂
を注入する。Alternatively, with the packing 8 fixed to the back surface of the die stage 4, the lead frame is set in the mold, and then vacuum is drawn from the exhaust port 7 to inject the resin into the mold.
【００１２】ここで，パッキン８は金型とダイステージ
のクリアランスを決める役目をしており，パッキン８の
厚さはパッケージ下面からダイステージ下部までの高さ
の設計値と同一にし，その高さでダイステージを金型に
固定する。Here, the packing 8 plays a role of determining the clearance between the die and the die stage, and the thickness of the packing 8 is made equal to the design value of the height from the lower surface of the package to the lower part of the die stage. To fix the die stage to the mold.
【００１３】この際に用いるパッキンの形状の例を図２
に示す。図中，点線で示されるようにいずれも排気口７
に接続する孔を有する。また，パッキン８は例えば銅，
または鉄ニッケル合金で作製される。An example of the shape of the packing used in this case is shown in FIG.
Shown in. As shown by the dotted line in the figure, both are exhaust ports 7.
Has a hole connecting to. Also, the packing 8 is, for example, copper,
Alternatively, it is made of iron-nickel alloy.
【００１４】この実施例では，パッキンの周囲に突起を
設けているため，封止後パッキンが脱落することはな
い。実施例では，リードフレームを使用した半導体装置
について説明したが，TCP(Tape Carrier Package)のよ
うに, ダイステージおよびサポートバーのない半導体装
置においては, ダイステージの代わりに直接チップ裏面
をパッキンを介して真空吸引して金型に固定する。In this embodiment, since the protrusion is provided around the packing, the packing does not fall off after the sealing. Although the semiconductor device using the lead frame has been described in the embodiment, in a semiconductor device without a die stage and a support bar such as TCP (Tape Carrier Package), instead of the die stage, the back surface of the chip is directly inserted via a packing. Vacuum suction and fix to the mold.
【００１５】[0015]
【発明の効果】本発明によれば，高粘度樹脂を用いても
チップまたはダイステージに変位を与えないで樹脂封止
を行うことができる。この結果，パッケージの小型化，
チップの高集積化に対応できるようになった。According to the present invention, even if a high-viscosity resin is used, resin encapsulation can be performed without displacement of the chip or die stage. As a result, downsizing of the package,
It has become possible to support higher integration of chips.
【図１】 本発明の原理説明図FIG. 1 is an explanatory view of the principle of the present invention.
【図２】 パッキンの形状の例を示す図FIG. 2 is a diagram showing an example of the shape of packing.
【図３】 従来の樹脂封止方法の説明図FIG. 3 is an explanatory diagram of a conventional resin sealing method.
１ 上金型 ２ 下金型 ３ リードフレームのサポートバー ４ リードフレームのダイステージ ５ 半導体チップ ６ ワイヤ ７ 排気口 ８ パッキン 1 Upper mold 2 Lower mold 3 Lead frame support bar 4 Lead frame die stage 5 Semiconductor chip 6 Wire 7 Exhaust port 8 Packing
Claims (2)
装置であって， 該樹脂に形成され，該半導体チップ(5) の裏面あるいは
該半導体チップを搭載したダイステージ(4）の裏面に到
達する貫通口と， 該貫通口にはめ込まれたパッキン(8) と， 該パッキンに形成され，該半導体チップ(5) の裏面ある
いは該半導体チップを搭載したダイステージ(4）の裏面
に到達する孔とを有することを特徴とする半導体装置。1. A semiconductor device in which a semiconductor chip (5) is sealed with a resin, the semiconductor device being formed of the resin, the back surface of the semiconductor chip (5) or the back surface of a die stage (4) having the semiconductor chip mounted thereon. A through hole to reach, a packing (8) fitted into the through hole, and a back surface of the semiconductor chip (5) or a back surface of a die stage (4) mounted with the semiconductor chip formed on the packing. A semiconductor device having a hole.
(5) の裏面あるいは半導体チップを搭載したダイステー
ジ(4）の裏面を前記パッキン(8) を介して該金型に設け
られた排気口(7) より真空吸引して金型に固定した状態
で樹脂を注入することを特徴とする半導体装置の製造方
法。2. A semiconductor chip in a molding die.
A state in which the back surface of (5) or the back surface of a die stage (4) on which a semiconductor chip is mounted is vacuum-sucked from the exhaust port (7) provided in the mold through the packing (8) and fixed to the mold. A method for manufacturing a semiconductor device, which comprises injecting a resin by means of.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3291075A JPH05129352A (en) | 1991-11-07 | 1991-11-07 | Semiconductor device and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3291075A JPH05129352A (en) | 1991-11-07 | 1991-11-07 | Semiconductor device and manufacturing method thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH05129352A true JPH05129352A (en) | 1993-05-25 |
Family
ID=17764111
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3291075A Withdrawn JPH05129352A (en) | 1991-11-07 | 1991-11-07 | Semiconductor device and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH05129352A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116441752A (en) * | 2023-04-27 | 2023-07-18 | 广州丰江微电子有限公司 | High-precision positioning lead frame cutting system |
-
1991
- 1991-11-07 JP JP3291075A patent/JPH05129352A/en not_active Withdrawn
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116441752A (en) * | 2023-04-27 | 2023-07-18 | 广州丰江微电子有限公司 | High-precision positioning lead frame cutting system |
| CN116441752B (en) * | 2023-04-27 | 2023-11-21 | 广州丰江微电子有限公司 | High-precision positioning lead frame cutting system |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A300 | Withdrawal of application because of no request for examination |
Free format text: JAPANESE INTERMEDIATE CODE: A300 Effective date: 19990204 |