KR0163872B1 - Packing structure having bond wire error prevention blocking lead - Google Patents

Packing structure having bond wire error prevention blocking lead Download PDF

Info

Publication number
KR0163872B1
KR0163872B1 KR1019950051327A KR19950051327A KR0163872B1 KR 0163872 B1 KR0163872 B1 KR 0163872B1 KR 1019950051327 A KR1019950051327 A KR 1019950051327A KR 19950051327 A KR19950051327 A KR 19950051327A KR 0163872 B1 KR0163872 B1 KR 0163872B1
Authority
KR
South Korea
Prior art keywords
blocking
lead
packing structure
chip
leads
Prior art date
Application number
KR1019950051327A
Other languages
Korean (ko)
Other versions
KR970053706A (en
Inventor
이상협
이윤수
Original Assignee
김광호
삼성전자주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김광호, 삼성전자주식회사 filed Critical 김광호
Priority to KR1019950051327A priority Critical patent/KR0163872B1/en
Publication of KR970053706A publication Critical patent/KR970053706A/en
Application granted granted Critical
Publication of KR0163872B1 publication Critical patent/KR0163872B1/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/4826—Connecting between the body and an opposite side of the item with respect to the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73215—Layer and wire connectors

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

본 발명은 패킹 구조에 관한 것으로, 리드 온 칩(lead on chip)의 성형 공정시에 칩 상에 존재하는 내부리드 외에 성형 금형 내로 유입되는 성형 수지를 적절하게 막을 수 있는 블로킹 리드를 별도로 설치하여 성형 수지의 과도한 유속(流速) 및 유량(流量)에 의해 발생되는 본딩 와이어의 스위핑(sweeping) 현상을 방지할 수 있는 것을 특징으로 한다.The present invention relates to a packing structure, wherein in addition to the internal lead existing on the chip during the molding process of a lead on chip, a blocking lead capable of appropriately blocking the molding resin flowing into the molding die is formed separately. A sweeping phenomenon of the bonding wire caused by excessive flow rate and flow rate of the resin can be prevented.

Description

본딩 와이어 불량 방지용 블로킹 리드(bolcking lead)를 갖는 패킹 구조Packing structure with blocking lead for bonding wire failure prevention

제1도는 종래 기술에 의한 패킹 구조의 성형 공정을 나타내는 단면도.1 is a cross-sectional view showing a molding process of a packing structure according to the prior art.

제2도는 본 발명에 의한 본딩 와이어 불량 방지용 블로킹 리드를 갖는 패킹 구조의 성형 공정을 나타내는 단면도.2 is a cross-sectional view showing a molding process of a packing structure having a blocking lead for preventing defects in bonding wires according to the present invention.

제3도는 제2도의 성형 금형을 제거하여 성형 수지의 흐름을 나타내는 사시도.3 is a perspective view showing the flow of molding resin by removing the molding die of FIG.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings

10 : 칩 12 : 본딩 패드10 chip 12 bonding pad

20 : 폴리이미드 테이프 30 : 본딩 와이어20 polyimide tape 30 bonding wire

40 : 내부리드 50 : 외부리드40: inner lead 50: outer lead

100 : 상부 금형 110,210 : 캐비티100: upper mold 110,210: cavity

140 : 블로킹 리드 200 : 하부 금형140: blocking lead 200: lower mold

본 발명은 패킹 구조에 관한 것으로, 더욱 상세하게는 리드 온 칩(lead on chip) 패키지의 성형 공정 시에 칩 상에 존재하는 내부리드 외에 성형 금형 내로 유입되는 성형 수지를 적절하게 막을 수 있는 블로킹 리드를 별도로 설치하여 성형 수지의 과도한 유속(流速) 및 유량(流量)에 의해 발생되는 본딩 와이어의 스위핑(sweeping) 현상을 방지할 수 있는 본딩 와이어 불량 방지용 블로킹 리드(blocking lead)를 갖는 패킹 구조에 관한 것이다.The present invention relates to a packing structure, and more particularly, to a blocking lead capable of appropriately blocking a molding resin introduced into a molding die in addition to an internal lead existing on a chip during a molding process of a lead on chip package. For a packing structure having a blocking lead for preventing defects in bonding wires, which can prevent the sweeping phenomenon of the bonding wires caused by excessive flow rate and flow rate of the molding resin by separately installing will be.

통상적인 패키지는 칩의 본딩 패드들과 그들에 대응되는 리드프레임의 내부리드들이 본딩 와이어에 의해서 각기 전기적 연결이 된다. 그리고, 이 전기적 연결 부분은 외부의 환경으로부터 보호되기 위해 에폭시 계열의 성형 수지에 의해서 봉지된다.In a typical package, the bonding pads of the chip and the inner leads of the leadframes corresponding thereto are electrically connected by the bonding wires. And this electrical connection part is sealed by epoxy-type molding resin in order to protect from external environment.

상기 에폭시에 의한 성형 공정은 패키지의 대량 생산 및 낮은 제조 단가 등의 장점을 갖으나, 성형 금형 내로 과도한 유속과 유량을 갖은 성형 수지가 유입될 경우에 전기적 연결 부분들에 손상을 가하는 단점을 내포하고 있다.The molding process by epoxy has advantages such as mass production of package and low manufacturing cost, but it impairs electrical connection parts when molding resin with excessive flow rate and flow rate flows into the molding die. have.

제1도는 종래 기술에 의해 패킹 구조의 성형 공정을 나타내는 단면도이다. 제1도를 참조하면, 상하부 금형(100),(200)에 형성된 캐비티(110),(210) 내에 반조립 상태의 리드프레임이 탑재된 구조이며, 그 반조립 상태의 리드프레임은 와이어 본딩 공정이 완료된 상태를 말한다.1 is a cross-sectional view showing a molding process of a packing structure according to the prior art. Referring to FIG. 1, the semi-assembled lead frame is mounted in the cavities 110 and 210 formed in the upper and lower molds 100 and 200, and the lead frame in the semi-assembled state is a wire bonding process. Say this is complete.

여기서, 반조립 상태의 리드프레임은 칩(10)의 상부면 가장자리와 내부리드들(40)의 하부면이 폴리이미드 테이프(20)에 의해서 접착되어 있으며, 칩(10)의 중심부분에 형성된 복수개의 본딩 패드들(12)이 그들(12)에 각기 대응되는 리드프레임의 내부리드들(40)과 본딩 와이어(30)에 의해 각기 전기적으로 연결된 구조를 갖는다.Here, in the lead frame in the semi-assembled state, the upper surface edge of the chip 10 and the lower surface of the inner leads 40 are bonded by the polyimide tape 20, and a plurality of lead frames are formed in the central portion of the chip 10. The bonding pads 12 have a structure in which each of the two bonding pads 12 is electrically connected to the inner leads 40 and the bonding wires 30 of the lead frame, respectively.

제1도에 있어서, 본 도면의 앞에서 뒤로 성형 수지가 유동되며, 그 성형 수지의 유동에 의해 상기 본딩 와이어(30)의 스위핑이 발생된다.In FIG. 1, the molding resin flows from the front to the front of the drawing, and the sweeping of the bonding wire 30 is generated by the flow of the molding resin.

이와 같은 구조를 갖는 반조립 상태의 패킹 구조는, 성형 금형에 탑재되어 성형 공정이 진행되는 경우에 성형 수지의 과도한 유속과 그로 인한 유량에 의해 상기 칩과 내부리드들을 각기 전기적 연결하는 매개인 본딩 와이어의 루프가 밀려서 스위핑 현상이 발생되며, 그로 인해 완제품인 패키지의 불량을 야기한다.The semi-assembled packing structure having such a structure is a bonding wire, which is a medium for electrically connecting the chip and the inner leads to each other by the excessive flow rate of the molding resin and the resulting flow rate when the molding process is carried out in the molding die. The loop of p is pushed, causing a sweeping phenomenon, which causes a failure of the finished package.

따라서 본 발명의 목적은 리드 온 칩 패키지의 성형 공정 시에 칩 상에 존재하는 내부리드 외에 성형 금형 내로 유입되는 성형 수지를 적절하게 막을 수 있는 블로킹 리드를 별도로 설치하여 성형 수지의 과도한 유속 및 유량에 의해 발생되는 본딩 와이어의 스위핑 현상을 방지할 수 있는 본딩 와이어 불량 방지용 블로킹 리드를 갖는 패킹 구조를 제공하는데 있다.Accordingly, an object of the present invention is to provide a blocking lead that can adequately block the molding resin flowing into the molding die in addition to the internal lead existing on the chip during the molding process of the lead-on chip package, thereby preventing excessive flow rate and flow rate of the molding resin. The present invention provides a packing structure having a blocking lead for preventing a defect of a bonding wire, which can prevent a sweeping phenomenon of the bonding wire caused by the bonding wire.

상기 목적을 달성하기 위하여, 복수개의 본딩 패드를 갖는 칩과, 그 칩의 일면과 그 칩의 상부 상에 존재되어 상기 칩과 접착되어 있으며, 상기 본딩 패드들에 각기 대응되어 전기적 연결된 내부리드들과, 상기 내부리드들의 두께보다 더 두꺼운 블로킹 리드를 갖는 리드프레임을 갖는 것을 특징으로 하는 본딩 와이어 불량 방지용 블로킹 리드(blocking lead)를 갖는 패킹 구조를 제공한다.In order to achieve the above object, there is provided a chip having a plurality of bonding pads, the inner lead is present on one surface of the chip and the upper portion of the chip and bonded to the chip, and electrically connected to the bonding pads, respectively. It provides a packing structure having a blocking lead (blocking lead) for preventing failure of the bonding wire, characterized in that having a lead frame having a blocking lead thicker than the thickness of the inner leads.

이하, 첨부 도면을 참조하여 본 발명을 보다 상세하게 설명하고자 한다.Hereinafter, the present invention will be described in more detail with reference to the accompanying drawings.

제2도는 본 발명에 의한 본딩 와이어 불량 방지용 블로킹 리드를 갖는 패킹 구조의 성형 공정을 나타내는 단면도이다.2 is a cross-sectional view showing a molding process of a packing structure having a blocking lead for preventing defects in bonding wires according to the present invention.

제3도는 제2도의 성형 금형을 제거하여 성형 수지의 흐름을 나타내는 사시도이다.3 is a perspective view showing the flow of molding resin by removing the molding die of FIG.

제2도 및 제3도를 참조하면, 본 발명에 의한 패킹 구조는 성형 수지의 유입에 의한 본딩 와이어(30)의 스위핑을 방지하기 위해 성형 수지가 유입되는 부분에 블로킹 리드(140)가 설치되어 있다.Referring to FIGS. 2 and 3, the packing structure according to the present invention has a blocking lead 140 installed at a portion where a molding resin is introduced to prevent the sweeping of the bonding wire 30 due to the introduction of the molding resin. have.

여기서, 블로킹 리ㄷ(140)의 두께는 통상적인 내부리드들(40)보다 더 두꺼우나, 성형 금형(100),(200)에 의해 클램핑되는 영역의 두께는 통상적인 내부리드들(40)의 두께와 동일하다.Here, the thickness of the blocking lead 140 is thicker than the conventional inner leads 40, but the thickness of the region clamped by the molding die 100 and 200 is the thickness of the conventional inner leads 40. Same as thickness.

블로킹 리드(140)의 두께가 통상적인 내부리드들(40)과 동일한 경우도 변형가능하나, 이는 바람직하지 못하다. 왜냐하면, 성형 금형(100),(200)에 클램핑되는 블로킹 리드(140)의 두께와 내부리드들(40)의 두께가 차이가 나면, 그 차이난 부분으로 성형 수지에 의한 플래쉬(flash)가 발생되기 때문이다.Although the thickness of the blocking lead 140 is the same as that of the conventional inner leads 40, it is deformable, but this is not preferable. If the thickness of the blocking lead 140 clamped to the molding dies 100 and 200 and the thickness of the inner leads 40 are different from each other, a flash is generated by the molding resin into the difference portion. Because it becomes.

제3도를 참조하여 블로킹 리드(140)에 대해 좀 더 상세히 설명하면, 본 도면의 화살표는 성형 수지의 유입 방향이다. 그리고, 블로킹 리드(140)의 두께는 제2도에 나타나 있는 바와 같이 통상적인 내부리드들(40) 보다는 더 두껍게 되어 있다.Referring to the blocking lead 140 in more detail with reference to Figure 3, the arrow in this figure is the inflow direction of the molding resin. And, the thickness of the blocking lead 140 is thicker than the conventional inner leads 40 as shown in FIG.

또한, 블로킹 리드(140)는 통상적인 리드 온 칩 구조의 내부리드들(40)과는 달리 칩(10)의 외곽에 배치되어 있으며, 블로킹 리드(140)는 도면에 나타난 바와 같이 한 쌍을 이루며 배치되어 있다.In addition, the blocking leads 140 are disposed outside the chip 10, unlike the internal leads 40 of the conventional lead-on chip structure, and the blocking leads 140 are paired as shown in the drawing. It is arranged.

그리고, 상기 블로킹 리드의 두꺼운 부분은 상기 성형 금형의 캐비티의 폭보다는 더 작게 형성되어야 한다.And, the thick portion of the blocking lead should be formed smaller than the width of the cavity of the molding die.

또한, 상기 블로킹 리드는 상기 성형 수지가 유입되는 방향에 하나가 형성되어 있어도 무관하나, 바람직하게는 제2도 및 제3도에서 예시한 바와 같이 한 쌍을 이루는 것이 좋다.In addition, although one blocking lead may be formed in the direction in which the molding resin flows, it is preferable to form a pair as illustrated in FIGS. 2 and 3.

따라서, 본 발명에 따른 구조에 따르면, 성형 금형 내로 유입되는 성형 수지를 적절하게 막을 수 있는 블로킹 리드를 별도로 성치하여 성형 수지의 과도한 유속(유속流速) 및 유량(流量)에 의해 발생되는 본딩 와이어의 스위핑(sweeping) 현상을 방지할 수 이점(利點)이 있다.Therefore, according to the structure according to the present invention, a blocking lead capable of appropriately blocking the molding resin flowing into the molding die is separately set so that the bonding wire generated by the excessive flow rate and the flow rate of the molding resin can be prevented. There is an advantage that can prevent the sweeping phenomenon.

Claims (5)

복수개의 본딩 패드를 갖는 칩과; 그 칩의 일면과 그 칩의 상부 상에 존재되어 상기 칩과 접착되어 있으며, 상기 본딩 패드들에 각기 대응되어 전기적 연결된 내부리드들과, 상기 내부리드들의 두께보다 더 두꺼운 블로킹 리드를 갖는 리드프레임을 갖는 것을 특징으로 하는 본딩 와이어 불량 방지용 블로킹 리드(blocking lead)를 갖는 패킹 구조.A chip having a plurality of bonding pads; A lead frame having inner leads on one side of the chip and on top of the chip and bonded to the chip and electrically connected to the bonding pads, and having blocking leads thicker than the thickness of the inner leads. Packing structure having a blocking lead (blocking lead) for preventing failure of the bonding wire, characterized in that it has. 제1항에 있어서, 상기 본딩 패드들과 그들에 각기 대응된 상기 내부리드들을 각기 전기적 연결하는 수단이 본딩 와이어인 것을 특징으로 하는 본딩와이어 불량 방지용 블로킹 리드를 갖는 패킹 구조.The packing structure according to claim 1, wherein a means for electrically connecting the bonding pads and the inner leads respectively corresponding to the bonding pads is a bonding wire. 제1항에 있어서, 상기 블로킹 리드가 상기 칩의 외곽에 이격되어 배치된 것을 특징으로 하는 본딩 와이어 불량 방지용 블로킹 리드를 갖는 패킹 구조.The packing structure according to claim 1, wherein the blocking leads are spaced apart from the outside of the chip. 제1항 내지 제3항 중의 어느 한 항에 있어서, 상기 블로킹 리드가 성형 수지의 유입 방향에 배치되어 상기 성형 수지의 과도한 유속에 의한 상기 본딩 와이어의 불량을 방지하는 것을 특징으로 하는 본딩 와이어 불량 방지용 블로킹 리드를 갖는 패킹 구조.The blocking wire failure prevention method according to any one of claims 1 to 3, wherein the blocking lead is disposed in an inflow direction of the molding resin to prevent a failure of the bonding wire due to an excessive flow rate of the molding resin. Packing structure with blocking leads. 제1항에 있어서, 상기 블로킹 리드가 상기 칩을 사이에 두고 한 쌍을 이루며 배치된 것을 특징으로 하는 본딩 와이어 불량 방지용 블로킹 리드를 갖는 패킹 구조.The packing structure according to claim 1, wherein the blocking leads are arranged in pairs with the chips interposed therebetween.
KR1019950051327A 1995-12-18 1995-12-18 Packing structure having bond wire error prevention blocking lead KR0163872B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950051327A KR0163872B1 (en) 1995-12-18 1995-12-18 Packing structure having bond wire error prevention blocking lead

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950051327A KR0163872B1 (en) 1995-12-18 1995-12-18 Packing structure having bond wire error prevention blocking lead

Publications (2)

Publication Number Publication Date
KR970053706A KR970053706A (en) 1997-07-31
KR0163872B1 true KR0163872B1 (en) 1998-12-01

Family

ID=19440956

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019950051327A KR0163872B1 (en) 1995-12-18 1995-12-18 Packing structure having bond wire error prevention blocking lead

Country Status (1)

Country Link
KR (1) KR0163872B1 (en)

Also Published As

Publication number Publication date
KR970053706A (en) 1997-07-31

Similar Documents

Publication Publication Date Title
KR200309906Y1 (en) lead frame for fabricating semiconductor package
US6277225B1 (en) Stress reduction feature for LOC lead frame
US5623163A (en) Leadframe for semiconductor devices
US5932923A (en) Semiconductor device packages having dummy block leads and tie bars with extended portions to prevent formation of air traps in the encapsulate
JPH047848A (en) Manufacture of resin sealing type semiconductor equipment and resin sealing die and lead frame used therein
KR0163872B1 (en) Packing structure having bond wire error prevention blocking lead
KR100216064B1 (en) Semiconductor chip package
KR0151828B1 (en) A package molding apparatus
JPS6197955A (en) Lead frame
KR100298688B1 (en) Air Vent Structure of Mold Mold for Semiconductor Package Manufacturing
JPH06196609A (en) Lead frame and semiconductor device using same
JPH05218508A (en) Manufacture of optical semiconductor device
KR0172020B1 (en) Resin-sealed semiconductor device
JP2855787B2 (en) Mold for manufacturing resin-encapsulated semiconductor device and method for manufacturing resin-encapsulated semiconductor device using the same
JP3185354B2 (en) Method for manufacturing semiconductor device and resin sealing device for semiconductor device
KR100983304B1 (en) Lead frame, semiconductor package manufactured by applying same, and manufacturing method of semiconductor package
JPS59132639A (en) Lead frame
KR100258876B1 (en) Method for fabricating test package of semiconductor
KR0119759Y1 (en) Bottom Leaded Semiconductor Package
JP2984137B2 (en) Resin-sealed semiconductor device
JPH0714965A (en) Lead frame for semiconductor device
KR930007177Y1 (en) Lead frame without dam-bar
JPS63131558A (en) Lead frame for resin seal type semiconductor device
JP3514516B2 (en) Method for manufacturing semiconductor device
JPH04284658A (en) Manufacture of lead frame and integrated circuit using the same

Legal Events

Date Code Title Description
A201 Request for examination
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20060830

Year of fee payment: 9

LAPS Lapse due to unpaid annual fee