JPS63289845A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS63289845A JPS63289845A JP12521387A JP12521387A JPS63289845A JP S63289845 A JPS63289845 A JP S63289845A JP 12521387 A JP12521387 A JP 12521387A JP 12521387 A JP12521387 A JP 12521387A JP S63289845 A JPS63289845 A JP S63289845A
- Authority
- JP
- Japan
- Prior art keywords
- metal film
- photosensitive resin
- bump
- etching
- metal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 34
- 238000004519 manufacturing process Methods 0.000 title claims description 12
- 229910052751 metal Inorganic materials 0.000 claims abstract description 62
- 239000002184 metal Substances 0.000 claims abstract description 62
- 239000011347 resin Substances 0.000 claims abstract description 24
- 229920005989 resin Polymers 0.000 claims abstract description 24
- 239000000758 substrate Substances 0.000 claims abstract description 12
- 238000007747 plating Methods 0.000 claims abstract description 6
- 238000010438 heat treatment Methods 0.000 claims description 8
- 238000000034 method Methods 0.000 claims description 7
- 238000000151 deposition Methods 0.000 claims 1
- 238000005530 etching Methods 0.000 abstract description 22
- 239000000956 alloy Substances 0.000 abstract description 8
- 229910045601 alloy Inorganic materials 0.000 abstract description 8
- 230000004888 barrier function Effects 0.000 abstract description 5
- 230000015572 biosynthetic process Effects 0.000 abstract 1
- 229910052782 aluminium Inorganic materials 0.000 description 6
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 6
- 238000004544 sputter deposition Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- QAOWNCQODCNURD-UHFFFAOYSA-N Sulfuric acid Chemical compound OS(O)(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-N 0.000 description 2
- 150000004767 nitrides Chemical class 0.000 description 2
- 238000007740 vapor deposition Methods 0.000 description 2
- 229910010165 TiCu Inorganic materials 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 1
- 238000002203 pretreatment Methods 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置の製造方法に関し、特に金属バンク
を有する半導体装置の製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method of manufacturing a semiconductor device, and particularly to a method of manufacturing a semiconductor device having a metal bank.
第３図ｔａ）乃至第３図（ｅ）は、従来の半導体装置の
製造方法を工程顆に示す断面図である。FIGS. 3(a) to 3(e) are cross-sectional views illustrating a conventional method for manufacturing a semiconductor device.
従来、この種の半導体装置は、第３図（ａ）に示すよう
に１半導体素子を形成した半導体基板１６上に、アルミ
ニウム層を蒸着法又はスパッタ法により１μｍ程度形成
し、このアルミニウム層全面に感光性樹脂を形成し、半
導体基板１６に形成した半導体素子に接続するためのパ
ッド電極領域のみを残して、アルミニウム層を選択的に
エツチングを行なう。その後感光性樹脂を除去し、パッ
ド電極１７上を含む全面に、絶縁膜１８としてＣＶＤ酸
化膜又はプラズマＣＶＤ窒化膜を形成する。次に感光性
樹脂を用いて、選択的に絶縁膜１８をエツチングし、パ
ッド電極１７の上方に第１の開口を形成する。Conventionally, in this type of semiconductor device, as shown in FIG. 3(a), an aluminum layer is formed to a thickness of about 1 μm by vapor deposition or sputtering on a semiconductor substrate 16 on which one semiconductor element is formed, and the entire surface of this aluminum layer is covered with A photosensitive resin is formed and the aluminum layer is selectively etched leaving only the pad electrode area for connection to the semiconductor element formed on the semiconductor substrate 16. Thereafter, the photosensitive resin is removed, and a CVD oxide film or a plasma CVD nitride film is formed as an insulating film 18 over the entire surface including the top of the pad electrode 17. Next, the insulating film 18 is selectively etched using a photosensitive resin to form a first opening above the pad electrode 17.
その後、第３図（ｂ）に示すように、パッド電極１７を
含む半導体基板の主全面に、第１．第２の金属膜１９．
２０例えばＴｉ、Ｃｕ等を約１０００Ａ程度スパッタ法
により形成し、バリアメタル及びメッキ電極とし、第２
の金属膜２０上に感光性樹脂２１を形成し、感光性樹脂
２１のパッド電極１７上方Ｋ、第１の開口より大きい第
２の開口を形成し、ここに第２の金属膜２０を露出させ
る。Thereafter, as shown in FIG. 3(b), the first. Second metal film 19.
20 For example, Ti, Cu, etc. are formed by sputtering to about 1000A to form a barrier metal and a plating electrode, and the second
A photosensitive resin 21 is formed on the metal film 20, and a second opening larger than the first opening is formed above the pad electrode 17 in the photosensitive resin 21, and the second metal film 20 is exposed there. .
次いで、第３図（Ｃ１に示すようＫ、露出した第２の金
属膜２０上に、電解メッキによりバンプ２２例えばＣｕ
バンプを形成する。この膜厚は、２０μｍ程度あれは充
分である。Next, as shown in FIG. 3 (C1), bumps 22, for example Cu
Form a bump. A film thickness of about 20 μm is sufficient.
次に、第３図（ｄ）に示すように、感光性樹脂２１を除
去後、第２の金属膜２０を、バンプ２２をマスクとして
、エツチングを行なう。次いで第３図（ｅ）に示すよう
に、バンプ２２ｔ−マスクとして、第１の金属膜１９を
エツチングすることにより、形成していた。Next, as shown in FIG. 3(d), after removing the photosensitive resin 21, the second metal film 20 is etched using the bumps 22 as a mask. Next, as shown in FIG. 3(e), a bump 22t-mask was formed by etching the first metal film 19.
前述した従来の半導体装置の製造方法によれば、バンプ
２２を形成し、感光性樹脂２１を除去した後、第３図ｔ
ｂ＋の第２の金属膜２０をエツチングし、さらに第１の
バリアメタルをウェットエツチング法によりエッチング
する際、バンプ材料（例えばＣｕ ）と第１の金属膜１
９（例えばＴｉ）のイオン化傾向の差によって、第１の
金属膜１９のエツチング速度が速くなるため、エツチン
グのコントロールが難かしく、バンプ２２及び第２の金
属膜２０の下部の第１の金属膜１９のサイドエッチが進
行するため、バンプ２２とパッド電極１７との密着強度
が低下したり、あるいはパッド電極１７がエツチングさ
れ、断線等を引き起こすという欠点があった。本発明の
目豹は前記欠点が解決され、バンプの密着強度を高めた
半導体装置の製造方法を提供することにある。According to the conventional semiconductor device manufacturing method described above, after forming the bumps 22 and removing the photosensitive resin 21, the process shown in FIG.
When etching the b+ second metal film 20 and further etching the first barrier metal by wet etching, the bump material (for example, Cu) and the first metal film 1 are etched.
9 (for example, Ti), the etching rate of the first metal film 19 increases, making it difficult to control the etching. Since the side etching of the bump 22 and the pad electrode 17 progresses, there is a drawback that the adhesion strength between the bump 22 and the pad electrode 17 is reduced, or the pad electrode 17 is etched, causing wire breakage. An object of the present invention is to provide a method for manufacturing a semiconductor device that solves the above-mentioned drawbacks and improves the adhesion strength of bumps.
本発明の半導体装置の製造方法の構成は、半導体素子を
形成した半導体基板上に前記半導体素子に接続するパッ
ド電極を形成する工程と、前記パッド電極を含む半導体
基板の表面に絶縁膜を形成し、前記パッド電極の上方に
第１の開口を形成する工程と、前記パッド電極及び前記
絶縁膜を有する前記半導体基板の表面に第１及び第２の
金属膜を形成する工程と、前記第２の金属膜上に感光性
樹脂を付着形成し、前記感光性樹脂の前記パッド電極の
上方に選択的に前記第１の開口部より大きい第２の開口
を形成し、前記第２の金属膜を露出させる工程と、前記
第２の金属膜上にバンプをメッキ形成し、前記感光性樹
脂を除去し、前記メッキ形成したバンプをマスクとして
前記第２の金属膜を除去した後、熱処理を行う工程と、
前記メッキしたバンプをマスクとして前記第１の金属膜
を除去する工程とを含むことを特徴とする。The method of manufacturing a semiconductor device of the present invention includes a step of forming a pad electrode connected to the semiconductor element on a semiconductor substrate on which a semiconductor element is formed, and forming an insulating film on the surface of the semiconductor substrate including the pad electrode. , forming a first opening above the pad electrode; forming first and second metal films on the surface of the semiconductor substrate having the pad electrode and the insulating film; A photosensitive resin is deposited and formed on the metal film, and a second opening larger than the first opening is selectively formed above the pad electrode of the photosensitive resin to expose the second metal film. a step of plating bumps on the second metal film, removing the photosensitive resin, removing the second metal film using the plated bumps as a mask, and then performing heat treatment. ,
The method includes a step of removing the first metal film using the plated bump as a mask.
本発明によれば、第２の金属膜をエツチングした後、熱
処理を行うことによって第１、第２の金属膜を合金化す
ることによりて、サイドエッチを防止し、安定なバンプ
構造を有する半導体装置が得られる。According to the present invention, after etching the second metal film, heat treatment is performed to alloy the first and second metal films, thereby preventing side etching and forming a semiconductor having a stable bump structure. A device is obtained.
次に本発明について図面を参照して詳細に説明する。 Next, the present invention will be explained in detail with reference to the drawings.
第１図ｔａｌ乃至第１図（ｆ）は、本発明の第１の実施
例の半導体装置の製造方法を工程順に示す断面図である
。まず第１図（ａ）Ｋ示すように、半導体素子を形成し
た半導体基板１上にアルミニウム層を蒸着法又はスパッ
タ法により１μｍ程度形成し、このアルミニウム層全面
に感光性樹脂を形成し、半導体基板１に形成した半導体
素子に接続するためのパッド電極２の領域のみを残して
、アルミニウム層を選択的にエツチングを行なう。その
後、この感光性樹脂を除去し、パッド電極２を含む全面
に絶縁膜３としてＣＶＤ酸化膜又はＣＶＤ窒化膜を形成
する。次に感光性樹脂を用いて選択的に絶縁膜をエツチ
ングし、パッド電極の上方に第１の開口を形成する。1 to 1(f) are cross-sectional views showing the method for manufacturing a semiconductor device according to the first embodiment of the present invention in order of steps. First, as shown in FIG. 1(a)K, an aluminum layer with a thickness of about 1 μm is formed on the semiconductor substrate 1 on which a semiconductor element is formed by vapor deposition or sputtering, a photosensitive resin is formed on the entire surface of the aluminum layer, and the semiconductor substrate 1 is coated with a photosensitive resin. The aluminum layer is selectively etched leaving only the area of the pad electrode 2 for connection to the semiconductor element formed in 1. Thereafter, this photosensitive resin is removed, and a CVD oxide film or a CVD nitride film is formed as an insulating film 3 over the entire surface including the pad electrode 2. Next, the insulating film is selectively etched using a photosensitive resin to form a first opening above the pad electrode.
その後、第１図ｔｂ）に示すように、パッド電極２を含
む半導体基板の全面に第１．第２の金属膜４゜５、例え
ばＴｉ Ｃｕ等を約１０００Ａ程度、スパッタ法によ
り形成しバリアメタル及びメッキ電極とし、さらに第２
の金属膜５上に感光性樹脂６を形成し、感光性樹脂６の
パッド電極上方に第１の開口より大きい第２の開口を形
成し、第２の金属膜５を露出させる。Thereafter, as shown in FIG. A second metal film 4°5, for example TiCu, etc., with a thickness of about 1000 A is formed by sputtering to serve as a barrier metal and a plating electrode, and then
A photosensitive resin 6 is formed on the metal film 5 , and a second opening larger than the first opening is formed above the pad electrode in the photosensitive resin 6 to expose the second metal film 5 .
次いで、第１図（ｃ）に示すように、露出した第２の金
属膜５上に、電解メッキによりバンプ７例えばＣｕバン
プを形成する。この膜淳は２０μｍ程度あれば充分であ
る。次に第１図（ｄ）に示すように、感光性樹脂６を除
去後、第２の金属膜５をピング７をマスクとしてエツチ
ングを行なう。Next, as shown in FIG. 1(c), bumps 7, for example, Cu bumps, are formed on the exposed second metal film 5 by electrolytic plating. A thickness of about 20 μm is sufficient for this film. Next, as shown in FIG. 1(d), after removing the photosensitive resin 6, the second metal film 5 is etched using the pin 7 as a mask.
次いで、第１図ｔｅｌに示すように熱処理を行うことに
より、第１の金属膜４と第２の金属膜５との合金属８を
形成する。その後第１図Ｔｆ＋に示すように、バンプ７
をマスクとして第１の金属膜４をエツチング除去するこ
とによって、サイドエッチのない安定したバンプ構造を
形成することができる。Next, as shown in FIG. 1, a heat treatment is performed to form an alloy 8 of the first metal film 4 and the second metal film 5. After that, as shown in FIG. 1 Tf+, the bump 7
By etching and removing the first metal film 4 using as a mask, a stable bump structure without side etching can be formed.
第２図（ａ）、第２図（ｂ）は、本発明の他の実施例の
半導体装置の製造方法を工程順に示す断面図である。本
実施例においては、前記第１図ｔｄｌまでの工程、即ち
第２の金属膜のエツチングまでの工程は、前述の実施例
と同一である。第２図（ａ）において、第１図（ｄＪの
工程後、熱処理を行うことにより合金層１４を形成する
。同時Ｋ、第１の金属膜１３の表面に１酸化膜が形成さ
れる。この酸化膜は第１の金属膜１３例えばＴｉ表面を
きわめてメッキされにくくする。この時Ｃｕ上にも酸化
膜が形成されるが、希硫酸等の前処理を行ない選択的に
除去できるため、Ｃｕ表面は選択的にメッキされやすく
なる。したがって、Ｃｕバンプ１５表面のみに選択的に
金属膜９をメッキ形成することができる。FIGS. 2(a) and 2(b) are cross-sectional views showing a method for manufacturing a semiconductor device according to another embodiment of the present invention in order of steps. In this embodiment, the steps up to tdl in FIG. 1, ie, the steps up to etching the second metal film, are the same as in the previous embodiment. In FIG. 2(a), after the process of FIG. 1 (dJ), an alloy layer 14 is formed by performing heat treatment. At the same time, a monooxide film is formed on the surface of the first metal film 13. The oxide film makes the surface of the first metal film 13, for example Ti, extremely difficult to be plated.At this time, an oxide film is also formed on the Cu, but it can be selectively removed by pre-treatment with dilute sulfuric acid, etc. Therefore, the metal film 9 can be selectively plated only on the surface of the Cu bump 15.
その後第１の金属膜１３をエツチングによって除去する
ことにより、バンプ１５を形成する金属が酸化されやす
い場合又はバンプ１５の硬度が高すぎる場合、例えばＣ
ｕバンプ表面に形成する金属膜９をバンプ表面にしかも
全面に形成でき、さらに合金層１４によってサイドエッ
チのない安定したバンプ構造を形成できる。Thereafter, by removing the first metal film 13 by etching, if the metal forming the bumps 15 is easily oxidized or the hardness of the bumps 15 is too high, e.g.
The metal film 9 formed on the surface of the u-bump can be formed on the entire surface of the bump, and furthermore, the alloy layer 14 can form a stable bump structure without side etching.
以上説明したように、本発明によれば、バンプ形成のた
めの電極、及びバリアメタルとして用いた第２の金属膜
をエツチングした後熱処理を行ない、第１．第２の金属
膜の合金層を形成した後、第１の金属膜のエツチングを
行うことにより、熱処理によって形成した合金層ができ
るから、第１の金属膜のエツチングの際に起こるサイド
エッチを防止できるという効果がある。As explained above, according to the present invention, after etching the second metal film used as an electrode for forming bumps and a barrier metal, heat treatment is performed, and the first metal film is etched. By etching the first metal film after forming the alloy layer of the second metal film, an alloy layer formed by heat treatment is formed, thereby preventing side etching that occurs when etching the first metal film. There is an effect that it can be done.
第１図ｔａｌ乃至第１図（ｆ＋は本発明の第１の実施例
の半導体装置の製造方法を工程順に示す断面図、第２図
（ａ）、第２図（ｂｌは本発明の第２の実施例の半導体
装置の製造方法を工程順に示す断面図、第３図＋ａ）乃
至第３図ｔｅｌは従来の製造方法を工程順に示す断面図
である。
１．１６・・・半導体基板、２，１７・・・パッド電極
、３．１８・・・絶縁膜、４，１３．１９・・・第１の
金属膜、５．２０・・・第２の金属膜、６．２１・・・
感光性樹脂、７．１５，２２・・・バンプ、８．１４・
・・合金層、９・・・金属膜。
／１冒を
代理人 弁理士 内 原 晋′、・ ゛。
第１図Figures 1 tal to 1 (f+ are cross-sectional views showing the method of manufacturing a semiconductor device according to the first embodiment of the present invention in order of steps, Figures 2 (a) and 2 (bl are cross-sectional views showing the method of manufacturing a semiconductor device according to the first embodiment of the present invention). 1.16...Semiconductor substrate, 2 , 17... Pad electrode, 3.18... Insulating film, 4, 13.19... First metal film, 5.20... Second metal film, 6.21...
Photosensitive resin, 7.15, 22... bump, 8.14.
...Alloy layer, 9...Metal film. Patent attorney Susumu Uchihara represents /1. Figure 1
Claims (1)
接続するパッド電極を形成する工程と、前記パッド電極
を含む半導体基板の表面に絶縁膜を形成し、前記パッド
電極の上方に第１の開口を形成する工程と、前記パッド
電極及び前記絶縁膜を有する前記半導体基板の表面に第
１及び第２の金属膜を形成する工程と、前記第２の金属
膜上に感光性樹脂を付着形成し、前記感光性樹脂の前記
パッド電極の上方に選択的に前記第１の開口より大きい
第２の開口を形成し、前記第２の金属膜を露出させる工
程と、前記第２の金属膜上にバンプをメッキ形成し、前
記感光性樹脂を除去し、前記メッキ形成したバンプをマ
スクとして、前記第２の金属膜を除去した後、熱処理を
行う工程と、前記メッキ形成したバンプをマスクとして
前記第１の金属膜を除去する工程とを含むことを特徴と
する半導体装置の製造方法。forming a pad electrode connected to the semiconductor element on a semiconductor substrate on which a semiconductor element is formed; forming an insulating film on the surface of the semiconductor substrate including the pad electrode; and forming a first opening above the pad electrode. forming first and second metal films on the surface of the semiconductor substrate having the pad electrode and the insulating film; depositing and forming a photosensitive resin on the second metal film; selectively forming a second opening larger than the first opening above the pad electrode of the photosensitive resin to expose the second metal film; and forming a bump on the second metal film. a step of plating, removing the photosensitive resin, removing the second metal film using the plated bump as a mask, and then performing heat treatment; and using the plated bump as a mask, performing heat treatment. A method for manufacturing a semiconductor device, comprising the step of removing a metal film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12521387A JPS63289845A (en) | 1987-05-21 | 1987-05-21 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12521387A JPS63289845A (en) | 1987-05-21 | 1987-05-21 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63289845A true JPS63289845A (en) | 1988-11-28 |
Family
ID=14904673
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12521387A Pending JPS63289845A (en) | 1987-05-21 | 1987-05-21 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63289845A (en) |
-
1987
- 1987-05-21 JP JP12521387A patent/JPS63289845A/en active Pending
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