JPS63288500A - Test circuit for reading rom - Google Patents

Abstract

PURPOSE:To shorten the reading test times of many ROMs by reading data from plural ROMs in parallel, selecting each of the read data and outputting them onto an internal data bus. CONSTITUTION:The ROMs 1, 4 addressed by ROM address generation circuits 2, 5 are precharged, thereafter data in addresses O are read out simultaneously, and the data are held in ROM data read buffers 3 and 6. Next, by means of a ROM test address signal 14 from a ROM test address generation circuit 10, the buffers 3, 6 are alternately selected, so that ROM test read signals 13 are sequentially outputted from a ROM test read signal generation circuit 9. Subsequently, the data from the ROMs 1, 4 held in the buffers 3, 6 are sequentially held in a data bus buffer 11 through the internal bus 15 at the timing of its up edge in the order of the data in the address O of the ROMs 1, 4, and the data in the address 1 of the same 1, 4, ..., and the data are outputted to outside of the LSI.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to a ROM read test circuit.

[Conventional technology]

Currently, CPt is used on one chip as a semiconductor integrated circuit.
LSIs are being manufactured that are equipped with memory such as J, ROM, and RAM, as well as multiple functional blocks. Conventionally, in such an LSI, all data in the ROM has been read and checked in order to test whether the data in the internal jalR0M is correct.

FIG. 4 is a block diagram of a conventional example of a ROM read test circuit.

A ROM test signal 22 indicating that the ROM is a read test is generated by the ROM test signal generation circuit 28, and upon receiving this signal, the instruction control circuit 27 stops its normal operation and enters the ROM 24 read test state. The ROM address generation circuit 25 receives the ROM test signal 22 and
Increase the address of M24 by +1 from 0. ROM
ROM2 addressed by the output of the address generation circuit 25
4 is read out and stored in ROM data read buffer 2.
6 to the internal data bus 15, enters the data buffer 11, and is output from the data bus buffer 11 to the outside of the LSI.

[Problem that the invention seeks to solve]

The conventional ROM read test circuit described above uses built-in ROM
There is no problem with test efficiency when there is only one RO, but the built-in RO
If there are multiple M's, address the desired ROM, precharge the address, read the data from the ROM, send the data to the data bus buffer via the internal bus, and then transfer the data from the data bus buffer to the outside of the LSI. Since the operation of transferring data to each address of each ROM is performed sequentially for each address of each ROM, there is a drawback that the ROM read test takes a long time. This trend is seen in modern microprocessors, where multiple ROMs, such as a ROM for storing instructions and a ROM for storing constants during calculations, are integrated into one.
When built into one LSI, the number increases as the number of built-in ROMs increases.

[Means for solving problems]

The first ROMD output test circuit of the present invention is provided for each ROM, is reset when a ROM test signal is input, and outputs an address signal incremented at the same predetermined timing from the top address to the ROM.
An address generation circuit, a ROM data read buffer that is provided for each ROM, holds the data read from the ROM, and outputs it to the data bus; A ROM test read signal generation circuit that outputs a ROM test read signal to be read to each ROM data read buffer, and a ROM test address generation circuit that outputs a selection control signal that selects the ROM data read buffer door to each ROM data read buffer. Then, during a ROM read test, a ROM test signal is output to an external circuit, a ROM address generation circuit, a ROM data read buffer, a ROM test read signal generation circuit, and a ROM test address generation circuit, thereby allowing the external circuit to access the ROM. and a ROM test signal generation circuit that inhibits and enables a ROM data read buffer, a ROM test read signal generation circuit, and a ROM test address generation circuit.

The second ROM read test circuit of the present invention includes a plurality of RO
A ROM address generation circuit is provided in common to each ROM of a composite ROM in which M is combined, and when a ROM test signal is input, it is reset and gives the same address to all ROMs at the same time, and a ROM test read signal is input as a selection signal. , selects the data read out in parallel from each ROM, and selects the data read out in parallel from each ROM.
The ROM data switching circuit outputs data for each OM, and the output of the ROM data switching circuit is input and held, and the ROM
When a test read signal is input, the ROM data read buffer outputs the held data to the data bus, and the ROM test read signal that reads the data held in the ROM data read buffer is output to the ROM data read buffer and ROM data switching circuit. ROM test read signal generation circuit, ROM test signal to external circuit,
ROM test that outputs to the ROM address generation circuit, ROM data read buffer, and ROM test read signal generation circuit, prohibits access to the ROM by external circuits, and enables the ROM data read buffer and ROM test read signal generation circuit. It has a signal generation circuit.

[Effect]

The first ROM read test circuit operates multiple ROM address generation circuits simultaneously to simultaneously read data from each of the multiple ROMs and hold it in each ROM data read buffer, and then sequentially selects the ROM data read buffers. and outputs the data onto the internal data bus.

Further, the second ROM read test circuit operates the ROM address generation circuit to read data simultaneously from each of the plurality of ROMs constituting the composite ROM.
The data is selected by the M data switching circuit and outputted onto the internal data bus via the ROM data read buffer.

In this way, by reading multiple ROMs simultaneously,
ROM read test time can be shortened.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of a first embodiment of the ROM m output test circuit of the present invention, and FIG. 2 is a timing chart showing the operation of the circuit of FIG.

ROM address generation circuit 2.5 receives ROM test signal 12
When inputted, it is reset, and address signals incremented from the first address at the same predetermined timing are outputted to the ROMs 1.4, and the ROM data read buffers 3.6 each hold the data read from the ROMs 1.4. The ROM test address generation circuit 10 is a ROM
A test address signal 14 is generated, one of the ROM data read buffers 3.6 is sequentially selected, the held data is read onto the internal data bus 15, and the data is outputted to the outside of the LSI via the data bus buffer 11. ROM test read signal generation circuit 9 generates ROM test read signal 13 to control reading of ROM data read buffer 3.6. The ROM test signal generation circuit 8 generates the ROM test signal 12, stops the normal operation of the instruction control circuit 7, and also outputs the ROM data read buffer 3, 6°RO.
Enable M test read signal generation circuit 9 and ROM test address generation circuit 1o.

Next, the operation of this embodiment will be explained.

When the ROM test signal 12 output from the ROM test signal generation circuit 8 becomes 1'' at time to, the ROM data read test state is entered.The ROM address generation circuits 2 and 5 normally operate independently, but It is reset to OII at the moment it enters the test state, and thereafter it is incremented at the same timing. ROM1# addressed by such ROM address generation circuits 2 and 5
and 4, data at address O is simultaneously read out after precharging (precharge period Tp) and held in ROM data read buffers 3 and 6, respectively.

Next, the ROM from the ROM test address generation circuit 10
The ROM data read buffers 3 and 6 are alternately selected by the test address signal 14, and a ROM test read signal 13 is generated from the ROM test read 4nR generation circuit 9.
are sequentially output, the ROM data read buffer 3.
The data in ROM 1.4 held at
．． ..., t5, ..., the data at address O of ROMI, then the data at address O of ROM4, and then R
The data at address 1 of OM1, the data at address 1 of ROM4, etc. are held in order and output to the outside of the LSI.

FIG. 3 is a block diagram of a second embodiment of the ROM read test circuit of the present invention.

The wood flow side is a composite RO consisting of ROM16+ and 162
This is a test circuit for M16. Although ROM161 and 162 hold different data, their capacity is small and the area of the peripheral control circuit is larger than that of ROM16+ and 16z, respectively, so these two ROM1
6+, 162 are combined into one composite ROM 16, and the peripheral control circuit is shared. ROM address generation circuit 1
7 is reset when the ROM test signal 12 is input, outputs an address signal that increments at the same predetermined timing to the composite ROM 16, and reads data from the ROv 161 and the ROM 162 in parallel. The read data is selected by the ROM data switching circuit 18 at the timing of the ROM test read signal and held in one ROM data read buffer. One ROM data read buffer is read-controlled by the ROM test read signal 13 output from the ROM test read signal generation circuit 9, chip-selected by the ROM test address generation circuit 10, and the held data is transferred onto the internal data bus 15. is read out.

Note that in the first and second embodiments, the case where there are two ROMs is shown, but the more ROMs there are, the more
It is clear that reading data from M simultaneously in parallel increases the effect of shortening test time. Further, by sharing the ROM test: sale signal 13 and the ROM test address signal 14 with the ROM read signal and the ROM address signal signal erlQ, which are used at times other than testing, it is possible to reduce wiring.

(Effects of the Invention) As explained above, the present invention reads data from a plurality of ROMs in parallel, selects each piece of data read out in parallel, and outputs it onto an internal data bus. This has the effect of shortening the ROM read test time.

[Brief explanation of drawings]

1 and 3 are block diagrams of the first and second embodiments of the ROM read test circuit of the present invention, respectively.
1 is a timing diagram showing the operation of the circuit shown in FIG. 1, and FIG. 4 is a block diagram of a conventional example of a ROMa output test circuit. 1.4.16+, 162...ROM, 2.5.17
...ROM address generation circuit, 3.6.19...R
OM data read buffer, 7... Instruction control circuit, 8... R, OM test signal generation circuit, 9... ROM
Test read signal generation circuit, 10... ROM test address generation circuit, 11... Data bus buffer, 12... ROM test signal, 13... ROM test output signal, 14... ROM test address signal , 15... Internal data bus, 16... Complex ROM, 18... ROM data switching circuit. “ゝ”141 Susumu Uchihara・1′V□,,,H,. Figure 1 Figure 3

Claims (1)

[Scope of Claims] 1. A ROM address generation circuit that is provided for each ROM, is reset when a ROM test signal is input, and outputs an address signal incremented from the first address at a predetermined same timing to the ROM; A ROM data read buffer that holds data read from the ROM and outputs it to the data bus, and a ROM test read signal that reads the data of each ROM at the same address held in the ROM data read buffer. a ROM test read signal generation circuit that outputs to each ROM data read buffer; a ROM test address generation circuit that outputs a selection control signal for selecting the ROM data read buffer to each ROM data read buffer; A test signal is output to an external circuit, a ROM address generation circuit, a ROM data read buffer, a ROM test read signal generation circuit, and a ROM test address generation circuit to prohibit access to the ROM by the external circuit, and a ROM data read buffer. A ROM read test circuit having a ROM test read signal generation circuit and a ROM test signal generation circuit that enables a ROM test address generation circuit. 2. Each R of a composite ROM composed of multiple ROMs
A ROM address generation circuit that is provided in common to the OM and is reset when a ROM test signal is input and gives the same address to all ROMs at the same time, and a ROM address generation circuit that inputs a ROM test read signal as a selection signal and reads out from each ROM in parallel. Select the data and press R
The ROM data switching circuit outputs data for each OM, and the output of the ROM data switching circuit is input and held, and the ROM
A ROM data read buffer that outputs held data to the data bus when a test read signal is input, and a ROM test read signal that reads data held in the ROM data read buffer is output to the ROM data read buffer and ROM data switching circuit. A ROM test read signal generation circuit outputs a ROM test signal to an external circuit, a ROM address generation circuit, a ROM data read buffer, and a ROM test read signal generation circuit to prohibit access to the ROM by external circuits. A ROM read test circuit having a data read buffer and a ROM test signal generation circuit that enables a ROM test read signal generation circuit.