JPH02208722A - Pseudo fifo memory - Google Patents

Abstract

PURPOSE:To artificially realize the FIFO of a large capacity by using a large capacity RAM by constituting this FIFO memory so that data written from an input data bus is read out of an output data bus in the order of write without executing an address control from the outside. CONSTITUTION:As for a read-out address, since a read-out pulse signal RD inputted to a terminal 22 is inputted to a read-out address counter 14 through an AND gate 16, this read-out address counter 14 is counted up automatically, and data can be read out of a new address at any time. In such a manner, data can be read out successively from a random access memory 6. Accordingly, the FIFO of a large capacity can be realized artificially and easily by using a large capacity RAM being on the market.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Minute Hand] The present invention relates to a digital semiconductor memory, and particularly to a synchronized FIFO memory which has a delay in propagation time and is capable of increasing its capacity.

[Conventional technology]

Conventionally, this type of FIFO memory does not have addresses and uses serially arranged memories, and the data written from the input data bus is propagated serially from the first stage memory cells, and the data is transferred to the last stage memory cells. The structure was such that it was read out from the output data bus.

[Problem to be solved by the invention]

When the conventional FIFO memory described above is increased in capacity by increasing the number of memory cells, the time required to propagate data from the first stage to the final version cannot be ignored, making it difficult to do so in practice.

Additionally, an additional circuit is required for each memory cell to transfer data to the next stage, and as capacity increases, the amount of circuitry increases, so commercially available random access memory (RAM)
Since it is difficult to increase the capacity to the same level as the above using the same design rules, there is a drawback that it is not possible to realize a large capacity F'IFO mesori on a realistic circuit scale.

[Means to solve the problem]

The pseudo F'IFO memory according to the present invention uses a random access memory, and includes an address controller that independently controls write addresses and read addresses to the random access memory, and a bus that separates into an input data bus and an output data bus. The data written to the input data path are read out to the output data bus in the order in which they were written, without external address control.

[Effect]

This invention uses a commercially available large-capacity RAM to create a large-capacity FRAM.
'IFO can be easily realized in a pseudo manner.

〔Example〕

The figure is a block diagram showing an embodiment of a pseudo FIFO memory according to the present invention. In the figure, 1 is a terminal to which the Full signal is output, 2 is a terminal to which the chip select signal C8w is input, and 3 is data D! D is the input terminal, 4 is the input terminal for the write pulse signal WR, sit is the AND gate, 6 is the random access memory IJ (RAM), and 7 is the input terminal.
A data bus controller section comprising three-state bus gates 8a and 8b, 9 a selector, 10 an adder, 11 and 12 comparators, 13 a write address counter, 14 a read address counter, 1
5 and 16 are AND gates, 17 is a terminal where the gnpty signal is output, 18 is a terminal where the R/mouth signal is input, 1
9 is a terminal to which the chip selector signal C8m is input, 20 is a terminal to which the Wal signal is output, and 21 is a data Dot.
+t is the output terminal, 22 is the read pulse signal ktD
This is the terminal where the signal is input.

Note that 23 is the selector 9. Adder 10° Comparators 11 and 12. Write address counter 13.
A read address counter 14 is an address controller section consisting of AND gates 15 and 16.

Next, the operation of the pseudo FIFO memory having the above configuration will be explained. First, when writing data DIN, chip select signal C8W is applied to terminal 2, and data D! is applied to terminal 3. When a write pulse signal is applied to terminal 4,
Data prs is from terminal 3 to three stealth l'r'-48
The data is written to the random access memory 6 via m.

The write address at this time is output from the write address counter 13 and input to the address terminal A (1xAn) of the random access memory 6 via the selector 9.

As for this write address, the write pulse signal WR input to the terminal 4 is input to the write address counter 13 via the AND gate 15, so the write address counter 13 is automatically counted up and data can be written to a new address at any time. Can be done. Also, while writing this data DIN, the chip select signal C8
w generates a Wait signal to the reading system to notify the writing operation. In this way, the data Dx
s are sequentially written into the random access memory 6. At this time, the write address output from the write address counter 13 is added to the adder 10 by +1 (+1).
be done. Therefore, the comparator 11 is this plus one
(+1) The write address and the read address from the read address counter 14 are compared, and the difference is 0. That is, when a match occurs, the Fυ11 signal is output from the terminal 1, notifying that there is no remaining area in the random access memory 6, and closing the memory area 15 to prohibit writing. Next, when reading data, when a chip selector signal C8R is applied to the terminal 19 and a read pulse signal RD is applied to the terminal 22, the data D out read from the random access memory 6 becomes the three speed pass game) 8b. It is output from the terminal 21 via.

The read address at this time is output from the read address counter 14 and input to address terminals ALI to An of the random access memory 6 via the selector 9.

This read address is determined by the read pulse signal RD input to the terminal 22, which is applied to the read address counter 14 through the AND gate 16, so that the read address counter 14 is automatically counted up, and from time to time the read pulse signal RD input to the terminal 22 is applied to the read address counter 14. Data can be read.

In this way, data is sequentially read from the random access memory 6. At this time, the comparator 12 compares the write address value outputted from the write address counter 13 and the read address value outputted from the read address counter 14, and when the difference is O2, that is, they match, the terminal 17 color 4p ty flaw signal is output. and notifies that there is no remaining data to be read from the random access memory 6, and closes the AND gate 16 to prohibit reading. Through the above operation, the data written from the terminal 3 is transferred to the terminal 21 as data DOUT.
It can be read as .

〔Effect of the invention〕

As explained in detail above, the pseudo FI according to the present invention
According to FO memory, by controlling the address bus and data bus of a commercially available random access memory (RAM) using an address controller and a bus controller, data committed from an input data bus can be transferred. jlii sworn from the output data bus without propagation! I can get started. This results in
By using a commercially available large-capacity FIFO, pseudo-fishing can be easily realized. Moreover, since no data is propagated, there is an effect that no propagation time delay (data delay time) occurs due to increased capacity.

[Brief explanation of the drawing]

The figure is a block diagram showing one embodiment of a pseudo FIFO memory according to the present invention. 1 to 4...terminal, 5...-and gate 6...
・Random access memory (RAM), 7...Data bus controller section, $a and 13b...
・Three-state Hasgate, 9...-Selector, 1
0...Adder, 11 and 12...Comparator, 13...-Write address counter, 14...
-Read address counter, 15 and 16-...
・AND gate, 17-22...terminal, 23...
・Address controller section.

Claims (1)

[Claims] Using random access memory, it is equipped with an address controller that independently controls the write address and read address to this random access memory, and a bus controller that separates the input data bus and output data bus, without external address control. , a pseudo FIFO characterized in that data written from an input data bus is read from an output data bus in the order in which they were written.
memory.