JPS5945699A - Ic memory testing device - Google Patents

Abstract

PURPOSE:To obtain an IC memory testing device of simple constitution which has a less unnecessary part and good efficiency, by switching and using a combined counter/register circuit. CONSTITUTION:When the input part 12 of an IC memory testing device is operated according to the kind of an IC memory 2 to be tested, a multiplexer selection signal is generated by a control part 11a according to the program in a storage part 13a. Then, a combined corresponding counter/register circuit 17 is selected and switched by the program; the address generated by a counter and data buffered in a register are outputted and a test of the memory 2 is taken without using two systems, i.e. the counter and the register. Therefore, the efficient IC memory testing device of the simple constitution which have such a less unnecessary part that one system halts is obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to improvements in address control and data control circuitry in an IC memory testing device 4.

(bl) Technology background IC memory is becoming increasingly diverse with the development of semiconductor technology, especially #-, and integration technology, and with the increase in capacity of IC memory.

In order to cope with the growing demand, it is expected that the equipment required for testing IC memory will become more diverse.

IcI Prior Art and Problems Figure 1 shows a block diagram of a conventional IC system. In the figure, 1 is the test drive device, 2 is the IC of the test object
Memo II (MUT), 1 t is a control section, 12 is an input section, 13 storage sections, 14 a, b, c are counters, r and 1.
5a and 5h are registers. Control unit 111d input unit 12
The memory section 13 (not shown) contains a plurality of test programs and test patterns, and addresses are inputted one by one according to the test programs designated by the input section 12. Data by selected test pattern? Send MIJT:? For example, take a light reading test.

The address data 77 and pattern data of Kone, et al. are sent via the data bus and money. Therefore, the exam IJ [ha84
Corresponding to U 'l' 2, τ is \ and C is 1.
+4t 24 'j'1'less e.g. 80 of MUT2
The γ address control IH number which selectively controls the column 1-address and the 16-column address is controlled by each counter 4a, b, cif.
j's callan-9u-do, no register 5a, b is 16
It is a half-french of 8 input data x 2 corresponding to the column address, and the test pattern is sent out and the data i is input into each address of ~1[JT2] by the address signal mentioned above.

The illustrated data control signals are chip select Bcs for each of the 17 registers 15a and 15h,
E), Outyople ((Monthly No. 15 r mark/Jll
In addition, the MUT2's reading code is received and compared with the test pattern to determine the pass/fail of the MU'l'2. In this θ), the conventional test equipment @1 has m address counters corresponding to the attribute [C] of PUT2's manual rliiA-to. ]~l1
1 and n data registers 15a and -n', separate installations were made for each, and the fabrication, testing, and adjustment were also carried out in 2
I was preparing for the series. The address counter and data register in this IC testing equipment are M
Is there a sufficient number to accommodate address and data input terminals with different combinations of element configurations in UT2? For example, if there is a memory IC with 20 address groups, 1 data line, 10 address lines, and 11 data lines, conventionally 20 address lines and 11 address lines are required. In many cases, it was a waste of effort to use idle strings.

fd+ OBJECTS OF THE INVENTION The purpose of the present invention is to eliminate the above-mentioned waste 7 by designing a test device for both address generation and data generation circuits, switching all of the dual-use circuits according to a selection signal from the control section, and at certain times switching between address and data generation circuits. The circuit is designed to function as a 6777 circuit for data, and to cover address and data line operations with as few drive circuits as possible.

Production, testing, and adjustment - A testing device that is efficient in all aspects due to its inability to function! <k> This is what we are trying to provide.

(el) Structure of the Invention The object of the present invention is to provide a test system for an IC memory according to the present invention. A memory section is provided to hold the test pattern, and while accessing the memory section, the test program or T- sends a selection signal to the selector according to the attribute of the input terminal using a separate input means. , the address control raI sent separately by the control unit.
'i Send a data control signal control signal port selection to the register/counter dual-use circuit and perform an operation test of an IC memory having an arbitrary input terminal attribute array 7? This can be achieved by providing a special IC memory testing device.

(fl Embodiment of the Invention The drawings will be explained in accordance with an embodiment of the present invention.

FIG. 2 is a complete diagram of an IC memory test circuit according to an embodiment of the invention. In the figure, 1a is the test@device,
2 is the IC Memo II (MIJT) to be tested,
11a i'jfII control section, 12-digit input section, 13a
16 is a selector (MPX) and 17
is a counter/register dual use circuit (C/R).

The control unit 11a ij accesses the storage unit 13 according to the operation from the input unit 12 as before. The storage unit 13 contains all the test programs and test patterns, and selects the test program 12 specified by the input unit 12 one by one and sends the data according to the test pattern to the MUT.
2 There is no difference in testing ffi j1 Now, should each input terminal of MUT2 be used as address or data line? Since all the data to be selected is required, the storage unit 12
M corresponding to each test program held by
If the attribute data of the input terminal is included in accordance with the type of UT2, the control unit 11a controls the MPX according to the attribute data.
Selection signal 2MP) (sent to x6. MPX16 controller 11a separately sends signals such as counter load, counter full, counter count/subtraction, counter reset, etc. as i'L address control signal and as data control signal. Signals such as register load and register reset are applied to each MP according to the MPX selection signal mentioned above.
X16 sends an address control signal or a data control signal to the corresponding V I1.17, and C/R17y functions as an address counter or a data register. After that, as before, address data and data patterns according to the test pattern are sent to MUT2 through the data basketball, and the entire write is performed in the evening.
Receive all the read signals from UT2 and compare them with the test pattern.M
Perform all UTz pass/fail judgments.

Is the above the metal data of the input terminal? The value k obtained from the test program may be applied each time by operating the input section 12, or, if necessary, may be directly applied by manually operating the C/X selection signal for each MPX 16.

As described above, depending on the type of MUT2, if the control unit 11a selects 1til+1- as either the C/Rt7y address counter or data register function, any input terminal attribute array t-\i is set. (J.T.
It is possible to construct an ICC memory test-1 that can cover a wide range of issues.

[gl As described in detail, the present invention (unlike conventional circuits dedicated to address counters and data registers? Two systems each? Since it can be integrated by making them correspond each time, it is possible to construct an efficient test device with fewer counters and registers being left idle as in the past. By reducing the number of circuits in the system to one, the number of circuits is reduced.
Since 1° manufacturing, testing ε and adjustment only need to be carried out for a single circuit, it is also useful in terms of manufacturing costs.

[Brief explanation of the drawing]

Figure 1 is a block diagram of a conventional IC memory test, and Figure 2 is a block diagram of a conventional IC mesh test.
! FIG. 2 is a block diagram of a Goru IC memory testing device. In the figure, I and la are test equipment, 2 is an IC memory that is used for nuclear testing, and 11. lla is system (+'l1 part, 12i
Mairibu month yB, 13.13a is the storage part, j4a, b, c
i: Counters 15a and 15b have registers, 16 is a selector, and 0 and I7 are counter/register dual-use circuits.

Claims (1)

[Claims] IC memory test system KJ3, especially 1. daytime power means for the input terminal of the IC memory serving as the i test specimen;
Multiple register/counter dual-purpose circuits, selectors ε corresponding to the circuits, test patterns t,
The control unit is provided with ii + 2 phantom parts to hold, and the control unit accesses the storage unit Z), and the test program j is inputted by a separate input means. , : is an IC memory testing device which selects a data control signal i and sends it to the L7-register/counter dual-use circuit, and performs an operation test of an IC memory having an arbitrary input terminal attribute arrangement trr.