JPH0962617A - Conflict arbitration device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the throughput of an information processor by preferentially processing a request which is high in urgency. SOLUTION: A block load instruction recognition part once recognizing block load instructions from a plurality of arithmetic parts 8 generate a plurality of load requests; and an address generation part 2 generates the addresses of the load requests and a priority level generation part 4 generates the priority levels of the load requests respectively. The priority levels are carried about during access to a main storage part 9 and read out of respective banks to a conflict arbitration part 6. The conflict arbitration part 6 arbitrates the load requests with specific logic according to the priority levels and issues a crossbar control signal and a load data crossbar 7 sends the load data out to an arithmetic part 8 in response to the crossbar control signal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a contention arbitration device for data transfer between a plurality of memories and a plurality of arithmetic units, and more particularly, to the same when transmitting data from a plurality of banks of a main memory to a plurality of arithmetic units. The present invention relates to a contention arbitration device having a function of arbitrating contention that occurs between data heading for a computing device and allowing high-priority data to pass first.

[0002]

2. Description of the Related Art FIG. 4 shows an example of a conventional competitive arbitration device of this type.

In FIG. 4, a request from the arithmetic unit is input from seven request input ports 100 to 107. The input request is a 2-way selector 204
And is input to the 8-bit FF904. At this time, as the input request, it is assumed that a request is input from a port marked with a circle in the request presence / absence column in FIG. Therefore, the value of the 8-bit FF904 is "1110.
1111 ".

At the first clock, the contents of the 8-bit FF 904 are input to the 8-bit arbiter 601. The 8-bit arbiter 601 is a fixed-priority contention arbitration circuit. Assuming that the input port 100 has the highest priority, as a result of arbitration, the input port 10
A request of 0 is selected and "10000000" is output as the crossbar control signal. At the same time, the signal obtained by inverting the arbiter output signal by the inverter 702 and the output signal of the 8-bit FF904 are logically ANDed by the logical AND circuit 703 and output to the selector control circuit 900 as an arbitration result signal having the content “01101111”.

The selector control circuit 402 receives this arbitration result signal, and outputs 8 arbitration result signals when the number of requests is 1 or more (that is, when the arbitration result signals are all other than "0").
The selector control signal is output so as to be output to the bit FF904. If the arbitration result signal is other than all "0", an ON hold signal is sent to the main memory. The 2-way selector 204 receives the selector control signal, selects the arbitration control signal, and inputs it to the 8-bit FF 904. Through the series of operations described above, the arbitration result signal “011
01111 "is set.

At the second clock, the request of the request input port 101 is selected according to the result of the above-mentioned arbitration and is output as the crossbar control signal. At the same time, the arbitration result signal having the content “00101111” is input to the 8-bit FF904. In this case, the arbitration result signal becomes “00101111” due to the same process as in the first clock, and since it is not all “0”, the selector control circuit 900 outputs an ON hold signal.

In the first clock, the same operation as in the second clock is performed after the third clock, and the request of the request input port 102 is made in the third clock and the request of the request input port 104 is made in the fourth clock.
The request from the request input port 105 is at the 5th clock, and the request input port 106 is at the 6th clock.
In the 7th clock, the request from the request input port 107 is selected as a result of the arbitration. At the 7th clock, the last request for the input port 107 is selected, and at the same time, the content is "0000000".
The selector control circuit 402, which has received the arbitration result signal of 0 ″, releases the hold signal sent to the main memory unit and receives a new request. As a result of the above series of operations, FIG. The requests are processed in the order shown in the contention arbitration output rank column.

[0008]

In the conventional contention arbitration apparatus described above, the priority order between contention requests is determined by the circuit configuration of the contention arbitration circuit. In addition to such contention arbitration apparatus, contention arbitration apparatus is also provided. There is also a method of changing the priority order by switching a circuit of a part to a circuit having a different priority order, but in any case, there is no method of preferentially processing arbitrary data.

[0009]

The apparatus of the present invention comprises one or more arithmetic units each of which can operate independently, a main memory unit having a plurality of banks which can operate in parallel, the arithmetic unit and the above-mentioned arithmetic unit. In the vector data processing device capable of performing a plurality of data transfers in parallel with the main memory unit, the data transfer contention arbitration device receives the instruction sent from the arithmetic unit and recognizes the block load instruction. Block load instruction recognition unit for generating a plurality of load requests, an address generation unit for generating an address for the generated load requests, and a priority for generating a priority level for the plurality of load requests In the order of the level generation unit and the generated priority level circulated to access the bank by the generated address, A contention arbitration unit that arbitrates contention of load requests and outputs a crossbar control signal, and a load data crossbar that receives the crossbar control signal, selects data read from the bank, and sends the selected data to the arithmetic unit It is characterized by

[0010]

Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention, in which a block load instruction recognition unit 1, an address generation unit 2,
Address crossbar 3, priority level generation unit 4, priority level crossbar 5, contention arbitration unit 6, and load data crossbar 7
Consists of

The block load request issued from the arithmetic unit 8 is input to the block load instruction recognition unit 1.
When the block load instruction recognition unit 1 recognizes the block load instruction, the address generation unit 2 and the priority level generation unit 4
Send instructions to When the address generator 2 receives the instruction, it generates as many addresses as the number of banks in the main memory 9 and sends them to the address crossbar 3. The priority level generation unit 4
According to an instruction from the block load recognition unit 1, a priority order is generated for each request and sent to the priority level crossbar 5.
The address crossbar 3 sends the load address to the request destination bank port, and the priority level crossbar 5 also sends the priority level to the request destination bank port.

The main memory 9 receives the load address and the priority level and reads the load data. At this time, the priority level is held and sent together with the load data as one request. The competition arbitration unit 6 includes the main storage unit 9
Receives the priority level signal of the request sent from each bank, arbitrates the competition between the banks, determines the highest priority bank, and sends the crossbar control signal to the load data crossbar 7. When the request remains in the contention arbitration unit 6, the hold signal is sent to the main storage unit 9 as "1", and the main storage unit 9 responds to the hold signal "1" in response to the contention arbitration unit 6 described above. To stop sending to. The load data crossbar 7 receives the crossbar control signal sent from the contention arbitration unit 6, selects the load data of the bank indicated by the crossbar control signal from the load data sent from each bank, and the arithmetic unit 8 Send to.

Next, this embodiment will be described in detail with reference to the detailed diagram of the contention arbitration unit 6 shown in FIG.

FIG. 2 has eight request input ports,
This is an example of a contention arbitration unit 6 that adopts a priority order determination method having four priority levels, including eight request input ports 100 to 107 and four two-way selectors 200 to 2.
03, four 8-bit OR circuits 300 to 303, selector control circuit 400, 32-bit OR circuit 401, 4-way selector for arbiter input 500, 8-bit arbiter 600, inverter 700, AND circuit 701, four FF inputs 2 way selectors 800-803 and four 8-bit FFs 900-903.

Now, the 8-bit FFs 900 to 903 are "a".
When the value is "ll0", "0" is output from the 32-bit OR circuit 401 and sent as a hold signal to the main memory unit 9. When the main memory unit 9 receives the hold signal having the content "0", A priority level signal is sent from each of the eight banks forming the storage unit 9 to the competition arbitration unit 6.
The request input ports 100-107 receive this priority level signal. The priority level signal is composed of 4 bits, and the order of priority is "1000" and "010".
It is one of four patterns of "0", "0010", and "0001", and when the priority level signal is "0000", there is no request.

The received priority level signal is supplied to the 2-way selectors 200 to 203, and the 2-way selector 2
00 is the leftmost bit of the request input ports 100 to 107, 2 way selector 201 is the 2nd bit from the left of each port, 2 way selector 202 is the 3rd bit from the left of each port, 2 way selector Two
The rightmost bit is input to 03. These 2-way selectors 200-203 select and output the signals from the request input ports 100-107 if the hold signal is "0", and select the signals of the 8-bit FFs 900-903 if they are "1".

The 8-bit OR circuits 300 to 303 have 2
The outputs of the way selectors 200 to 203 are ORed and sent to the selector control circuit 400. Selector control circuit 40
0 inputs the outputs of the 8-bit OR circuits 300 to 303 and outputs a 4-way selector control signal for arbiter control.
At this time, if the output of the 8-bit OR circuit 300 is "1", the control signal "1000" for selecting the output of the 2-way selector 200 is set to 8 when the output of the 8-bit OR circuit 300 is "0". Output of bit OR circuit 301 is "1"
If so, the control signal "0100" for selecting the output of the 2-way selector 201 is output to the 8-bit OR circuit 300.
If the outputs of 0 and 301 are "0" and the output of the 8-bit OR circuit 302 is "1", the control signal "0010" for selecting the output of the 2-way selector 202 is set to the 8-bit OR circuits 300 and 301. If the outputs of 0 and 302 are "0" and the output of the 8-bit OR circuit 303 is "1", the control signal "000" for selecting the output of the 2-way selector 203
1 ", respectively, and the selector control circuit 40.
The arbiter input 4-way selector control signal output from 0 is also used as a control signal for the FF input 2-way selectors 800 to 803.

4-way selector 500 for arbiter input
Receives the above-mentioned 4-way selector control signal for arbiter input outputted from the selector control circuit 400, selects one of the output signals of the 2-way selectors 200 to 203, and outputs it to the 8-bit arbiter 600. The 8-bit arbiter 600 performs arbitration according to a predetermined priority order and outputs the result as a slobar control signal. The priority may be fixed or rotary. The inverter 700 inverts the output of the 8-bit arbiter 600 and outputs it to the AND circuit 701,
The AND circuit 701 is a 4-way selector 5 for arbiter input.
00 and the output of the inverter 700 are ANDed and output to the FF input 2-way selectors 800 to 803. The 2-way selectors 800-803 for FF input are
In response to the 4-way selector control signal for arbiter input output from the selector control circuit 400, the outputs of the 2-way selectors 200 to 203 or the AND circuit 701 are selected and output to the 8-bit FFs 900 to 903.

At this time, the leftmost bit of the 4 bits of the 4-way selector control signal for arbiter input is the control signal of the 2-way selector 800 for FF input, and the second bit from the left of the 4 bits is the control signal. In the control signal of the selector 801, the third bit from the left is the control signal of the selector 802, and the rightmost bit is the control signal of the selector 803. As the selection condition of the selectors 800 to 803, if the selection signal is “0”, the 2-way selectors 200 to 203 are selected.
If the selection signal is "1", the output of the AND circuit 701 is selected. If the contents of the 8-bit FFs 900 to 903 are not "all0", the 32-bit OR circuit 401
Output becomes "1" and 2-way selectors 200-2
03 selects the output signals of the 8-bit FFs 900 to 903.

Next, this embodiment will be described in more detail with reference to specific examples of priority level signals sent from the eight banks of the main memory 9. FIG. 3A shows a specific example of the priority level signals received by the request input ports 100 to 107 and the priority order of the priority level signals. FIG. Figure 3 when there is no
The state where the priority level signal of (a) is received is clock 1
Shows the internal state up to clock 8.

The operation of the contention arbitration unit 6 will be described below with reference to FIG.

Now, when the contents of the 8-bit FFs 900 to 903 are "all0" and there is no request, and the hold signal is "0", the main memory 9 requests the request input ports 100 to 107 of the contention arbitration unit 6. To Figure 3
It is assumed that the priority level signal shown in (a) is input.
The 2-way selectors 200 to 203 have the request input port 1 because the hold signal which is the control signal is “0”.
The signal from 00 to 107 is selected, and the signal of 200 in FIG.
A signal like the column of output to output 203 is output. At this time, the outputs of the 8-bit OR circuits 300 to 303 are "11".
11 ".

The selector control circuit 400 receives the outputs of the 8-bit OR circuits 300 to 303 and outputs the 4-way selector control signal for arbiter input. At this time, the output of the 8-bit OR circuit 300 is "1". An arbiter input 4-way selector control signal "1000" for selecting the output of the 2-way selector 200 is output. Receiving the 4-way selector control signal "1000" for arbiter input, the output "000010" of the 2-way selector 200
00 "is selected and output to the 8-bit arbiter 600.
At this time, the output of the 8-bit arbiter 600 is "00001."
000 ”and the output of the inverter 700 is“ 1111 ”.
0111 ”, and the output of the AND circuit 701 is“ 000 ”.
It becomes 00000 ".

2-way selector for FF input 800 to 80
Since only the control signal of the selector 800 among the control signals of 3 is “1”, the 2-way selector 800 for FF input is used.
Only selects the output “00000000” of the AND circuit 701, and the other 2-way selectors 801 to 80 for FF input.
3 selects the outputs of the 2-way selectors 201 to 203. As a result of clock 1, the 8-bit FFs 900 to 903 have "00000000" and "00100000", respectively.
Values of 0 "," 00000101 ", and" 11000010 "are entered.

At clock 2, the hold signal is "1". 2-way selectors 200-203 are 8-bit FF9
Select the output from 00 to 903. 8-bit OR circuit 3
Since the output of 00 is "0" and the output of the 8-bit OR circuit 301 is "1", the 4-way selector control signal for arbiter input output from the selector control circuit 400 is "010".
Therefore, the output “0010000” of the 2-way selector 201 is input to the 8-bit arbiter 600. The output of the 8-bit arbiter 600 is “001000”.
00 ”, the output of the AND circuit 701 is“ 0000000 ”.
The output signal of the selector control circuit 400 is “0”.
Since it is 100 ", only the 2-way selector for FF input 801 selects the output of the AND circuit 701. As a result of the clock 2, the 8-bit FFs 900 to 903 have" 000 "respectively.
"00000", "00000000", "000001"
The values "01" and "11000010" are entered.

At clock 3, the hold signal is "1". 2-way selectors 200-203 are 8-bit FF9
Select the output from 00 to 903. Since the outputs of the AND circuits 300 and 301 are “0” and the output of the AND circuit 302 is “1”, the 4-way selector control signal for arbiter input output from the selector control circuit 400 is “001”.
Therefore, the output “000000101” of the 2-way selector 202 is input to the 8-bit arbiter 600. The output of the 8-bit arbiter 600 is “000001”.
00 ", the output of the inverter 700 is" 1111101 ".
1 ", the output of the AND circuit 701 is" 00000001 "
Becomes The output signal of the selector control circuit 400 is “001
Since it is 0 ″, only the 2-way selector for FF input 802 selects the output of the AND circuit 701. As a result of the clock 3,
The 8-bit FFs 900 to 903 have "00000" respectively.
000 "," 00000000 "," 0000000 "
The values "1" and "11000010" are entered.

At clock 4, the hold signal is "1". 2-way selectors 200-203 are 8-bit FF9
Select the output from 00 to 903. 8-bit OR circuit 3
The outputs of 00 and 301 are “0”, and the 8-bit OR circuit 3
Since the output of 02 is "1", the arbiter input 4-way selector control signal output from the selector control circuit 400 is "0010". Therefore, 8-bit arbiter 600
The output of the 2-way selector 202 is “0000000”.
1 ”is input. The output of the 8-bit arbiter 600 is“ 00000001 ”and the output of the AND circuit 701 is“ 00000000. ”Selector control circuit 400
Since the output signal of is "0010", only the 2-way selector for FF input 802 selects the output of the AND circuit 701. As a result of the clock 4, the 8-bit FFs 900 to 903 have "00000000" and "0000000", respectively.
Values of 0 ”,“ 00000000 ”, and“ 11000010 ”are entered.

At clock 5, the hold signal is "1". 2-way selectors 200-203 are 8-bit FF9
Select the output from 00 to 903. 8-bit OR circuit 3
Since the outputs of 00, 301 and 302 are "0" and the output of the 8-bit OR circuit 303 is "1", the 4-way selector control signal for arbiter input output from the selector control circuit 400 is "0001". Therefore, the 8-bit arbiter 600 outputs "1100" from the 2-way selector 203.
0010 ”is input. The output of the 8-bit arbiter 600 is“ 10000000 ”, the output of the inverter 700 is“ 01111111 ”, and the output of the AND circuit 701 is“ 01000010 ”.
Since the output signal of is "0001", only the 2-way selector for FF input 803 selects the output of the AND circuit 701. As a result of the clock 5, the 8-bit FFs 900 to 903 have “00000000” and “0000000”, respectively.
Values of 0 ”,“ 00000000 ”, and“ 01000010 ”are entered.

In the clock 6, the hold signal is "1", and the arbiter input 4 output from the selector control circuit 400 is input.
The way selector control signal is "0001". The output “01000010” of the 2-way selector 203 is input to the 8-bit arbiter 600. The output of the 8-bit arbiter 600 is “01000000”, and the inverter 70
The output of 0 is “10111111” and the output of the AND circuit 701 is “00000010”. Since the output of the selector control circuit 400 is “0001”, only the 2-way selector for FF input 803 selects the output of the AND circuit 701. As a result of clock 6, 8-bit FF900 to 90
3 is "00000000" and "000000", respectively.
00 ”,“ 00000000 ”,“ 00000010 ”
Enter the value of.

In the clock 7, the hold signal is "1", and the arbiter input 4 output from the selector control circuit 400.
The way selector control signal is "0001". The bit arbiter 600 outputs “0” to the 2-way selector 203.
0000010 "is input. 8-bit arbiter 60
The output of 0 is “00000010”, the output of the inverter 700 is “11111101”, and the output of the AND circuit 701 is “00000000”. Selector control circuit 40
Since the output of 0 is "0001", only the 2-way selector for FF input 803 selects the output of the AND circuit 701. As a result of the clock 7, the 8-bit FFs 900 to 903 have "00000000" and "0000000", respectively.
Values of 0 ”,“ 00000000 ”and“ 00000000 ”are entered.

The processing of the first request group has been completed.

At clock 8, the hold signal becomes "0", and a new request group is sent from the main memory unit 9.

FIG. 3 (c) shows a comparison of the request output order between the contention arbitration apparatus of the present invention and the conventional contention arbitration apparatus. It can be seen that, in the conventional example, the data of the request input port 103 that wants the load data earliest is output fourth, whereas in the configuration of the present invention, the data is output first.

[0035]

As described above, according to the present invention, when a load request is issued from the arithmetic unit, a request from the main storage unit is requested to the arithmetic unit by adding a high priority to a request requiring a prompt reply. Even if a conflict occurs when the process returns, the required request is preferentially processed, and the processing efficiency of the entire information processing apparatus can be improved.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a competitive arbitration device of the present invention.

FIG. 2 is a detailed diagram of a contention arbitration unit shown in FIG.

FIG. 3 is a diagram for explaining an operation in this embodiment and a conventional method.

FIG. 4 is a block diagram showing a configuration of a conventional example.

[Explanation of symbols]

 1 block load instruction recognition unit 2 address generation unit 3 address crossbar 4 priority level generation unit 5 priority level crossbar 6 contention arbitration unit 7 load data crossbar 8 arithmetic unit 9 main storage unit 100 to 107 request input port 200 to 204 2 way selector 300 -303 8-bit OR circuit 400,402 Selector control circuit 401 32-bit OR circuit 500 4-way selector for arbiter input 600-601 8-bit arbiter 700,702 Inverter 701,703 AND circuit 800-803 2-way for FF input Selector 900 to 904 8-bit FF

Claims (2)

[Claims] 1. A plurality of arithmetic units, each of which can operate independently, a main memory unit having a plurality of banks that can operate in parallel, and a plurality of memory units arranged in parallel between the arithmetic units and the main memory unit. A contention arbitration device for data transfer in a vector data processing device capable of performing data transfer of a block for receiving a command sent from the operation unit, recognizing a block load command, and generating a plurality of load requests A load instruction recognition unit, an address generation unit that generates an address for the plurality of generated load requests, a priority level generation unit that generates a priority level for the plurality of load requests, and the generated addresses Arbitrate the contention of the load request in the order of the generated priority levels carried around to access the bank And a load data crossbar for receiving the crossbar control signal and selecting the data read from the bank and sending the selected data to the arithmetic unit. Arbitration device. 2. The contention arbitration unit accepts a flip-flop that holds the presence / absence of a load request corresponding to the priority level and the output of the flip-flop unless all of the flip-flops are empty. A two-way selector corresponding to the priority level that accepts a load request from a bank, an arbiter input selector that selects one of the two way selectors based on the priority level, and a predetermined output for the arbiter input selector. 2. The contention arbitration apparatus according to claim 1, further comprising: an arbiter that generates the crossbar control signal according to logic, and a means that updates the flip-flop by the crossbar control signal.