JPS63284864A - Manufacture of insulated-gate field-effect transistor - Google Patents
Manufacture of insulated-gate field-effect transistorInfo
- Publication number
- JPS63284864A JPS63284864A JP11954087A JP11954087A JPS63284864A JP S63284864 A JPS63284864 A JP S63284864A JP 11954087 A JP11954087 A JP 11954087A JP 11954087 A JP11954087 A JP 11954087A JP S63284864 A JPS63284864 A JP S63284864A
- Authority
- JP
- Japan
- Prior art keywords
- oxide film
- gate oxide
- epitaxial growth
- substrate
- forming
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 6
- 230000005669 field effect Effects 0.000 title claims description 3
- 239000000758 substrate Substances 0.000 claims abstract description 20
- 239000012535 impurity Substances 0.000 claims abstract description 16
- 238000005229 chemical vapour deposition Methods 0.000 claims description 2
- 238000000034 method Methods 0.000 abstract description 8
- 238000009792 diffusion process Methods 0.000 abstract description 6
- 239000007789 gas Substances 0.000 abstract description 6
- GQPLMRYTRLFLPF-UHFFFAOYSA-N Nitrous Oxide Chemical compound [O-][N+]#N GQPLMRYTRLFLPF-UHFFFAOYSA-N 0.000 abstract description 4
- MROCJMGDEKINLD-UHFFFAOYSA-N dichlorosilane Chemical compound Cl[SiH2]Cl MROCJMGDEKINLD-UHFFFAOYSA-N 0.000 abstract description 2
- 239000000463 material Substances 0.000 abstract description 2
- 229960001730 nitrous oxide Drugs 0.000 abstract 1
- 235000013842 nitrous oxide Nutrition 0.000 abstract 1
- 239000010408 film Substances 0.000 description 13
- 230000003647 oxidation Effects 0.000 description 4
- 238000007254 oxidation reaction Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 239000013078 crystal Substances 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000009826 distribution Methods 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 239000010409 thin film Substances 0.000 description 2
- 241000282693 Cercopithecidae Species 0.000 description 1
- 101100081489 Drosophila melanogaster Obp83a gene Proteins 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000002109 crystal growth method Methods 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 1
- 239000002052 molecular layer Substances 0.000 description 1
- 239000001272 nitrous oxide Substances 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、高速かつ低消費電力で動作し超ＬＳＩなどの
基本素子として用いられる絶縁ゲート電界効果トランジ
スタ（以下、ＭＯＳＦＥＴと略す）の製造方法に関する
。[Detailed Description of the Invention] [Field of Industrial Application] The present invention provides a method for manufacturing an insulated gate field effect transistor (hereinafter abbreviated as MOSFET), which operates at high speed and with low power consumption and is used as a basic element of VLSI etc. Regarding.
近年、分子線エピタキシャル成長法（以下、ＭＢＥと略
す）や分子層エピタキシャル成長法（以下ＭＬＥと略す
）による結晶成長技術の進歩によって、低温において単
原子層の精度で単結晶薄膜を形成できるようになってき
た。例えばＭＢＨについては、応用物理、第５１巻、第
８号（１９８２）Ｐ、９３８〜Ｐ、９４１において、ま
たＭＬＥについては、例えば、Ｓｅｍ１ｃｏｎｄｕｃｔ
ｏｒ Ｈｏ１ｄ １９８５．１．Ｐ、１３５〜Ｐ、１４
０において報告されている。本発明は、上述の結晶成長
法を用いて高濃度基板上に低温でエピタキシャル成長を
行うことにより低不純物濃度のチャネル領域を形成する
とともに、ＣＶＤ法を用いてゲート酸化膜形成時の基板
温度を低くすることにより、高濃度基板からチャネル領
域への不純物の拡散を防止している。これにより、耐ラ
ンチアップ性に優れ、短チヤネル効果防止に有効で、か
つ移動度の高いデバイス構造を実現できる。In recent years, advances in crystal growth technology using molecular beam epitaxial growth (hereinafter referred to as MBE) and molecular layer epitaxial growth (hereinafter referred to as MLE) have made it possible to form single-crystal thin films with the precision of a single atomic layer at low temperatures. Ta. For example, regarding MBH, see Applied Physics, Vol. 51, No. 8 (1982) P, 938-P, 941, and regarding MLE, e.g.
orHold 1985.1. P, 135-P, 14
Reported in 0. The present invention forms a channel region with a low impurity concentration by performing epitaxial growth on a high concentration substrate at a low temperature using the above-mentioned crystal growth method, and also lowers the substrate temperature when forming a gate oxide film using a CVD method. This prevents impurities from diffusing from the highly doped substrate to the channel region. This makes it possible to realize a device structure that has excellent launch-up resistance, is effective in preventing short channel effects, and has high mobility.
従来は、ＭＢＥあるいはＭＬＥを用いて、高濃度基板上
に低濃度のエピタキシャル成長層を形成してチャネル領
域とした後に、熱酸化法を用いてゲート酸化膜を形成し
ていた。Conventionally, a low concentration epitaxial growth layer was formed on a high concentration substrate using MBE or MLE to form a channel region, and then a gate oxide film was formed using a thermal oxidation method.
不純物純度がＩ ＸＩＯ”ｃｍ−’の高濃度基板上に約
１０００人の膜厚を有するエピタキシャル成長層を例え
ばＭＢＥ法を用いて、例えば基板温度８５０℃で形成し
た場合の不純物濃度分布は、第３図の曲線ａのようにな
る。When an epitaxial growth layer having a thickness of about 1,000 layers is formed on a highly concentrated substrate with an impurity purity of I It will look like curve a in the figure.
尚、第３図において横軸Ｘは、エピタキシャル成長層表
面をＯとして深さ方向を正にとっている。In FIG. 3, the horizontal axis X takes the surface of the epitaxial growth layer as O, and the depth direction is positive.
しかし、ゲート酸化膜を熱酸化法を用いて例えば、１０
００℃、 ｌＱｍｉｎ、という条件で約３００人形成し
た後のエピタキシャル成長層の不純物濃度分布は、基板
からの不純物拡散のために、第３図の曲線すのようにな
る。このため、チャネル領域の不純物濃度が高くなって
しまい、実効的に移動変が低下するという問題があった
。However, if the gate oxide film is formed using a thermal oxidation method, for example,
The impurity concentration distribution of the epitaxial growth layer after approximately 300 layers were formed under the conditions of 00° C. and lQmin becomes as shown in the curve in FIG. 3 due to impurity diffusion from the substrate. As a result, the impurity concentration in the channel region becomes high, resulting in a problem that the transfer variation is effectively reduced.
本発明は、ＭＯＳ Ｆ ＥＴのゲート酸化膜形成時に、
従来から用いられてきた熱酸化法は用いないで、ＣＶＤ
法を用いることにより、チャネル領域を形成した時のエ
ピタキシャル成長温度よりも低い温度においてゲート酸
化膜を形成し、高濃度基板からの不純物のチャネル領域
への拡散を防止し、チャネル領域の不純物濃度を低く保
ち、高移動度を実現している。In the present invention, when forming a gate oxide film of a MOS FET,
CVD does not use the conventional thermal oxidation method.
By using this method, the gate oxide film is formed at a temperature lower than the epitaxial growth temperature when forming the channel region, preventing the diffusion of impurities from the high concentration substrate into the channel region, and lowering the impurity concentration in the channel region. and achieves high mobility.
以下、実施例に基づいて本発明の詳細な説明する。第１
図ｆ８） 〜ｆｃ）は、本発明によるＭＯＳＦＥＴの製
造工程順断面図である。８５０℃以下の基板温度におい
て第１図１ｂｌで示すような高濃度基板１の上に形成さ
れた低濃度エピタキシャル成長層２の上に、エピタキシ
ャル成長温度よりも低い温度においてゲート酸化膜３を
形成するには、以下のような方法を用いる。即ち１．第
１図ｆａ）でエピタキシャル成長Ｎ２を形成した後、ホ
ットウォール型の減圧ＣＶＤ装置内に基板をセントする
。ゲート酸化膜３形成のための材料ガスにジクロルシラ
ン（ＳｉＨｚＣ！□）及び亜酸化窒素（ＮｚＯ）を用い
て、例えば基板温度を８５０℃に保ち、ガス圧力、ガス
流量などを最適条件に設定することにより、良好な酸化
膜を得ることができる。このようにして第１図１ｂｌに
示すようにゲート酸化膜３を形成すれば、従来の熱酸化
法を用いて酸化膜を形成していた際に生じる高濃度基板
１から低濃度エピタキシャル成長層２への不純物の拡散
を無視できる程度に抑えることができ、第２図に示すよ
うな不純物濃度の低いチャネル領域を高濃度基板上に設
けることができる。Hereinafter, the present invention will be described in detail based on Examples. 1st
Figures f8) to fc) are cross-sectional views in the order of manufacturing steps of the MOSFET according to the present invention. To form a gate oxide film 3 at a temperature lower than the epitaxial growth temperature on a low concentration epitaxial growth layer 2 formed on a high concentration substrate 1 as shown in FIG. 1 1bl at a substrate temperature of 850° C. or less , using the following method. Namely 1. After epitaxial growth N2 is formed in FIG. 1fa), the substrate is placed in a hot wall type low pressure CVD apparatus. Dichlorosilane (SiHzC!□) and nitrous oxide (NzO) are used as material gases for forming the gate oxide film 3, and the substrate temperature is maintained at, for example, 850° C., and the gas pressure, gas flow rate, etc. are set to optimal conditions. Accordingly, a good oxide film can be obtained. If the gate oxide film 3 is formed in this manner as shown in FIG. The diffusion of impurities can be suppressed to a negligible level, and a channel region with a low impurity concentration as shown in FIG. 2 can be provided on a highly doped substrate.
尚、第２図において横軸Ｘはエピタキシャル成長層表面
を０として深さ方向を正にとっている。In FIG. 2, the horizontal axis X takes the surface of the epitaxial growth layer as 0 and the depth direction as positive.
この後、第１図中）に示すように、多結晶シリコンを堆
積してゲート５とし、ゲート５のパターニング終了後、
第１図（Ｃ１に示すようにイオン注入法を用いてソース
６及びドレイン７を形成している。After this, as shown in FIG. 1), polycrystalline silicon is deposited to form the gate 5, and after patterning of the gate 5,
As shown in FIG. 1 (C1), the source 6 and drain 7 are formed using the ion implantation method.
以上のように、本発明によれば、高濃度基板上に形成し
た低濃度エピタキシャル成長薄膜層をチャネル領域とし
て用いるに際して、ゲート酸化膜形成時における不純物
の基板からチャネル領域への拡散を防止している。この
ためゲートＭ化膜形成後でもチャネル領域の不純物濃度
を十分低くすることができる。従って、本発明によるＭ
ＯＳＦＥＴは高速動作を特徴とする。更に、耐ラツチア
ツプ性や短チヤネル効果防止のうえで優れている。As described above, according to the present invention, when a low concentration epitaxially grown thin film layer formed on a high concentration substrate is used as a channel region, diffusion of impurities from the substrate to the channel region during gate oxide film formation is prevented. . Therefore, even after forming the gate M film, the impurity concentration in the channel region can be made sufficiently low. Therefore, M according to the present invention
OSFETs are characterized by high speed operation. Furthermore, it is excellent in terms of latch resistance and prevention of short channel effects.
第１図（ａｌ 〜（Ｃ１は、本発明によるＭＯＳＦＥＴ
（７）製造工程順断面図、第２図は、本発明によるＭＯ
ＳＦＥＴのチャネル領域における不純物濃度分布図、第
３図は１、ゲート酸化膜を熱酸化法により形成した従来
のＭＯＳＦＥＴのチャネル領域における不純物濃度の変
化を示す図である。
■・・・高濃度基板
２・・・エピタキシャル成長層
３・・・ゲート酸化膜
４・・・多結晶シリコン ５・・・ゲート６・・・ソー
ス ７・・・ドレイン以上
出願人 セイコー電子工業株式会社
本１６Ｉ！月１日ろＭＯＳＦＥＴの製表１才隻１１頁断
光図、本、ｉａｌ’（Ｉて ＝ｔ ６ Ｍ ＯＳ Ｆ
ＥＴＶ）＋ＪＩＬＡｆｔ％て′のｌ統牛功濃簾４Ｎ申
１目FIG. 1 (al ~ (C1 is a MOSFET according to the present invention)
(7) A cross-sectional view of the manufacturing process, FIG. 2 shows the MO according to the present invention.
FIG. 3 is a diagram showing the impurity concentration distribution in the channel region of a conventional MOSFET in which a gate oxide film is formed by thermal oxidation. ■...High concentration substrate 2...Epitaxial growth layer 3...Gate oxide film 4...Polycrystalline silicon 5...Gate 6...Source 7...Drain and above Applicant Seiko Electronics Industries, Ltd. Book 16I! Monthly MOSFET manufacturing table 11 pages cross section diagram, book, ial'(Ite =t 6 M OS F
ETV) + JILAft%te' l togyukonoren 4N Monkey 1
Claims (1)
濃度の低いエピタキシャル成長層を形成してチャネルと
した後に、ＣＶＤ法を用いてエピタキシャル成長温度よ
りも低い温度で前記エピタキシャル成長層の上にゲート
酸化膜を形成することを特徴とする絶縁ゲート電界効果
トランジスタの製造方法。After forming an epitaxial growth layer with a low impurity concentration on a high concentration substrate to form a channel at a substrate temperature of 850° C. or lower, a gate oxide film is formed on the epitaxial growth layer using a CVD method at a temperature lower than the epitaxial growth temperature. A method of manufacturing an insulated gate field effect transistor, characterized by:
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11954087A JPS63284864A (en) | 1987-05-15 | 1987-05-15 | Manufacture of insulated-gate field-effect transistor |
| EP88303695A EP0289246A1 (en) | 1987-04-27 | 1988-04-25 | Method of manufacturing MOS devices |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11954087A JPS63284864A (en) | 1987-05-15 | 1987-05-15 | Manufacture of insulated-gate field-effect transistor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63284864A true JPS63284864A (en) | 1988-11-22 |
Family
ID=14763817
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11954087A Pending JPS63284864A (en) | 1987-04-27 | 1987-05-15 | Manufacture of insulated-gate field-effect transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63284864A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100228330B1 (en) * | 1995-12-29 | 1999-11-01 | 김영환 | Mosfet device and a manufacturing method thereof |
-
1987
- 1987-05-15 JP JP11954087A patent/JPS63284864A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100228330B1 (en) * | 1995-12-29 | 1999-11-01 | 김영환 | Mosfet device and a manufacturing method thereof |
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