KR100228330B1 - Mosfet device and a manufacturing method thereof - Google Patents
Mosfet device and a manufacturing method thereof Download PDFInfo
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- KR100228330B1 KR100228330B1 KR1019950064535A KR19950064535A KR100228330B1 KR 100228330 B1 KR100228330 B1 KR 100228330B1 KR 1019950064535 A KR1019950064535 A KR 1019950064535A KR 19950064535 A KR19950064535 A KR 19950064535A KR 100228330 B1 KR100228330 B1 KR 100228330B1
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 10
- 239000000758 substrate Substances 0.000 claims abstract description 20
- 239000004065 semiconductor Substances 0.000 claims abstract description 19
- 239000012535 impurity Substances 0.000 claims abstract description 7
- 238000000059 patterning Methods 0.000 claims abstract description 4
- 238000000407 epitaxy Methods 0.000 claims description 17
- 238000000034 method Methods 0.000 claims description 12
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 5
- 229910052796 boron Inorganic materials 0.000 claims description 5
- 238000010438 heat treatment Methods 0.000 claims description 3
- 238000007669 thermal treatment Methods 0.000 claims 1
- 230000000694 effects Effects 0.000 abstract description 6
- 230000007704 transition Effects 0.000 description 4
- 238000009792 diffusion process Methods 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 238000004151 rapid thermal annealing Methods 0.000 description 2
- 125000006850 spacer group Chemical group 0.000 description 2
- 230000005540 biological transmission Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02293—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process formation of epitaxial layers by a deposition process
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823412—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823418—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
Abstract
본 발명은 반도체소자 및 그 제조방법에 관한 것으로, 숏채널 효과를 억제하고 면저항을 감소시키기 위한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, to suppress short channel effects and reduce sheet resistance.
이를 위해 본 발명은 반도체기판상에 에피택시층을 형성하는 단계와, 상기 에피택시층상에 게이트산화막과 게이트 형성용 도전층을 차례로 형성하는 단계, 상기 도전층과 게이트산화막 및 에피택시층을 소정의 게이트패턴으로 패터닝하여 게이트를 형성하는 단계, 및 기판에 기판과 반대도전형의 불순물을 이온주입하고 RTA처리를 행하여 소오스 및 드레인영역을 형성하는 단계를 포함하여 이루어지는 것을 특징으로 하는 반도체소자 제조방법을 제공한다.To this end, the present invention comprises forming an epitaxial layer on a semiconductor substrate, sequentially forming a gate oxide film and a gate forming conductive layer on the epitaxial layer, and forming the conductive layer, the gate oxide film, and the epitaxial layer. Forming a gate by patterning the gate pattern; and implanting impurities of opposite conductivity type to the substrate and performing RTA treatment to form a source and a drain region. to provide.
Description
제1(a)도 내지 제1(d)도는 본 발명의 실시예에 따른 모스펫 소자 제조 공정 단면도.1 (a) to 1 (d) is a cross-sectional view of the MOSFET device manufacturing process according to an embodiment of the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
1 : 반도체기판 2 : 필드산화막1: semiconductor substrate 2: field oxide film
3 : 에피택시층 4 : 게이트산화막3: epitaxy layer 4: gate oxide film
5 : 게이트 6 : 스페이서5: gate 6: spacer
7 : 소오스 및 드레인영역 8 : 선택 에피택시층7 source and drain regions 8 select epitaxy layer
본 발명은 반도체소자 및 그 제조방법에 관한 것으로, 특히 숏채널 효과(short channel effect)를 억제하고 면저항(sheet resistance)을 감소시킬 수 있는 MOSFET 및 이의 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a MOSFET capable of suppressing short channel effects and reducing sheet resistance, and a method of manufacturing the same.
종래의 MOSFET 제조방법은 소자의 집적도가 높아짐에 따라 게이트 산화막의 두께가 얇아져 보론(boron) 투과 등으로 야기되는 문턱전압 천이 현상, 이동도의 저하 및 숏채널 효과 등의 문제를 내포하고 있다.Conventional MOSFET fabrication methods have problems with threshold voltage transitions, mobility degradation, and short channel effects caused by boron permeation, as the gate oxide film becomes thinner as the device density increases.
이와 같은 문제를 해결하기 위해 본 발명은 게이트 산화막 하부에 채널 에피택시층을 형성하고 차후에 급속열처리(RTA, rapid thermal annealing) 공정을 진행하여 일종의 채널 스토퍼(channel stopper) 역할을 할 수 있도록 함으로써, 즉 기판으로부터 게이트 산화막으로 불순물이 확산되는 것을 억제하여 문턱전압 천이를 방지하고 숏채널 효과를 방지할 수 있는 MOSFET 및 이의 제조방법을 제공하는데 그 목적이 있다.In order to solve this problem, the present invention forms a channel epitaxy layer under the gate oxide layer, and then performs a rapid thermal annealing (RTA) process to act as a channel stopper. It is an object of the present invention to provide a MOSFET and a method of manufacturing the same, which can prevent diffusion of impurities from a substrate into a gate oxide film, thereby preventing a threshold voltage transition and preventing a short channel effect.
상기 목적을 달성하기 위한 본 발명은, 반도체 기판; 상기 반도체 기판에 형성된 소오스 및 드레인; 상기 소오스 및 드레인 사이의 상기 반도체 기판에 형성된 채널영역; 상기 반도체 기판 상에 형성되어 상기 채널영역과 접하는 에피택시층; 상기 에피택시층 상에 형성된 게이트 산화막; 및 상기 게이트 산화막 상에 형성된 게이트를 포함하는 모스펫 소자를 제공한다.The present invention for achieving the above object, a semiconductor substrate; A source and a drain formed on the semiconductor substrate; A channel region formed in the semiconductor substrate between the source and the drain; An epitaxial layer formed on the semiconductor substrate and in contact with the channel region; A gate oxide film formed on the epitaxy layer; And it provides a MOSFET device comprising a gate formed on the gate oxide film.
또한, 상기 목적을 달성하기 위한 본 발명은 반도체 기판 상에 에피택시층을 형성하는 제1단계; 상기 에피택시층 상에 게이트산화막 및 게이트 형성용 도전층을 차례로 형성하는 제2단계; 상기 도전층, 상기 게이트 산화막 및 상기 에피택시층을 패터닝하여 게이트 패턴을 형성하는 제3단계; 및 상기 반도체 기판에 상기 반도체 기판과 반대 도전형의 불순물을 이온주입하고 급속열처리를 실시하여 소오스 및 드레인을 형성하는 제4단계를 포함하는 모스펫 소자 제조방법을 제공한다.In addition, the present invention for achieving the above object is a first step of forming an epitaxy layer on a semiconductor substrate; A second step of sequentially forming a gate oxide film and a gate forming conductive layer on the epitaxy layer; Forming a gate pattern by patterning the conductive layer, the gate oxide layer, and the epitaxy layer; And a fourth step of ion implanting impurities of opposite conductivity type to the semiconductor substrate and performing rapid heat treatment to form a source and a drain.
이하, 첨부된 도면을 참조하여 본 발명을 상세히 설명한다.Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.
제1(a)도 내지 제1(d)도에 본 발명의 실시예에 의한 MOSFET 제조방법을 공정순서에 따라 도시하였다.1 (a) to 1 (d) show a MOSFET manufacturing method according to an embodiment of the present invention according to the process sequence.
먼저, 제1(a)도에 도시된 바와 같이 필드산화막(2)에 의해 소자분리영역과 액티브 영역으로 구분된 p형 반도체 기판(1)의 액티브영역 상부에 UHV-CVD(Ultra High VAcuum Chemical Vapor Deposition)을 이용하여 보론이 도핑된 에피택시층(3)을 300Å정도의 두께로 형성한다. 이때, 보론의 농도는 1×1018㎝-3정도로 유지되도록 한다.First, as shown in FIG. 1 (a), UHV-CVD (Ultra High VAcuum Chemical Vapor) is formed on the active region of the p-type semiconductor substrate 1 divided into the device isolation region and the active region by the field oxide film 2. Deposition) to form a boron-doped epitaxy layer 3 to a thickness of about 300 kPa. At this time, the concentration of boron is maintained to about 1 × 10 18 cm -3 .
다음에 제1(b)도에 도시된 바와 같이 상기 에피택시층(3)상에 게이트 산화막(4)을 약 50Å정도의 두께로 형성하고, 게이트 산화막(4) 상에 게이트 형성용 도전층으로서, 예컨대 폴리실리콘층(5)을 형성한 후, 폴리실리콘층(5)과 게이트산화막(4) 및 에피택시층(3)을 사진식각공정을 통해 소정의 게이트 패턴으로 패터닝하여 게이트를 형성한다. 이때, 상기 에피택시층(3)은 채널 영역 상에 형성되어 결과적으로 얇은 매립 채널을 형성함으로써 보론 투과로 야기되는 문턱전압의 천이 및 숏채널 효과를 방지할 수 있게 된다. 이때, 에피택시층(3)의 두께는 두꺼울수록 효과적인데 (소자의 집적도에 따라 두께가 조정되어야 한다), 그 이유는 두께가 얇은 경우 높은 수직 전계(high electric field)에 기인하는 캐리어 이동도의 저하를 초래하게 되기 때문이다.Next, as shown in FIG. 1 (b), a gate oxide film 4 is formed on the epitaxial layer 3 to a thickness of about 50 GPa, and a gate forming conductive layer on the gate oxide film 4 is formed. For example, after the polysilicon layer 5 is formed, the gate is formed by patterning the polysilicon layer 5, the gate oxide film 4, and the epitaxy layer 3 into a predetermined gate pattern through a photolithography process. At this time, the epitaxy layer 3 is formed on the channel region, thereby forming a thin buried channel, thereby preventing the transition of the threshold voltage and the short channel effect caused by boron transmission. At this time, the thickness of the epitaxy layer 3 is more effective (the thickness should be adjusted according to the degree of integration of the device), because the thickness of the carrier mobility due to the high electric field is high when the thickness is thin. This is because it causes a decrease.
이어서 제1(c)도에 도시된 바와 같이 n형 불순물로서, As를 저농도로 이온주입한 후, 기판 전면에 절연층으로서 예컨대 LTO(low temperature oxide)를 증착하고 이를 에치백하여 게이트 측면에 스페이서(6)를 형성한다. 이어서, n형 불순물을 고농도로 이온주입한 후, 1050℃의 온도로 약 10초간 급속열처리를 실시하여 LDD(Lightly doped drain) 구조의 소오스 및 드레인영역(7)을 형성함으로써 MOSFET제조공정을 완료한다.Subsequently, as shown in FIG. 1 (c), as an n-type impurity, As is ion-implanted at a low concentration, a low temperature oxide (LTO), for example, is deposited as an insulating layer on the front surface of the substrate and etched back to form a spacer on the gate side. (6) is formed. Subsequently, after ion implantation with high concentration of n-type impurities, rapid heat treatment is performed at a temperature of 1050 ° C. for about 10 seconds to form a source and drain region 7 having a lightly doped drain (LDD) structure, thereby completing the MOSFET manufacturing process. .
한편, 상기 공정후 제1(d)도에 도시된 바와 같이 게이트(5)와 소오스 및 드레인영역(7) 표면상에 선택적 성장법으로 에피택시층(8)을 형성할 수도 있다. 이와 같이 선택적 성장법으로 에피택시층(8)을 형성함으로써 그후 상기 에피택시층(8)상에 Ti 살리사이드(salicide)를 형성할 경우 면저항을 감소시킬 수 있게 된다.On the other hand, as shown in FIG. 1 (d) after the above process, the epitaxial layer 8 may be formed on the surface of the gate 5 and the source and drain regions 7 by a selective growth method. By forming the epitaxial layer 8 by the selective growth method as described above, when Ti salicide is formed on the epitaxial layer 8, the sheet resistance can be reduced.
이상 상술한 바와 같이 본 발명에 의하면, 기판으로부터 게이트 산화막으로 불순물이 확산되는 것을 억제하여 MOSFET에 있어서의 숏채널 효과를 억제할 수 있고, 문턱전압의 천이를 방지할 수 있으며, Ti 살리사이드의 면저항을 감소시킬 수 있게 된다.As described above, according to the present invention, the diffusion of impurities from the substrate into the gate oxide film can be suppressed, so that the short channel effect in the MOSFET can be suppressed, the transition of the threshold voltage can be prevented, and the sheet resistance of Ti salicide Can be reduced.
이상에서 설명한 본 발명은 전술한 실시예 및 첨부된 도면에 의해 한정되는 것이 아니고, 본 발명의 기술적 사상을 벗어나지 않는 범위 내에서 여러 가지 치환, 변형 및 변경이 가능함이 본 발명이 속하는 기술분야에서 통상의 지식을 가진자에게 있어 명백할 것이다.The present invention described above is not limited to the above-described embodiment and the accompanying drawings, and various substitutions, modifications, and changes are possible in the art without departing from the technical spirit of the present invention. It will be evident to those who have knowledge of.
Claims (7)
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| KR1019950064535A KR100228330B1 (en) | 1995-12-29 | 1995-12-29 | Mosfet device and a manufacturing method thereof |
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| KR1019950064535A KR100228330B1 (en) | 1995-12-29 | 1995-12-29 | Mosfet device and a manufacturing method thereof |
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| KR100228330B1 true KR100228330B1 (en) | 1999-11-01 |
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|---|---|
| KR (1) | KR100228330B1 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100498592B1 (en) * | 1997-12-27 | 2006-04-28 | 주식회사 하이닉스반도체 | Most transistors and manufacturing method thereof |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63269577A (en) * | 1987-04-27 | 1988-11-07 | Seiko Instr & Electronics Ltd | Manufacture of insulated-gate field-effect transistor |
| JPS63284864A (en) * | 1987-05-15 | 1988-11-22 | Seiko Instr & Electronics Ltd | Manufacture of insulated-gate field-effect transistor |
-
1995
- 1995-12-29 KR KR1019950064535A patent/KR100228330B1/en not_active IP Right Cessation
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63269577A (en) * | 1987-04-27 | 1988-11-07 | Seiko Instr & Electronics Ltd | Manufacture of insulated-gate field-effect transistor |
| JPS63284864A (en) * | 1987-05-15 | 1988-11-22 | Seiko Instr & Electronics Ltd | Manufacture of insulated-gate field-effect transistor |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100498592B1 (en) * | 1997-12-27 | 2006-04-28 | 주식회사 하이닉스반도체 | Most transistors and manufacturing method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| KR970054435A (en) | 1997-07-31 |
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