KR20020045263A - Method of manufacturing a transistor in a semiconductor device - Google Patents
Method of manufacturing a transistor in a semiconductor device Download PDFInfo
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- KR20020045263A KR20020045263A KR1020000074647A KR20000074647A KR20020045263A KR 20020045263 A KR20020045263 A KR 20020045263A KR 1020000074647 A KR1020000074647 A KR 1020000074647A KR 20000074647 A KR20000074647 A KR 20000074647A KR 20020045263 A KR20020045263 A KR 20020045263A
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- boron
- polysilicon
- nitrogen
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- transistor
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 19
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 15
- IJGRMHOSHXDMSA-UHFFFAOYSA-N nitrogen Substances N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims abstract description 58
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 55
- 229920005591 polysilicon Polymers 0.000 claims abstract description 53
- 229910052796 boron Inorganic materials 0.000 claims abstract description 38
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims abstract description 35
- 229910052757 nitrogen Inorganic materials 0.000 claims abstract description 30
- 238000000034 method Methods 0.000 claims abstract description 17
- 238000009792 diffusion process Methods 0.000 claims abstract description 10
- 125000006850 spacer group Chemical group 0.000 claims abstract description 5
- 239000000758 substrate Substances 0.000 claims abstract description 5
- 229910052732 germanium Inorganic materials 0.000 claims description 33
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims description 33
- 239000007789 gas Substances 0.000 claims description 24
- 238000005468 ion implantation Methods 0.000 claims description 12
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims description 11
- 239000012535 impurity Substances 0.000 claims description 10
- 238000004518 low pressure chemical vapour deposition Methods 0.000 claims description 9
- 238000009825 accumulation Methods 0.000 claims description 5
- 238000001289 rapid thermal chemical vapour deposition Methods 0.000 claims description 5
- 238000000038 ultrahigh vacuum chemical vapour deposition Methods 0.000 claims description 5
- 238000010438 heat treatment Methods 0.000 claims description 4
- 229910052710 silicon Inorganic materials 0.000 claims description 4
- 239000010703 silicon Substances 0.000 claims description 4
- 238000011066 ex-situ storage Methods 0.000 claims description 3
- 238000011065 in-situ storage Methods 0.000 claims description 3
- 238000000059 patterning Methods 0.000 claims description 2
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 claims 1
- 238000001505 atmospheric-pressure chemical vapour deposition Methods 0.000 claims 1
- 239000007943 implant Substances 0.000 claims 1
- -1 boron ions Chemical class 0.000 abstract 5
- 229910000577 Silicon-germanium Inorganic materials 0.000 abstract 3
- AHKZTVQIVOEVFO-UHFFFAOYSA-N oxide(2-) Chemical compound [O-2] AHKZTVQIVOEVFO-UHFFFAOYSA-N 0.000 abstract 2
- 238000000137 annealing Methods 0.000 abstract 1
- 230000035515 penetration Effects 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 230000000903 blocking effect Effects 0.000 description 3
- 150000001638 boron Chemical class 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 239000007772 electrode material Substances 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 230000006911 nucleation Effects 0.000 description 1
- 238000010899 nucleation Methods 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 230000000704 physical effect Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28158—Making the insulator
- H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
- H01L21/28176—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation with a treatment, e.g. annealing, after the formation of the definitive gate conductor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
Abstract
Description
본 발명은 반도체 소자의 트랜지스터 제조 방법에 관한 것으로, 특히 폴리 실리콘 저마늄층으로 이루어진 게이트 전극을 형성하는 반도체 소자의 트랜지스터제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a transistor manufacturing method of a semiconductor device, and more particularly, to a transistor manufacturing method of a semiconductor device for forming a gate electrode made of a polysilicon germanium layer.
현재 반도체 소자 제조 방법 중 게이트 전극 재료로 사용되는 폴리실리콘은 게이트 재료로서 우수한 물리적 특성을 갖추고 있어서 현재까지 가장 많이 사용되고 있지만, 소자가 점점 고직접화되는 상황에서 여러 가지 문제점이 대두되고 있는 실정이다. 예를 들어, 매몰 채널(Buried channel)에 기인한 짧은 채널 효과(Short channel effect)와 이로 인한 DIBL(Drain Induced Barrier Lowing) 현상 증가 및 문턱 전압 불안정 현상이 나타난다. 또한, 폴리게이트 공핍 효과(Poly gate depletion effect) 및 게이트 산화막을 통한 채널 영역으로의 보론 불순물 침투 현상으로 소자의 전기적 특성이 열화된다. 이와 같은 단점을 극복하기 위해 도입된 게이트 전극 중의 하나가 폴리실리콘에 저마늄(Ge) 함량을 대략 60%까지 추가한 폴리 실리콘 저마늄(Poly-SiGe)이다. 기발표된 문헌들을 통해 볼 때, 폴리-실리콘 저마늄이 기존 폴리실리콘에 비해 보론 확산을 더 억제시켜 그 침투 현상을 억제시키는 효과가 있다고 하나 여전히 적지 않은 보론 불순물이 하부로 침투하여 소자의 특성을 열화시킬 수 있다.Polysilicon, which is used as a gate electrode material in the current semiconductor device manufacturing method, has the most physical properties as a gate material, and is used the most until now. For example, short channel effects due to buried channels, resulting in increased DBL (Drain Induced Barrier Lowing), and threshold voltage instability. In addition, due to the poly gate depletion effect and the boron impurity penetration into the channel region through the gate oxide layer, electrical characteristics of the device are deteriorated. One of the gate electrodes introduced to overcome this drawback is poly-silicon germanium (Poly-SiGe), which adds about 60% germanium (Ge) to polysilicon. According to the published literatures, poly-silicon germanium is more effective than the existing polysilicon to suppress the diffusion of boron to suppress the penetration phenomenon, but still a small number of boron impurities penetrate the bottom to improve the characteristics of the device May deteriorate.
따라서, 본 발명은 상기의 문제점을 해결하기 위하여 게이트 전극을 폴리 실리콘 저마늄으로 형성하고, 보론 주입시 질소를 함께 주입하되 질소를 보론보다 더 깊이 주입하여 게이트 산화막 상부에 축적함으로써 폴리 실리콘 저마늄층에서 보론의 확산을 1차로 차단하고, 게이트 산화막 상부에 축적된 질소 성분으로 2차 차단함으로써 게이트 산화막을 통과해 채널 영역으로의 보론 침투 현상을 효과적으로 억제하여 소자의 전기적 특성을 향상시킬 수 있는 반도체 소자의 게이트 전극 방법에 관한 것이다.Therefore, in order to solve the above problems, the present invention forms a gate electrode made of polysilicon germanium, and injects nitrogen together during boron injection, but injects nitrogen deeper than boron to accumulate on the gate oxide layer in the polysilicon germanium layer. Blocking the diffusion of boron first and second blocking with nitrogen accumulated on the gate oxide layer effectively prevents the penetration of boron into the channel region through the gate oxide layer and improves the electrical characteristics of the device. It relates to a gate electrode method.
도 1a 내지 도 1d는 본 발명에 따른 반도체 소자의 트랜지스터 제조 방법을 설명하기 위하여 순차적으로 도시한 소자의 단면도.1A to 1D are cross-sectional views of devices sequentially shown in order to explain a transistor manufacturing method of a semiconductor device according to the present invention.
<도면의 주요 부분에 대한 부호 설명><Description of the symbols for the main parts of the drawings>
1 : 반도체 기판2 : 게이트 산화막1 semiconductor substrate 2 gate oxide film
3 : 폴리실리콘 시드층4 : 폴리 실리콘 저마늄층3: polysilicon seed layer 4: polysilicon germanium layer
5 : 질소 축적층34 : 게이트 전극5: nitrogen accumulation layer 34: gate electrode
6 : 게이트 스페이서7 : 소오스/드레인6: gate spacer 7: source / drain
본 발명에 따른 반도체 소자의 트랜지스터 제조 방법은 반도체 기판 상에 게이트 산화막 및 폴리실리콘 시드층을 형성하는 단계, 폴리실리콘 시드층 상에 폴리 실리콘 저마늄층을 형성하는 단계, 폴리 실리콘 저마늄층에 보론 및 질소를 이온 주입하되 질소를 보론보다 더 깊이 이온 주입하는 단계, 폴리 실리콘 저마늄층, 폴리실리콘 시드층 및 게이트 산화막을 패터닝하는 단계, 열처리를 실시하여 질소를 확산시켜 폴리실리콘 시드층과 게이트 산화막의 계면에 보론의 확산을 방지할 수 있는 질소 축적층을 형성하는 단계 및 게이트 스페이서 및 LDD 구조의 소오스/드레인을 형성하는 단계로 이루어진다.A transistor manufacturing method of a semiconductor device according to the present invention comprises the steps of forming a gate oxide film and a polysilicon seed layer on a semiconductor substrate, forming a polysilicon germanium layer on the polysilicon seed layer, boron and nitrogen in the polysilicon germanium layer Ion implantation, but implanting nitrogen deeper than boron, patterning the polysilicon germanium layer, polysilicon seed layer and gate oxide film, and performing heat treatment to diffuse nitrogen to interface the polysilicon seed layer with the gate oxide film. Forming a nitrogen accumulation layer capable of preventing diffusion of boron and forming a source / drain of the gate spacer and the LDD structure.
폴리실리콘 시드층은 550 내지 650℃의 온도에서 100 내지 500Å의 두께로 형성한다. 폴리 실리콘 저마늄층은 비정질(Amorphous) 또는 결정질(Crystalline) 상태로 증착하며, 450 내지 650℃의 온도와 5 내지 1,000mTorr의 압력에서 LPCVD(Low Pressure CVD), VLPCVD(Very Low Pressure CVD), PE-VLPCVD(Plasma Enhanced-Very Low Pressure CVD), UHVCVD(Ultra High Vacuum CVD), RTCVD(Rapid Thermal CVD) 또는 APCVD(Atmosphere Pressure CVD)법을 이용해 700 내지 2500Å두께로 증착한다. 이때, 폴리 실리콘 저마늄층의 저마늄 함량은 10 내지 70%가 되도록 하며, 수소 가스에 SiH4가 10 내지 100% 포함된 혼합 가스나 수소 가스에 Si2H6가 10 내지 100% 포함된 혼합 가스를 실리콘의 소오스 가스로 사용하고, 수소 가스에 GeH4가스가 1 내지 100% 포함된 혼합 가스 또는 수소 가스에 GeF4가 1 내지 100% 포함된 혼합 가스를 저마늄 소오스 가스로 사용하여 형성한다. 보론 이온 주입시 사용하는 보론 불순물로는 B11또는 BF2를 사용하며, 질소 이온 주입시 사용하는 질소로는 14N+또는 28N2 +를 사용한다. 보론 이온 주입은 보론 불순물 가스를 이용해 인-시투로 주입하거나, 이온 주입 공정을 이용한 익스-시투(Ex-situ) 방법으로 불순물을 주입할 수도 있다.The polysilicon seed layer is formed to a thickness of 100 to 500 kPa at a temperature of 550 to 650 ℃. The polysilicon germanium layer is deposited in an amorphous or crystalline state, and is a low pressure CVD (LPCVD), a very low pressure CVD (VLPCVD), a PE- at a temperature of 450 to 650 ° C. and a pressure of 5 to 1,000 mTorr. It is deposited at a thickness of 700 to 2500 kPa using Plasma Enhanced-Very Low Pressure CVD (VLPCVD), Ultra High Vacuum CVD (UHVCVD), Rapid Thermal CVD (RTCVD), or Atmosphere Pressure CVD (APCVD). At this time, the germanium content of the polysilicon germanium layer is 10 to 70%, and a mixed gas containing 10 to 100% of SiH 4 in hydrogen gas or a mixed gas containing 10 to 100% of Si 2 H 6 in hydrogen gas. the formed using a source gas of silicon, a mixed gas with a GeF 4 contains 1 to 100% of the GeH 4 gas contains 1 to 100% of the mixed gas or hydrogen gas to the hydrogen gas to a germanium source gas. B 11 or BF 2 is used as boron impurities used for boron ion implantation, and 14N + or 28N 2 + is used as nitrogen used for nitrogen ion implantation. Boron ion implantation may be implanted in-situ using boron impurity gas, or impurities may be implanted by an ex-situ method using an ion implantation process.
이하, 첨부된 도면을 참조하여 본 발명의 실시예를 더욱 상세히 설명하기로 한다.Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention in more detail.
도 1a 내지 도 1d는 본 발명에 따른 반도체 소자의 트랜지스터 제조 방법을 설명하기 위하여 순차적으로 도시한 소자의 단면도이다.1A to 1D are cross-sectional views of devices sequentially shown to explain a method of manufacturing a transistor of a semiconductor device according to the present invention.
도 1a를 참조하면, 반도체 기판(1) 상에 게이트 산화막(2)을 형성한 후 폴리실리콘 시드층(3)을 형성한다.Referring to FIG. 1A, after forming the gate oxide layer 2 on the semiconductor substrate 1, the polysilicon seed layer 3 is formed.
폴리실리콘 시드층(3)은 폴리 실리콘 저마늄을 게이트 산화막 상에 증착하기 전에, 증착막의 양호한 접착(Adhesion)과 원할한 핵생성(Nucleation)을 위하여 형성하며, 550 내지 650℃의 온도에서 100 내지 500Å의 두께로 형성한다.The polysilicon seed layer 3 is formed for good adhesion and smooth nucleation of the deposited film before depositing the polysilicon germanium on the gate oxide film, and it is 100 to 100 at a temperature of 550 to 650 ° C. It is formed to a thickness of 500Å.
도 1b를 참조하면, 폴리실리콘 시드층(3) 상에 폴리 실리콘 저마늄층(4)을 형성한다. 이후, 폴리 실리콘 저마늄층(4)과 폴리실리콘 시드층(3)에 질소와 보론을 연속하여 이온 주입하되 질소를 보론보다 더 깊이 이온 주입한다.Referring to FIG. 1B, a polysilicon germanium layer 4 is formed on the polysilicon seed layer 3. Subsequently, nitrogen and boron are continuously ion implanted into the polysilicon germanium layer 4 and the polysilicon seed layer 3, but nitrogen is ion implanted deeper than boron.
폴리 실리콘 저마늄층(4)은 비정질(Amorphous) 또는 결정질(Crystalline) 상태로 증착하며, 450 내지 650℃의 온도와 5 내지 1,000mTorr의 압력에서 LPCVD(Low Pressure CVD), VLPCVD(Very Low Pressure CVD), PE-VLPCVD(Plasma Enhanced-Very Low Pressure CVD), UHVCVD(Ultra High Vacuum CVD), RTCVD(Rapid Thermal CVD) 또는 APCVD(Atmosphere Pressure CVD)법을 이용해 700 내지 2500Å 두께로 증착한다. 이때, 폴리실리콘 저마늄층(4)의 저마늄 함량은 10 내지 70%가 되도록 한다. 폴리 실리콘 저마늄층(4) 증착 시 실리콘의 소오스 가스(Source Gas)로는 수소 가스(H2)에 SiH4가 10 내지 100% 포함된 혼합 가스나 수소 가스에 Si2H6가 10 내지 100% 포함된 혼합 가스를 사용한다. 저마늄 소오스 가스로는 수소 가스에 GeH4가스가 1 내지 100% 포함된 혼합 가스 또는 수소 가스에 GeF4가 1 내지 100% 포함된 혼합 가스를 사용한다.The polysilicon germanium layer 4 is deposited in an amorphous or crystalline state, and is a low pressure CVD (LPCVD) and a very low pressure CVD (VLPCVD) at a temperature of 450 to 650 ° C. and a pressure of 5 to 1,000 mTorr. It is deposited to a thickness of 700 to 2500 Pa by using Plasma Enhanced-Very Low Pressure CVD (PE-VLPCVD), Ultra High Vacuum CVD (UHVCVD), Rapid Thermal CVD (RTCVD), or Atmosphere Pressure CVD (APCVD). At this time, the germanium content of the polysilicon germanium layer 4 is set to 10 to 70%. Source gas of silicon during deposition of the polysilicon germanium layer 4 includes 10 to 100% of Si 2 H 6 in a mixed gas or hydrogen gas containing 10 to 100% of SiH 4 in hydrogen gas (H 2 ). Mixed gas is used. Germanium source gas is a mixed gas with a GeF 4 contains 1 to 100% of the GeH 4 gas is a mixed gas comprising 1 to 100% hydrogen gas or a hydrogen gas.
보론 이온 주입시 사용하는 보론 불순물로는 B11또는 BF2를 사용하며, 질소 이온 주입시 사용하는 질소로는 14N+또는 28N2 +를 사용한다. 이때, 보론 불순물은 불순물 가스를 이용해 인-시투(In-situ)로 주입할 수도 있고, 도펀트를 이온 주입공정을 이용한 익스-시투(Ex-situ) 방법으로 주입할 수도 있다.B 11 or BF 2 is used as boron impurities used for boron ion implantation, and 14N + or 28N 2 + is used as nitrogen used for nitrogen ion implantation. In this case, the boron impurities may be implanted in-situ using an impurity gas, or the dopant may be implanted by an ex-situ method using an ion implantation process.
도 1c를 참조하면, 식각 공정으로 폴리 실리콘 저마늄층(4), 폴리실리콘 시드층(3) 및 게이트 산화막을 패터닝하여 게이트 전극(34)을 형성한 후 산화 분위기에서 열처리를 실시하여 LDD 산화막(도시되지 않음)을 형성함과 동시에 보론을 활성화시키고, 폴리실리콘 시드층(3)과 게이트 산화막(2)의 계면에 질소 성분을 축적시켜 질소 축적층(5)을 형성한다.Referring to FIG. 1C, the polysilicon germanium layer 4, the polysilicon seed layer 3, and the gate oxide layer are patterned by an etching process to form a gate electrode 34, and then thermally treated in an oxidizing atmosphere to form an LDD oxide layer (not shown). And boron are activated, and a nitrogen component is accumulated at the interface between the polysilicon seed layer 3 and the gate oxide film 2 to form the nitrogen accumulation layer 5.
열처리에 의해 질소와 보론이 폴리 실리콘 저마늄층(4) 및 폴리실리콘 시드층(3)을 거쳐 하부의 게이트 산화막(2) 쪽으로 확산할 때, 보론은 폴리 실리콘 저마늄층(4)에서 확산이 억제된다.When nitrogen and boron diffuse through the polysilicon germanium layer 4 and the polysilicon seed layer 3 toward the lower gate oxide film 2 by the heat treatment, the boron is suppressed from diffusing in the polysilicon germanium layer 4. .
실리콘 내에서 질소의 확산계수(Diffusivity; 7.29E-13 cm2/sec)가 보론의 확산 계수(1.33E-13 cm2/sec)보다 대략 5배 크므로 질소가 폴리실리콘 시드층(3)을 통해 더 빨리 확산될 뿐만 아니라, 폴리실리콘 시드층(3)/게이트 산화막(2) 계면에 축적된다. 결국, 보론은 폴리 실리콘 저마늄층(4)에 의해 확산이 억제될 뿐만 아니라, 폴리실리콘 시드층(3)/게이트 산화막(2)의 계면에 축적(Pile-up)된 질소 성분에 의해, 다시 한번 확산이 차단됨으로 보론의 침투을 매우 효과적으로 억제할 수 있다. 또한, 질소 축적층(5)에 의해 보론의 확산에 억제될 때, 그 계면에는 전기적으로 활성화된 보론의 농도가 증가하게 됨으로 소자의 전기적 특성을 더욱 향상시킬 수 있다.The diffusion coefficient of nitrogen in the silicon (Diffusivity; 7.29E-13 cm 2 / sec) is the diffusion coefficient (1.33E-13 cm 2 / sec ) is approximately five times larger polysilicon seed layer (3) than the nitrogen to boron Not only do they diffuse faster, but also accumulate at the polysilicon seed layer 3 / gate oxide film 2 interface. As a result, boron is not only prevented from being diffused by the polysilicon germanium layer 4 but also once again by a nitrogen component accumulated at the interface of the polysilicon seed layer 3 / gate oxide film 2. By blocking diffusion, boron can be very effectively suppressed. In addition, when the boron is inhibited by diffusion of the nitrogen accumulation layer 5, the concentration of the electrically activated boron increases at the interface, it is possible to further improve the electrical characteristics of the device.
도 1d를 참조하면, 일반적으로 공지된 기술에 의해 게이트 전극스페이서(6), 소오스/드레인(7) 등을 형성하여 트랜지스터를 제조한다.Referring to FIG. 1D, a transistor is manufactured by forming a gate electrode spacer 6, a source / drain 7, and the like by a generally known technique.
상술한 바와 같이, 본 발명은 후속 열처리시 보론 침투 현상을 효과적으로 억제하고 폴리실리콘 시드층과 게이트 산화막 계면에서 전기적으로 활성화된 보론의 농도가 증가하여 소자의 전기적 특성 및 신뢰성을 향상시키는 효과가 있다.As described above, the present invention effectively suppresses boron penetration during subsequent heat treatment and increases the concentration of electrically activated boron at the polysilicon seed layer and the gate oxide layer, thereby improving electrical characteristics and reliability of the device.
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