KR20020002899A - Method for forming gate electrode of semiconductor device - Google Patents
Method for forming gate electrode of semiconductor device Download PDFInfo
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- KR20020002899A KR20020002899A KR1020000037263A KR20000037263A KR20020002899A KR 20020002899 A KR20020002899 A KR 20020002899A KR 1020000037263 A KR1020000037263 A KR 1020000037263A KR 20000037263 A KR20000037263 A KR 20000037263A KR 20020002899 A KR20020002899 A KR 20020002899A
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- silicon germanium
- dopant
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- 238000000034 method Methods 0.000 title claims abstract description 52
- 239000004065 semiconductor Substances 0.000 title claims abstract description 28
- 229910052732 germanium Inorganic materials 0.000 claims abstract description 39
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims abstract description 39
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 37
- 239000002019 doping agent Substances 0.000 claims abstract description 28
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 25
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 25
- 239000010703 silicon Substances 0.000 claims abstract description 25
- 239000000758 substrate Substances 0.000 claims abstract description 17
- 238000009792 diffusion process Methods 0.000 claims abstract description 12
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 claims abstract description 5
- 238000010438 heat treatment Methods 0.000 claims description 15
- 150000004767 nitrides Chemical class 0.000 claims description 10
- 230000004888 barrier function Effects 0.000 claims description 8
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims description 7
- 238000004518 low pressure chemical vapour deposition Methods 0.000 claims description 5
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims description 4
- 239000007789 gas Substances 0.000 claims description 4
- 239000012299 nitrogen atmosphere Substances 0.000 claims description 4
- 239000012298 atmosphere Substances 0.000 claims description 3
- 238000001451 molecular beam epitaxy Methods 0.000 claims description 3
- 238000001289 rapid thermal chemical vapour deposition Methods 0.000 claims description 3
- 238000000038 ultrahigh vacuum chemical vapour deposition Methods 0.000 claims description 3
- 239000001257 hydrogen Substances 0.000 claims description 2
- 229910052739 hydrogen Inorganic materials 0.000 claims description 2
- 238000011065 in-situ storage Methods 0.000 claims description 2
- 238000005468 ion implantation Methods 0.000 claims description 2
- 230000003064 anti-oxidating effect Effects 0.000 claims 1
- 238000001505 atmospheric-pressure chemical vapour deposition Methods 0.000 claims 1
- 229920005591 polysilicon Polymers 0.000 abstract description 5
- 230000035515 penetration Effects 0.000 abstract description 4
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 abstract description 3
- 229910001873 dinitrogen Inorganic materials 0.000 abstract 1
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 7
- 229910052796 boron Inorganic materials 0.000 description 7
- 230000000149 penetrating effect Effects 0.000 description 5
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000004913 activation Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000002542 deteriorative effect Effects 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 238000005121 nitriding Methods 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28158—Making the insulator
- H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
- H01L21/28176—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation with a treatment, e.g. annealing, after the formation of the definitive gate conductor
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28158—Making the insulator
- H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
- H01L21/28185—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation with a treatment, e.g. annealing, after the formation of the gate insulator and before the formation of the definitive gate conductor
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
Abstract
Description
본 발명은 반도체소자의 게이트전극 형성방법에 관한 것으로써, 보다 자세하게는 게이트전극 형성 시, 폴리-실리콘게르마늄막을 형성한 후, 이에 도펀트를 주입하고 열처리공정을 실시할 때 도펀트가 확산하면서 반도체기판에 침투하는 것을방지할 수 있는 확산방지막을 형성할 수 있도록 한 반도체소자의 게이트전극 형성방법에 관한 것이다.The present invention relates to a method for forming a gate electrode of a semiconductor device, and more particularly, to form a poly-silicon germanium film during the formation of a gate electrode, and then dopants are injected into the semiconductor substrate while the dopant is diffused during the heat treatment process. A method of forming a gate electrode of a semiconductor device capable of forming a diffusion barrier film that can prevent penetration.
디자인룰이 감소함에 따라 N+ 폴리게이트 PMOS의 경우 보론 카운터 도핑(Counter doping)에 의해 채널 길이가 짧아지는 짧은 채널 효과(Short channel effect)가 발생하고 이로 인해 문턱전압이 불안정하고 누설전류가 증가되는 문제점이 발생하여 매몰채널(Buried channel) PMOS 트랜지스터 특성을 개선할 필요성이 제기되었다.As the design rule decreases, N + polygate PMOS causes short channel effect that shortens the channel length by boron counter doping, which causes the threshold voltage to be unstable and the leakage current increases. This has led to the need to improve the characteristics of buried channel PMOS transistors.
그래서, 이를 해결하기 위해 소자의 축소가 가능하고 낮은 전압에서도 안정적으로 사용할 수 있는 이중게이트 전극(Dual gate electrode)을 연구 개발하게 되었다.Therefore, in order to solve this problem, the researcher has developed a dual gate electrode which can reduce the size of the device and can be used stably at low voltage.
종래의 이중게이트 전극의 형성공정은 반도체기판 상부에 게이트산화막을 형성하고, 그 상부에 1000Å 이하의 얇은 폴리실리콘막을 형성한 후, 상기 폴리실리콘막에 붕소와 같은 P형 도펀트를 주입하고 열처리공정을 실시함으로써, 붕소를 확산시키고 활성화시켜 PMOS 트랜지스터 영역을 형성하였다.In the conventional double gate electrode forming process, a gate oxide film is formed on a semiconductor substrate, a thin polysilicon film of 1000 Å or less is formed thereon, a P-type dopant such as boron is injected into the polysilicon film, and a heat treatment process is performed. By doing so, boron was diffused and activated to form a PMOS transistor region.
하지만 상기와 같은 방법에서 있어서, 열처리공정 시에 붕소가 게이트산화막을 뚫고 반도체기판에 침투하여 문턱전압(threshold voltage)이 불안정해지고, 짧은 채널 효과(Short channel effect)를 가속화시키는 문제점이 있었다.However, in the above-described method, boron penetrates through the gate oxide layer and penetrates the semiconductor substrate during the heat treatment process, thereby making the threshold voltage unstable and accelerating the short channel effect.
또한, 붕소가 반도체기판에 침투하는 것을 방지하기 위해 열처리 공정을 행하지 않은 경우에는 붕소의 확산이 충분하게 일어나지 않아 게이트전극의 도펀트공핍(Gate depletion)현상이 발생하고, 붕소의 활성화률이 낮아지면서 폴리실리콘막의 저항이 증가하여 게이트 특성을 열화시키는 문제점이 발생하였다.In addition, when the heat treatment process is not performed to prevent boron from penetrating the semiconductor substrate, boron diffusion does not sufficiently occur, causing dopant depletion of the gate electrode, and lowering the activation rate of boron. The resistance of the silicon film is increased, causing a problem of deteriorating the gate characteristics.
그래서, 이를 해결하기 위해 폴리-실리콘게르마늄막(Si1-XGeX)을 게이트전극으로 사용하고자 하는 연구가 진행되었다.Thus, in order to solve this problem, a research has been conducted to use a poly-silicon germanium film (Si 1-X Ge X ) as a gate electrode.
폴리-실리콘게르마늄막은게르마늄함량에 따라 페르미에너지 레벨(Fermi energy)을 실리콘의 미드밴드갭(Mid band gap) 근처로 이동시킬 수 있어서, 양호한 대칭성 문턱전압(Symmetric threshold voltage)을 얻을 수 있고, NMOS영역과 PMOS영역을 모두 표면채널(Surface channel)모드에서 작동시킬 수 있다.The poly-silicon germanium film can move the Fermi energy level near the mid band gap of silicon according to the germanium content, so that a good symmetric threshold voltage can be obtained and the NMOS region can be obtained. Both the and PMOS regions can be operated in surface channel mode.
또한 상기 폴리-실리콘게르마늄막에 도펀트를 주입하고 열처리공정을 시행할 때, 폴리-실리콘게르마늄막 내에서 도펀트가 반도체기판에 침투하는 것이 억제되며, 게르마늄의 함량이 20%인 경우, 게이트 도펀트 공핍현상도 감소시킬 수 있어 종래의 폴리실리콘막에 비해 안정된 특성을 가진다.In addition, when the dopant is injected into the poly-silicon germanium film and the heat treatment process is performed, the dopant is prevented from penetrating into the semiconductor substrate in the poly-silicon germanium film, and when the germanium content is 20%, the gate dopant depletion phenomenon It can also be reduced, and has a stable characteristic compared with the conventional polysilicon film.
하지만, 최근에 반도체소자가 점점 소형화되는 추세에 있기 때문에 폴리-실리콘게르마늄막의 사용 시에도 도펀트가 반도체기판에 침투하는 현상을 더욱 효과적으로 억제시켜야 될 필요성이 있다.However, in recent years, as semiconductor devices are becoming more and more miniaturized, there is a need to more effectively suppress the dopant from penetrating the semiconductor substrate even when using a poly-silicon germanium film.
상기와 같은 필요성을 해결하기 위하여 창안된 본 발명의 목적은 게이트전극 형성 시, 폴리-실리콘게르마늄막을 형성한 후, 이에 도펀트를 주입하고 열처리공정을 실시할 때 도펀트가 확산하면서 반도체기판에 침투하는 것을 방지할 수 있는 확산방지막을 형성할 수 있도록 한 반도체소자의 게이트전극 형성방법을 제공하는데있다.An object of the present invention devised to solve the above necessity is to form a poly-silicon germanium film at the time of forming the gate electrode, and then to infiltrate the semiconductor substrate while the dopant is diffused during the dopant injection and heat treatment process. The present invention provides a method of forming a gate electrode of a semiconductor device capable of forming a diffusion preventing film that can be prevented.
도 1 내지 도 4는 본 발명에 따른 반도체소자의 게이트전극 형성방법을 설명하기 위해 도시된 단면도들이다.1 to 4 are cross-sectional views illustrating a method of forming a gate electrode of a semiconductor device according to the present invention.
＊도면의 주요부분에 대한 부호의 설명＊＊ Description of symbols for main parts of the drawings ＊
100 ; 반도체기판 110 ; 게이트산화막100; Semiconductor substrate 110; Gate oxide
110'; 질산화막 120 ; 실리콘시드막110 '; Nitriding film 120; Silicon seed film
120'; 질화막 130 ; 폴리-실리콘게르마늄막120 '; Nitride film 130; Poly-silicon germanium film
상기와 같은 목적을 달성하기 위한 본 발명은 반도체기판 상부에 게이트산화막을 형성하는 단계와; 상기 게이트산화막 상부에 실리콘시드막을 형성하는 단계와; 상기 실리콘시드막에 열처리공정을 실시하여 상기 실리콘시드막의 상부 및 상기 게이트산화막 상부에 확산방지막을 형성하는 단계와; 상기 결과물 상부에 폴리-실리콘게르마늄막을 형성하는 단계와; 상기 폴리-실리콘게르마늄막에 도펀트를 도핑하는 단계; 를 포함하여 이루어진 것을 특징으로 한다.The present invention for achieving the above object comprises the steps of forming a gate oxide film on the semiconductor substrate; Forming a silicon seed film on the gate oxide film; Performing a heat treatment process on the silicon seed layer to form a diffusion barrier layer on the silicon seed layer and on the gate oxide layer; Forming a poly-silicon germanium film on the resultant; Doping a dopant to the poly-silicon germanium film; Characterized in that comprises a.
이하, 첨부된 도면을 참조하여 본 발명의 바람직한 실시예에 대해 설명하고자 한다. 또한, 본 실시예는 발명의 권리범위를 제한하는 것이 아니고, 단지 예시로 제시된 것이다.Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings. In addition, this embodiment does not limit the scope of the invention, but is presented by way of example only.
도 1 내지 도 4는 본 발명에 따른 반도체소자의 게이트산화막 형성방법을 설명하기 위해 도시된 단면도들이다.1 to 4 are cross-sectional views illustrating a method of forming a gate oxide film of a semiconductor device according to the present invention.
우선, 도 1에 도시된 바와 같이 반도체기판(100) 상부에 게이트산화막(110)을 형성한 후, 상기 게이트산화막(110) 상부에 실리콘시드막(120)을 450∼550℃의 온도범위에서 30∼100Å의 두께로 형성한다.First, as shown in FIG. 1, after the gate oxide layer 110 is formed on the semiconductor substrate 100, the silicon seed layer 120 is formed on the gate oxide layer 110 at a temperature in the range of 450 to 550 ° C .. It is formed to a thickness of ˜100 mm 3.
그 다음, 도 2에 도시된 바와 같이 상기 실리콘시드막(120)에 질소분위기 하에서 열처리공정을 실시한다.Next, as shown in FIG. 2, the silicon seed film 120 is subjected to a heat treatment process under a nitrogen atmosphere.
상기 열처리공정은 N2,NH3중 어느 하나를 이용한 질소분위기와 800∼950℃ 의 온도에서 RTP방식으로 30∼120초간 실시되는데, 이로 인해 도 3에 도시된 바와 같이 상기 실리콘시드막(120)의 상부에는 질화막(120')이 형성되고, 질소성분이 상기 게이트산화막(110)까지 확산되면서 상기 게이트산화막(110) 상부에는 질산화막(110')이 형성된다.The heat treatment process is carried out for 30 to 120 seconds in a nitrogen atmosphere using any one of N 2, NH 3 and the RTP method at a temperature of 800 ~ 950 ℃, this is the silicon seed film 120 as shown in FIG. The nitride film 120 'is formed on the upper portion of the substrate, and the nitrogen component diffuses to the gate oxide film 110, and the nitride oxide film 110' is formed on the gate oxide film 110.
상기와 같이 형성된 질화막(120') 및 질산화막(110')은 확산방지막의 역할을 하게 된다. 즉, 이후 게이트전극으로 폴리-실리콘게르마늄막(130)을 형성하고 이에 도펀트를 주입한 후 열처리공정을 실시할 때, 상기 질화막(120') 및 질산화막(110')으로 인해 도펀트가 반도체기판(100)에 침투하는 것이 방지된다.The nitride film 120 'and the nitride oxide film 110' formed as described above serve as a diffusion barrier. That is, when the poly-silicon germanium layer 130 is formed as a gate electrode and a dopant is injected thereinto, and then a heat treatment process is performed, the dopant is formed of a semiconductor substrate due to the nitride film 120 'and the nitride oxide film 110'. Penetration is prevented.
상기와 같은 확산방지막을 형성한 후, 도 4에 도시된 바와 같이 상기 결과물의 상부에 폴리-실리콘게르마늄막(130)을 형성한다.After forming the diffusion barrier as described above, as shown in FIG. 4, a poly-silicon germanium film 130 is formed on the resultant.
상기 실리콘-게르마늄막(130)은 LPCVD(Low Pressure Chemical Vapor Deposition), VLPCVD(Very Low Pressure Chemical Vapor Deposition), PE-VLPCVD(Plasma Enhanced-Very Low Pressure Chemical Vapor Deposition), UHVCVD(Ultrahigh Vacuum Chemical Vapor Deposition), RTCVD(Rapid Thermal Chemical Vapor Deposition), APCVD(Atmosphere Pressure Chemical Vapor Deposition), MBE(Molecular Beam Epitaxy)방식 중 어느 하나를 이용하여 700∼1500Å의 두께로 형성되는데, 이때 상기 실리콘-게르마늄막(130) 내의 게르마늄 함량은 10∼70%이고, 공정압력은 5∼1000mTorr이며, 온도범위는 500∼650℃이다.The silicon-germanium layer 130 may include low pressure chemical vapor deposition (LPCVD), very low pressure chemical vapor deposition (VLPCVD), plasma enhanced-very low pressure chemical vapor deposition (PE-VLPCVD), and ultrahigh vacuum chemical vapor deposition (UHVCVD). ), RTCVD (Rapid Thermal Chemical Vapor Deposition), APCVD (Atmosphere Pressure Chemical Vapor Deposition), MBE (Molecular Beam Epitaxy) method using any one of the thickness of 700 ~ 1500Å, wherein the silicon-germanium film 130 The germanium content in) is 10-70%, the process pressure is 5-1000 mTorr, and the temperature range is 500-650 ° C.
그리고, 상기 폴리-실리콘게르마늄막(130) 형성 시 실리콘의 소스로는 SiH4, Si6H6중 어느 하나를 사용하고, 게르마늄의 소스로는 GeH4, GeF4중 어느 하나를 사용하면 된다.In addition, the poly-to-source in the silicon germanium film 130 during the formation of silicon is to use any one of SiH 4, Si 6 H 6, it is when the source back to the germanium is used for any one of GeH 4, GeF 4.
또한, 상기 폴리-실리콘게르마늄막(130) 형성공정은 수소가스를 이용한 수소분위기 하에서 진행되는데, 상기 SiH4및 Si6H6가스는 수소가스 내에 10∼100% 정도 함유된 것을 사용하고, 상기 GeH4, GeF4가스는 수소가스 내에 1∼100% 정도 함유된 것을 사용한다.In addition, the poly-silicon germanium film 130 forming process is carried out under a hydrogen atmosphere using hydrogen gas, the SiH 4 and Si 6 H 6 gas is used that contains about 10 to 100% in hydrogen gas, the GeH 4 , GeF 4 gas is used containing about 1 to 100% in hydrogen gas.
이후, 상기 폴리-실리콘게르마늄막(130)에 도펀트를 도핑하고, 열공정을 실시한다.Thereafter, a dopant is doped into the poly-silicon germanium layer 130 and a thermal process is performed.
이때, 상기 폴리-실리콘게르마늄막(130)에 주입되는 도펀트는 B, BF2중 어느 하나를 사용하는데, 상기 폴리-실리콘게르마늄 막(130)이 형성될 때, 도펀트가스를 사용한 인-시튜방식으로 상기 폴리-실리콘게르마늄막(130)에 도핑되거나 상기 폴리-실리콘게르마늄막(130)을 형성한 후, 이온주입방식으로 상기 폴리-실리콘게르마늄막(130)에 도핑된다.In this case, the dopant injected into the poly-silicon germanium film 130 may use any one of B and BF 2. When the poly-silicon germanium film 130 is formed, an in-situ method using a dopant gas may be used. After the poly-silicon germanium layer 130 is doped or the poly-silicon germanium layer 130 is formed, the poly-silicon germanium layer 130 is doped by ion implantation.
그리고, 열공정을 실시하여 도펀트를 고르게 확산시킬 때 상기에서 형성된 질화막(120') 및 질산화막(110')으로 인해 도펀트가 반도체기판(100)에 침투하는 것이 방지된다.In addition, when the dopant is uniformly diffused by performing the thermal process, the dopant is prevented from penetrating into the semiconductor substrate 100 due to the nitride film 120 'and the nitride oxide film 110' formed above.
상기한 바와 같이 본 발명은 반도체소자의 게이트전극 형성방법에 관한 것으로써, 반도체기판의 상부에 게이트산화막 및 실리콘시드막을 차례로 형성한 후, 상기 실리콘시드막에 질소분위기 하에서 열처리공정을 실시하여 상기 실리콘시드막의 상부 및 상기 게이트산화막의 상부에 확산방지막을 형성함으로써, 이후 상기 실리콘시드막의 상부에 게이트전극으로 폴리-실리콘게르마늄막을 형성하고, 이에 도펀트를 주입한 후 열공정을 실시할 때 상기 확산방지막으로 인해 도펀트가 확산하면서 반도체기판에 침투하는 것이 방지되어 게이트특성 및 반도체소자의 전기적 특성을 향상시킬 수 있는 효과를 가진다.As described above, the present invention relates to a method for forming a gate electrode of a semiconductor device. The gate oxide film and a silicon seed film are sequentially formed on a semiconductor substrate, and then the silicon seed film is subjected to a heat treatment process under a nitrogen atmosphere. By forming a diffusion barrier layer on the seed layer and the gate oxide layer, a poly-silicon germanium layer is formed on the silicon seed layer as a gate electrode, and then a dopant is injected into the diffusion barrier layer. As a result, dopants are prevented from penetrating into the semiconductor substrate while being diffused, thereby improving the gate characteristics and electrical characteristics of the semiconductor device.
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| KR100451039B1 (en) * | 2000-12-20 | 2004-10-02 | 주식회사 하이닉스반도체 | Method of forming a gate electrode in a semiconductor device |
| KR100640572B1 (en) * | 2000-09-20 | 2006-10-31 | 삼성전자주식회사 | Method for forming a transistor |
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| JPS60195975A (en) * | 1984-03-19 | 1985-10-04 | Fujitsu Ltd | Semiconductor device |
| KR980005455A (en) * | 1996-06-21 | 1998-03-30 | 김주용 | Gate electrode formation method of semiconductor device |
| KR0137901B1 (en) * | 1994-02-07 | 1998-04-27 | 문정환 | Mos transistor device & method for fabricating the same |
| KR100252898B1 (en) * | 1998-02-12 | 2000-04-15 | 김영환 | Semiconductor element manufacturing method |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| JPS60195975A (en) * | 1984-03-19 | 1985-10-04 | Fujitsu Ltd | Semiconductor device |
| KR0137901B1 (en) * | 1994-02-07 | 1998-04-27 | 문정환 | Mos transistor device & method for fabricating the same |
| KR980005455A (en) * | 1996-06-21 | 1998-03-30 | 김주용 | Gate electrode formation method of semiconductor device |
| KR100252898B1 (en) * | 1998-02-12 | 2000-04-15 | 김영환 | Semiconductor element manufacturing method |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100640572B1 (en) * | 2000-09-20 | 2006-10-31 | 삼성전자주식회사 | Method for forming a transistor |
| KR100451039B1 (en) * | 2000-12-20 | 2004-10-02 | 주식회사 하이닉스반도체 | Method of forming a gate electrode in a semiconductor device |
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