KR100306812B1 - Method of forming gate for semiconductor device - Google Patents
Method of forming gate for semiconductor device Download PDFInfo
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- KR100306812B1 KR100306812B1 KR1019990025253A KR19990025253A KR100306812B1 KR 100306812 B1 KR100306812 B1 KR 100306812B1 KR 1019990025253 A KR1019990025253 A KR 1019990025253A KR 19990025253 A KR19990025253 A KR 19990025253A KR 100306812 B1 KR100306812 B1 KR 100306812B1
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 14
- 238000000034 method Methods 0.000 title claims description 18
- 229910052732 germanium Inorganic materials 0.000 claims abstract description 45
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims abstract description 45
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 33
- 229920005591 polysilicon Polymers 0.000 claims abstract description 31
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 18
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 18
- 239000010703 silicon Substances 0.000 claims abstract description 18
- 230000003647 oxidation Effects 0.000 claims abstract description 17
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 17
- 239000007789 gas Substances 0.000 claims abstract description 16
- 239000000758 substrate Substances 0.000 claims abstract description 11
- 239000012298 atmosphere Substances 0.000 claims abstract description 9
- 239000012535 impurity Substances 0.000 claims abstract description 9
- 238000005530 etching Methods 0.000 claims abstract description 8
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims abstract description 5
- 238000010438 heat treatment Methods 0.000 claims abstract description 5
- 239000001301 oxygen Substances 0.000 claims abstract description 5
- 229910052760 oxygen Inorganic materials 0.000 claims abstract description 5
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims abstract description 4
- 229910001873 dinitrogen Inorganic materials 0.000 claims abstract description 4
- 150000002500 ions Chemical class 0.000 claims description 8
- 238000004518 low pressure chemical vapour deposition Methods 0.000 claims description 8
- 238000001505 atmospheric-pressure chemical vapour deposition Methods 0.000 claims description 3
- 229910052796 boron Inorganic materials 0.000 claims description 3
- 238000000151 deposition Methods 0.000 claims description 3
- 229910052698 phosphorus Inorganic materials 0.000 claims description 3
- 238000001289 rapid thermal chemical vapour deposition Methods 0.000 claims description 3
- 238000001451 molecular beam epitaxy Methods 0.000 claims description 2
- 230000001590 oxidative effect Effects 0.000 claims description 2
- 238000005229 chemical vapour deposition Methods 0.000 claims 1
- 238000004519 manufacturing process Methods 0.000 abstract description 3
- 230000006866 deterioration Effects 0.000 abstract description 2
- 239000010408 film Substances 0.000 description 19
- 230000000694 effects Effects 0.000 description 5
- 230000015572 biosynthetic process Effects 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 238000011065 in-situ storage Methods 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 229910002616 GeOx Inorganic materials 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 239000012299 nitrogen atmosphere Substances 0.000 description 1
- 230000035515 penetration Effects 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
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- E02D3/10—Improving by compacting by watering, draining, de-aerating or blasting, e.g. by installing sand or wick drains
- E02D3/103—Improving by compacting by watering, draining, de-aerating or blasting, e.g. by installing sand or wick drains by installing wick drains or sand bags
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- E—FIXED CONSTRUCTIONS
- E02—HYDRAULIC ENGINEERING; FOUNDATIONS; SOIL SHIFTING
- E02D—FOUNDATIONS; EXCAVATIONS; EMBANKMENTS; UNDERGROUND OR UNDERWATER STRUCTURES
- E02D2600/00—Miscellaneous
- E02D2600/20—Miscellaneous comprising details of connection between elements
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- Agronomy & Crop Science (AREA)
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Abstract
본 발명은 폴리 실리콘저마늄의 산화특성에 의한 게이트 특성 및 신뢰성 저하를 방지할 수 있는 반도체 소자의 제조방법을 제공한다.The present invention provides a method of manufacturing a semiconductor device that can prevent the gate characteristics and the reliability deterioration due to the oxidation characteristics of polysilicon germanium.
본 발명에 따라 반도체 기판 상에 게이트 절연막 및 불순물이 도핑된 폴리 실리콘저마늄막을 증착하고, 도핑된 폴리 실리콘저마늄막을 식각하여 게이트를 형성한다. 그런 다음, 게이트가 형성된 기판을 열처리하여 상기 게이트의 측부에 실리콘리치 영역을 형성하고, 실리콘리치 영역이 형성된 기판을 LDD 산화한다. 본 실시예에서, 열처리는 질소개스 분위기에서 600 내지 900℃의 온도로 20분 내지 3시간 동안 진행하고, LDD 산화는 산소 또는 H2O 개스 분위기에서 700 내지 900℃의 온도로 30분 내지 3시간 동안 진행한다.According to the present invention, a gate insulating film and a polysilicon germanium layer doped with an impurity are deposited on a semiconductor substrate, and a gate is formed by etching the doped polysilicon germanium layer. Then, the substrate on which the gate is formed is heat-treated to form a silicon rich region on the side of the gate, and the substrate on which the silicon rich region is formed is LDD oxidized. In this embodiment, the heat treatment is performed for 20 minutes to 3 hours at a temperature of 600 to 900 ℃ in nitrogen gas atmosphere, LDD oxidation 30 minutes to 3 hours at a temperature of 700 to 900 ℃ in oxygen or H 2 O gas atmosphere Proceed.
Description
본 발명은 반도체 소자의 제조방법에 관한 것으로, 특히 폴리 실리콘저마늄을 이용한 반도체 소자의 게이트 형성방법에 관한 것이다.The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for forming a gate of a semiconductor device using polysilicon germanium.
일반적으로, 반도체 소자의 게이트 물질로서 저저항, 고융점, 박막 형성의 용이성, 라인 패턴(line pattern) 형성의 용이성, 산화분위기에 대한 안정성, 평탄한 표면특성 등이 우수한 폴리실리콘막이 널리 사용된다. 한편, 고집적화에 따른 저저항의 게이트를 얻기 위하여 폴리실리콘막에 보론(B) 또는 인(P)과 같은 불순물을 주입하여 폴리실리콘막의 저항을 감소시켰다. 이러한 게이트를 이용하여 PMOS 및 NMOS 트랜지스터를 형성하게 되면, NMOS 트랜지스터는 표면채널(surface channel) 형태로 동작하고, PMOS 트랜지스터에서는 배리드 채널(buried channel) 형태로 동작한다.In general, a polysilicon film excellent in low resistance, high melting point, ease of forming a thin film, ease of forming a line pattern, stability to an oxidizing atmosphere, flat surface characteristics, etc. is widely used as a gate material of a semiconductor device. On the other hand, in order to obtain a low resistance gate due to high integration, impurities such as boron (B) or phosphorus (P) are injected into the polysilicon film to reduce the resistance of the polysilicon film. When the PMOS and the NMOS transistors are formed using the gates, the NMOS transistors operate in the form of surface channels and the buried channels in the PMOS transistors.
한편, PMOS 트랜지스터의 경우에는 적절한 문턱전압을 얻기 위하여, B이온을 카운터 도핑하는데, 이때 고농도로 도핑된 B이온의 다수 캐리어인 홀(hole)이 저농도로 도핑된 채널영역으로 확산되어 단채널 효과(short channel effect)가 유발되어, 누설전류 및 DIBL(Drain Induced Barrier Lowering) 효과가 증가되어 고집적화에 큰 제한요인으로 작용한다. 또한, 게이트 물질로서 폴리실리콘막을 사용하는 경우, 게이트 공핍(gate depletion) 및 불순물 침투(peneration)등에 의해 문턱전압변동 및 게이트 특성이 열화되는 문제가 발생된다.On the other hand, in the case of a PMOS transistor, in order to obtain an appropriate threshold voltage, B ions are counter-doped. In this case, holes, which are a large number of carriers of heavily doped B ions, are diffused into the lightly doped channel region so that a short channel effect ( Short channel effects are induced, and leakage current and drain induced barrier lowering (DIBL) effects are increased, which is a large limiting factor for high integration. In addition, when a polysilicon film is used as the gate material, a problem arises in that the threshold voltage variation and gate characteristics are deteriorated due to gate depletion and impurity penation.
상기한 바와 같은 문제를 보완하기 위하여, 차세대 게이트 물질로서 폴리 실리콘저마늄(poly-Si1-XGeX)이 제시되었다. 이러한 폴리 실리콘저마늄은 저마늄의 몰불율을 증가시킬수록 페르미 에너지(Fermi energy) 레벨을 실리콘의 밴드갭 근처로 위치시킬 수 있어서, 양호한 대칭성 문턱전압을 얻을 수 있을 뿐만 아니라 NMOS 및 PMOS 트랜지스터를 표면 채널형태로의 동작을 가능하게 한다. 또한, 게이트 공핍효과 및 불순물 이온의 침투를 방지하여 게이트 특성이 향상된다.In order to solve the problem as described above, poly-silicon germanium (poly-Si 1-X Ge X ) has been proposed as a next-generation gate material. Such polysilicon germanium is able to place Fermi energy level near the silicon band gap as the molar ratio of germanium increases, so that a good symmetrical threshold voltage can be obtained as well as surface NMOS and PMOS transistors. Enable operation in channel form. In addition, gate characteristics are improved by preventing the gate depletion effect and the penetration of impurity ions.
그러나, 상기한 바와 같이 폴리 실리콘저마늄의 게이트 형성 후, LDD (Lightly Doped Drain) 산화 공정을 진행하게 되면, 저마늄의 함량에 따라 GeOx 및 SiOx와 같은 산화막이 두껍게 형성되어, 게이트의 측벽 프로파일의 변형이 유발되어 게이트의 특성 및 신뢰성이 저하될 뿐만 아니라 후속공정에 대하여 악영향을 미치게 된다. 즉, 도 1a 내지 도 1g는 XPS(X-ray Photoelectron Spectroscope) 분석에 의한 저마늄 함량에 따른 폴리 실리콘저마늄의 산화특성 데이터를 나타낸 도면으로서, 도 1a 내지 도 1e는 저마늄 함량이 각각 0%, 20%, 40%, 60% 및 100%인 경우의 산화특성을 나타내고, 도 1f 및 도 1g는 인시튜 상태로 B이온이 도핑되고 저마늄 함량이 60%인 경우와 인시튜 상태로 P이온이 도핑되고 저마늄 함량이 60%인 경우의 산화특성을 각각 나타낸다.However, as described above, when the LDD (Lightly Doped Drain) oxidation process is performed after the formation of the gate of the polysilicon germanium, oxide films such as GeOx and SiOx are thickly formed according to the germanium content, thereby forming the sidewall profile of the gate. Deformation is caused, which not only degrades the gate characteristics and reliability, but also adversely affects subsequent processes. 1A to 1G are graphs showing oxidation characteristics data of polysilicon germanium according to germanium content by X-ray photoelectron spectroscope (XPS) analysis, and FIGS. 1A to 1E are 0% germanium content, respectively. , 20%, 40%, 60% and 100% of the oxidation characteristics, Figures 1f and 1g is doped in the in-situ B ions and the germanium content of 60% and in situ P ions Oxidation characteristics are shown when the doped and germanium content is 60%.
따라서, 본 발명은 상기한 종래의 문제점을 해결하기 위한 것으로서, 폴리 실리콘저마늄의 산화특성에 의한 게이트 특성 및 신뢰성 저하를 방지할 수 있는 반도체 소자의 제조방법을 제공함에 그 목적이 있다.Accordingly, an object of the present invention is to provide a method of manufacturing a semiconductor device capable of preventing the deterioration of gate characteristics and reliability caused by oxidation characteristics of polysilicon germanium.
도 1a 내지 도 1g는 폴리 실리콘저마늄 게이트의 저마늄 함량에 따른 산화특성 데이터를 나타낸 도면.1A to 1G are graphs showing oxidation characteristic data according to germanium content of a polysilicon germanium gate.
도 2는 본 발명의 실시예에 따른 반도체 소자의 게이트 형성방법을 설명하기 위한 단면도.2 is a cross-sectional view illustrating a gate forming method of a semiconductor device in accordance with an embodiment of the present invention.
(도면의 주요부분에 대한 부호의 설명)(Explanation of symbols on the main parts of drawing
10 : 반도체 기판 11 : 게이트 절연막10 semiconductor substrate 11 gate insulating film
12 : 폴리 실리콘저마늄의 게이트12: gate of polysilicon germanium
12A : 실리콘 리치 영역 13 : LDD 산화막12A: Silicon Rich Region 13: LDD Oxide
상기한 본 발명의 목적을 달성하기 위하여, 본 발명에 따라 반도체 기판 상에 게이트 절연막 및 불순물이 도핑된 폴리 실리콘저마늄막을 증착하고, 도핑된 폴리 실리콘저마늄막을 식각하여 게이트를 형성한다. 그런 다음, 게이트가 형성된 기판을 열처리하여 상기 게이트의 측부에 실리콘리치 영역을 형성하고, 실리콘리치 영역이 형성된 기판을 LDD 산화한다.In order to achieve the above object of the present invention, a polysilicon germanium film doped with a gate insulating film and an impurity is deposited on a semiconductor substrate, and a gate is formed by etching the doped polysilicon germanium film. Then, the substrate on which the gate is formed is heat-treated to form a silicon rich region on the side of the gate, and the substrate on which the silicon rich region is formed is LDD oxidized.
본 실시예에서, 열처리는 질소개스 분위기에서 600 내지 900℃의 온도로 20분 내지 3시간 동안 진행하고, LDD 산화는 산소 또는 H2O 개스 분위기에서 700 내지 900℃의 온도로 30분 내지 3시간 동안 진행한다.In this embodiment, the heat treatment is performed for 20 minutes to 3 hours at a temperature of 600 to 900 ℃ in nitrogen gas atmosphere, LDD oxidation 30 minutes to 3 hours at a temperature of 700 to 900 ℃ in oxygen or H 2 O gas atmosphere Proceed.
이하, 첨부된 도면을 참조하여 본 발명의 실시예를 설명한다.Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention.
도 2는 본 발명의 실시예에 따른 폴리 실리콘저마늄을 이용한 반도체 소자의 게이트 형성방법을 설명하기 위한 단면도이다.2 is a cross-sectional view illustrating a gate forming method of a semiconductor device using polysilicon germanium according to an embodiment of the present invention.
도 2를 참조하면, 반도체 기판(10) 상에 열산화 공정으로 게이트 절연막(11)을 형성하고, 게이트 절연막(11) 상에 불순물이온이 도핑된 폴리 실리콘저마늄막을 증착한다. 여기서, 폴리 실리콘저마늄막은 450 내지 700℃의 온도와, 1 내지 3,000 mTorr의 압력에서 500 내지 5,000Å의 두께로 다결정 상태로 증착한다. 또한, 상기 불순믈 이온은 B, P 또는 As이고, 폴리 실리콘저마늄막의 저마늄 함량은 0 내지 70%의 범위로 한다.Referring to FIG. 2, a gate insulating film 11 is formed on a semiconductor substrate 10 by a thermal oxidation process, and a polysilicon germanium film doped with impurity ions is deposited on the gate insulating film 11. Here, the polysilicon germanium film is deposited in a polycrystalline state at a temperature of 450 to 700 ° C. and a thickness of 500 to 5,000 Pa at a pressure of 1 to 3,000 mTorr. In addition, the impurity ions are B, P or As, the germanium content of the polysilicon germanium film is in the range of 0 to 70%.
또한, 폴리 실리콘저마늄막은 실리콘 소오스 개스로서 SiH4개스와 Si2H6개스를 사용하고 저마늄 소오스 개스로서 GeH4개스를 사용하여, 저압화학기상증착 (Low Pressure Chemical Vapor Deposition; LPCVD), 매우 낮은 압력 CVD(Very LPCVD), 플라즈마 보조 VLPCVD(Plasma Enhanced VLPCVD; PE-VLPCVD), 과진공 CVD(Ultrahigh Vaccum CVD; UHVCVD), 급속열적 CVD(Rapid Thermal CVD; RTCVD), 상압 CVD (Atomosphere Pressure CVD; APCVD) 또는 분자빔에피택시(Molecular Beam Epitaxy; MBE)로 증착한다.Further, polysilicon germanium as a film silicon source gas using SiH 4 gas and Si 2 H 6 gas and using GeH 4 gas as a germanium source gas, low pressure chemical vapor deposition (Low Pressure Chemical Vapor Deposition; LPCVD), so Low Pressure CVD (Very LPCVD), Plasma Enhanced VLPCVD (PE-VLPCVD), Ultrahigh Vaccum CVD (UHVCVD), Rapid Thermal CVD (RTCVD), Atmospheric Pressure CVD (Atomosphere Pressure CVD); Deposition by APCVD or Molecular Beam Epitaxy (MBE).
그리고 나서, 도핑된 폴리 실리콘저마늄막을 포토리소그라피 및 식각공정으로 패터닝하여 폴리 실리콘저마늄의 게이트(12)를 형성한다. 이때, 식각은 SF6또는 Cl2개스를 기본으로 하는 플라즈마를 이용하여 진행한다. 또한, 식각시 플라즈마 손상에 의해 게이트 절연막(11)이 일부 식각된다.The doped polysilicon germanium film is then patterned by photolithography and etching to form the gate 12 of polysilicon germanium. At this time, etching is performed using a plasma based on SF 6 or Cl 2 gas. In addition, the gate insulating layer 11 is partially etched by plasma damage during etching.
그런 다음, 저마늄 함량에 따른 게이트(12)의 산화를 방지하기 위하여, 질소개스 분위기에서 600 내지 900℃의 온도로 20분 내지 3시간 동안 열처리를 진행하여 게이트(12)의 측부에 실리콘 리치(silicon rich) 영역(12A)을 형성한다. 즉, 실리콘의 열확산도(thermal diffusivity; 0.9㎠/초)가 저마늄의 열확산도(0.36㎠/초)보다 높고, 실리콘의 원자반경(1.32Å)이 저마늄의 원자반경(1.37Å)보다 작을 뿐만 아니라 실리콘의 원자량(28.01g)이 저마늄의 원자량(72.59g)보다 가볍기 대문에, 실리콘이 저마늄보다 동일한 조건하에서 확산속도가 빠르기 때문이다.Then, in order to prevent oxidation of the gate 12 according to the germanium content, a heat treatment is performed for 20 minutes to 3 hours at a temperature of 600 to 900 ° C. in a nitrogen gas atmosphere to provide silicon rich ( silicon rich) region 12A is formed. That is, the thermal diffusivity of silicon (0.9 cm 2 / sec) is higher than that of germanium (0.36 cm 2 / sec), and the atomic radius of silicon (1.32 Å) is smaller than that of germanium (1.37 Å). In addition, since the atomic weight of silicon (28.01 g) is lighter than that of germanium (72.59 g), the diffusion rate is faster under the same conditions than silicon.
그 후, 산소 또는 H2O 개스 분위기에서 700 내지 900℃의 온도로 30분 내지 3시간 동안 LDD 산화 공정을 진행하여, 게이트(12)의 측벽 및 노출된 기판(10) 표면 상에 LDD 산화막(13)을 형성한다. 이때, 게이트(12) 측부에 형성된 실리콘 리치영역(12A)에 의해, 저마늄과 산소와의 반응이 억제되어, 종래와 같은 두꺼운 측벽 산화막 형성이 방지되어, 게이트(12)의 측벽 프로파일 변형이 발생되지 않는다.Thereafter, the LDD oxidation process is performed for 30 minutes to 3 hours at an temperature of 700 to 900 ° C. in an oxygen or H 2 O gas atmosphere, so that the LDD oxide film ( 13). At this time, the silicon rich region 12A formed at the side of the gate 12 suppresses the reaction between germanium and oxygen, thereby preventing the formation of a thick sidewall oxide film as in the prior art, so that sidewall profile deformation of the gate 12 occurs. It doesn't work.
상기한 본 발명에 의하면, 게이트 형성을 위한 폴리 실리콘저마늄막의 식각 후, LDD 산화전에 질소 분위기에서 열처리를 진행하여, 게이트의 측부에 실리콘 리치 영역을 형성함으로써, LDD 산화시 게이트 측벽에서의 저마늄의 산화가 억제되어, 게이트 측벽 프로파일 변형이 방지된다. 이에 따라, 양호한 LDD 산화 효과를 얻을 수 있으므로, 결국 게이트의 특성 및 신뢰성이 향상된다.According to the present invention described above, after etching the polysilicon germanium film for gate formation, heat treatment is performed in a nitrogen atmosphere before LDD oxidation, and a silicon rich region is formed on the side of the gate, thereby making germanium at the gate sidewall during LDD oxidation. Oxidation is suppressed, and gate sidewall profile deformation is prevented. As a result, a good LDD oxidation effect can be obtained, which in turn improves the gate characteristics and reliability.
또한, 본 발명은 상기 실시예에 한정되지 않고, 본 발명의 기술적 요지를 벗어나지 않는 범위내에서 다양하게 변형시켜 실시할 수 있다.In addition, this invention is not limited to the said Example, It can variously deform and implement within the range which does not deviate from the technical summary of this invention.
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