KR100312657B1 - Method of forming gate for semiconductor device - Google Patents
Method of forming gate for semiconductor device Download PDFInfo
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- KR100312657B1 KR100312657B1 KR1019990058820A KR19990058820A KR100312657B1 KR 100312657 B1 KR100312657 B1 KR 100312657B1 KR 1019990058820 A KR1019990058820 A KR 1019990058820A KR 19990058820 A KR19990058820 A KR 19990058820A KR 100312657 B1 KR100312657 B1 KR 100312657B1
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- film
- polysilicon
- polysilicon germanium
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- germanium
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- 238000000034 method Methods 0.000 title claims abstract description 19
- 239000004065 semiconductor Substances 0.000 title claims abstract description 15
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 74
- 229920005591 polysilicon Polymers 0.000 claims abstract description 71
- 229910052732 germanium Inorganic materials 0.000 claims abstract description 58
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims abstract description 58
- 239000000758 substrate Substances 0.000 claims abstract description 10
- 238000004518 low pressure chemical vapour deposition Methods 0.000 claims description 4
- 238000005530 etching Methods 0.000 claims description 3
- 238000011065 in-situ storage Methods 0.000 claims description 3
- 238000001451 molecular beam epitaxy Methods 0.000 claims description 3
- 238000005498 polishing Methods 0.000 claims description 3
- 238000001289 rapid thermal chemical vapour deposition Methods 0.000 claims description 3
- 229910052710 silicon Inorganic materials 0.000 claims description 3
- 239000010703 silicon Substances 0.000 claims description 3
- 239000000126 substance Substances 0.000 claims description 3
- 238000000038 ultrahigh vacuum chemical vapour deposition Methods 0.000 claims description 3
- 238000011066 ex-situ storage Methods 0.000 claims description 2
- 238000001505 atmospheric-pressure chemical vapour deposition Methods 0.000 claims 1
- 230000015572 biosynthetic process Effects 0.000 claims 1
- 239000010408 film Substances 0.000 description 43
- 238000000151 deposition Methods 0.000 description 6
- 230000000694 effects Effects 0.000 description 5
- 150000002500 ions Chemical class 0.000 description 5
- 238000005229 chemical vapour deposition Methods 0.000 description 4
- 239000012535 impurity Substances 0.000 description 4
- 230000010354 integration Effects 0.000 description 4
- 230000003746 surface roughness Effects 0.000 description 4
- 230000008021 deposition Effects 0.000 description 3
- 238000005468 ion implantation Methods 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 125000006850 spacer group Chemical group 0.000 description 3
- 230000006866 deterioration Effects 0.000 description 2
- 239000002019 doping agent Substances 0.000 description 2
- 230000001590 oxidative effect Effects 0.000 description 2
- 230000035515 penetration Effects 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000009499 grossing Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28247—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon passivation or protection of the electrode, e.g. using re-oxidation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/32115—Planarisation
- H01L21/3212—Planarisation by chemical mechanical polishing [CMP]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
Abstract
본 발명은 폴리 실리콘저마늄의 표면특성을 향상시킬 수 있는 반도체 소자의게이트 형성방법을 제공한다.The present invention provides a method for forming a gate of a semiconductor device capable of improving the surface properties of polysilicon germanium.
본 발명에 따라, 반도체 기판 상에 게이트 산화막 및 도핑된 폴리 실리콘저마늄막을 순차적으로 형성하고, 폴리 실리콘저마늄막을 일부 제거하여 그의 표면을평탄화시킨다. 그런 다음, 폴리 실리콘저마늄 상에 발생되는 자연산화막을 제거하고, 평탄화된 폴리 실리콘저마늄막 상부에 캡핑층으로서 폴리실리콘막을 형성한 후, 폴리실리콘막 및 폴리실리콘저마늄막을 식각하여 게이트를 형성한다.According to the present invention, a gate oxide film and a doped polysilicon germanium film are sequentially formed on a semiconductor substrate, and a part of the polysilicon germanium film is removed to flatten its surface. Thereafter, a natural oxide film generated on the polysilicon germanium is removed, a polysilicon film is formed as a capping layer on the planarized polysilicon germanium film, and the polysilicon film and the polysilicon germanium film are etched to form a gate. .
Description
본 발명은 반도체 소자의 제조방법에 관한 것으로, 특히 폴리 실리콘저마늄을 이용한 반도체 소자의 게이트 형성방법에 관한 것이다.The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for forming a gate of a semiconductor device using polysilicon germanium.
일반적으로, 반도체 소자의 게이트 물질로서 저저항, 고융점, 박막 형성의 용이성, 라인 패턴(line pattern) 형성의 용이성, 산화분위기에 대한 안정성, 평탄한 표면특성 등이 우수한 폴리실리콘막이 널리 사용된다. 한편, 고집적화에 따른 저저항의 게이트를 얻기 위하여 폴리실리콘막에 보론(B) 또는 인(P)과 같은 불순물을 주입하여 폴리실리콘막의 저항을 감소시켰다. 이러한 게이트를 이용하여 PMOS 및 NMOS 트랜지스터를 형성하게 되면, NMOS 트랜지스터는 표면채널(surface channel) 형태로 동작하고, PMOS 트랜지스터에서는 배리드 채널(buried channel) 형태로 동작한다.In general, a polysilicon film excellent in low resistance, high melting point, ease of forming a thin film, ease of forming a line pattern, stability to an oxidizing atmosphere, flat surface characteristics, etc. is widely used as a gate material of a semiconductor device. On the other hand, in order to obtain a low resistance gate due to high integration, impurities such as boron (B) or phosphorus (P) are injected into the polysilicon film to reduce the resistance of the polysilicon film. When the PMOS and the NMOS transistors are formed using the gates, the NMOS transistors operate in the form of surface channels and the buried channels in the PMOS transistors.
여기서, PMOS 트랜지스터의 경우에는 적절한 문턱전압을 얻기 위하여, B이온을 카운터 도핑하는데, 이때 고농도로 도핑된 B이온의 다수 캐리어인 홀(hole)이 저농도로 도핑된 채널영역으로 확산되어 단채널 효과(short channel effect)가 유발되어, 누설전류 및 DIBL(Drain Induced Barrier Lowering) 효과가 증가되어 고집적화에 큰 제한요인으로 작용한다. 또한, 게이트 물질로서 폴리실리콘막을 사용하는 경우, 게이트 공핍현상(gate depletion effect) 및 불순물 침투(penetration)등에 의해 문턱전압변동 및 게이트 특성(GOI; Gate Oxide Integrity)이 열화되는 문제가 발생된다.Here, in the case of the PMOS transistor, in order to obtain an appropriate threshold voltage, B ions are counter-doped. In this case, holes, which are many carriers of heavily doped B ions, are diffused into the lightly doped channel region so that the short channel effect ( Short channel effects are induced, and leakage current and drain induced barrier lowering (DIBL) effects are increased, which is a large limiting factor for high integration. In addition, when a polysilicon film is used as the gate material, there is a problem in that threshold voltage fluctuation and gate characteristic (GOI) are degraded due to gate depletion effect and impurity penetration.
상기한 바와 같은 문제를 보완하기 위하여, 차세대 게이트 물질로서 폴리 실리콘저마늄(poly-Sil-xGex)이 제시되었다. 이러한 폴리 실리콘저마늄은 저마늄 함량에 따라(∼60%) 페르미 에너지(Fermi energy) 레벨을 실리콘의 미드 밴드갭(mid-bandgap) 근처로 위치시킬 수 있어서, 양호한 대칭성 문턱전압(Symmetric threshold voltage)을 얻을 수 있을 뿐만 아니라 NMOS 및 PMOS 트랜지스터 모두 표면 채널형태로의 동작을 가능하게 한다. 특히, 저마늄 함량이 20%인 경우에는 게이트 공핍효과 및 불순물 이온의 침투가 억제되어 게이트 특성이 향상된다.In order to solve the problems as described above, poly-silicon germanium (poly-Si lx Ge x ) has been proposed as a next-generation gate material. These polysilicon germaniums are able to place the Fermi energy level near the mid-bandgap of silicon, depending on the germanium content (-60%), resulting in a good symmetric threshold voltage. In addition, both NMOS and PMOS transistors enable operation in the form of surface channels. In particular, when the germanium content is 20%, gate depletion effects and penetration of impurity ions are suppressed, thereby improving gate characteristics.
그러나, 상기한 폴리 실리콘저마늄은 일반적으로 화학기상증착(chemical vapor deposition; CVD)으로 형성되는데, 이러한 폴리 실리콘저마늄은 폴리실리콘에 비하여 매우 거친 표면을 갖는다. 이에 따라, 소자특성의 열화가 초래될 뿐만 아니라 제조공정을 진행하기가 어렵고, 이러한 현상은 반도체 소자의 경박단소화 및 고집적화에 따라 더욱 심하게 발생된다.However, the above polysilicon germanium is generally formed by chemical vapor deposition (CVD), which has a much rougher surface than polysilicon. As a result, deterioration of the device characteristics is not only caused, but it is difficult to proceed with the manufacturing process, and this phenomenon is more severely generated due to lighter, shorter and smaller integration of the semiconductor device.
한편, 상기한 폴리 실리콘저마늄의 양호한 표면거칠기를 얻기 위하여, 폴리실리콘저마늄 상부에 인시튜(in-situ)로 폴리실리콘막을 형성하는 방법이 제시되었다.On the other hand, in order to obtain a good surface roughness of the polysilicon germanium, a method of forming a polysilicon film in-situ on the polysilicon germanium has been proposed.
즉, 도 1a 내지 도 1e는 폴리 실리콘저마늄 상부에 폴리실리콘막을 형성한 경우, 폴리 실리콘저마늄의 저마늄 함량에 따른 표면 형상을 AFM(Automic Force Microscope)로 관찰하여 나타낸 도면으로서, 도 1a는 저마늄을 함유하지 않은 경우즉, 폴리실리콘막만의 표면 형상을 나타내고, 도 1b 내지 도 1d는 20%, 40% 및 60%의 저마늄을 각각 함유한 경우의 표면 형상을 나타내며, 도 1e는 100%의 저마늄을함유한 경우의 표면 형상을 나타낸다. 이때, 표면거칠기값(RMS)은 각각 14Å, 45Å, 47Å, 54Å및 223Å으로서, 도면에서도 알 수 있는 바와 같이, 폴리 실리콘저마늄 상부에 폴리실리콘막을 형성하는 것에 관계없이 저마늄 함량이 높을수록 표면거칠기값이 증대된다.1A to 1E are views illustrating the surface shape according to the germanium content of polysilicon germanium by AFM (Automatic Force Microscope) when the polysilicon film is formed on the polysilicon germanium. In the case of not containing germanium, that is, the surface shape of only the polysilicon film is shown, and FIGS. 1B to 1D show the surface shape when 20%, 40%, and 60% of germanium is contained, respectively. The surface shape in the case of containing 100% germanium is shown. At this time, the surface roughness values (RMS) are 14 kPa, 45 kPa, 47 kPa, 54 kPa and 223 kPa, respectively. The roughness value is increased.
따라서, 본 발명은 상기한 종래의 문제점을 해결하기 위한 것으로서, 폴리 실리콘저마늄의 표면특성을 향상시킬 수 있는 반도체 소자의 게이트 형성방법을 제공함에 그 목적이 있다.Accordingly, an object of the present invention is to provide a method for forming a gate of a semiconductor device capable of improving the surface characteristics of polysilicon germanium.
도 1a 내지 도 1e는 폴리 실리콘저마늄 상부에 폴리실리콘막을 형성한 경우폴리 실리콘저마늄의 저마늄 함량에 따른 표면 형상을 AFM로 관찰하여 나타낸 도면.1A to 1E are views illustrating the surface shape according to the germanium content of polysilicon germanium by AFM when a polysilicon film is formed on the polysilicon germanium.
도 2a 내지 도 2e는 본 발명의 실시예에 따른 반도체 소자의 게이트 형성방법을 설명하기 위한 단면도.2A to 2E are cross-sectional views illustrating a gate forming method of a semiconductor device in accordance with an embodiment of the present invention.
(도면의 주요부분에 대한 부호의 설명)(Explanation of symbols on the main parts of drawing
20 : 반도체 기판 21 : 게이트 산화막20 semiconductor substrate 21 gate oxide film
22 : 폴리 실리콘저마늄막 23 : 폴리실리콘막22 polysilicon germanium film 23 polysilicon film
100 : 게이트 24 : LDD 산화막100: gate 24: LDD oxide film
25A, 25B : LDD 영역 26 : 스페이서25A, 25B: LDD region 26: spacer
27A, 27B : 소오스 및 드레인27A, 27B: Source and Drain
상기한 본 발명의 목적을 달성하기 위하여, 본 발명에 따라, 본 발명에 따라, 반도체 기판 상에 게이트 산화막 및 도핑된 폴리 실리콘저마늄막을 순차적으로형성하고, 폴리 실리콘저마늄막을 일부 제거하여 그의 표면을 평탄화시킨다. 그런다음, 폴리 실리콘저마늄 상에 발생되는 자연산화막을 제거하고, 평탄화된 폴리 실리콘저마늄막 상부에 캡핑층으로서 폴리실리콘막을 형성한 후, 폴리실리콘막 및 폴리실리콘저마늄막을 식각하여 게이트를 형성한다.In order to achieve the above object of the present invention, according to the present invention, according to the present invention, a gate oxide film and a doped polysilicon germanium film are sequentially formed on a semiconductor substrate, and a part of the polysilicon germanium film is removed to remove its surface. Planarize. Then, the natural oxide film generated on the polysilicon germanium is removed, a polysilicon film is formed as a capping layer on the planarized polysilicon germanium film, and the polysilicon film and the polysilicon germanium film are etched to form a gate. .
이하, 첨부된 도면을 참조하여 본 발명의 실시예를 설명한다.Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention.
도 2a 내지 도 2e는 본 발명의 실시예에 따른 폴리 실리콘저마늄을 이용한 반도체 소자의 게이트 형성방법을 설명하기 위한 단면도이다.2A to 2E are cross-sectional views illustrating a gate forming method of a semiconductor device using polysilicon germanium according to an embodiment of the present invention.
도 2a를 참조하면, 반도체 기판(20) 상에 열산화공정으로 게이트 산화막(21)을 형성한다. 그런 다음, 게이트 산화막(21) 상에 실리콘의 소오스 개스로서 SiH4와 Si2H6를 이용하고 저마늄의 소오스 개스로서 GeH4를 사용하여 5 내지 1,000mTorr의압력에서 LPCVD(Low Pressure CVD), VLCVD(Very LPCVD), PE-VLPCVD(Plasma Enhanced-VLPCVD), UHVCVD(Ultrahigh Vacuum CVD), RTCVD(Rapid Thermal CVD), APCVD (Atmosphere Pressure CVD) 또는 MBE(Molecular Beam Epitaxy)로 도핑된 폴리 실리콘저마늄막(22)을 증착한다. 이때, 폴리 실리콘저마늄막(22)의 증착온도는 500 내지 700℃ 이고, 증착두께는 5,000 내지 7,000Å이며, 폴리 실리콘저마늄막(22) 내의 저마늄 함량은 10 내지 70%이다. 또한, 폴리 실리콘저마늄막(22)은 도펀트 개스를 이용한 인-시튜(in-situ)로 도핑하거나, 증착후 도펀트를 이온주입하는 익스-시튜 (ex-situ)로 도핑한다.Referring to FIG. 2A, a gate oxide film 21 is formed on a semiconductor substrate 20 by a thermal oxidation process. Then, low pressure CVD (LPCVD) at a pressure of 5 to 1,000 mTorr using SiH 4 and Si 2 H 6 as a source gas of silicon and GeH 4 as a source gas of germanium on the gate oxide film 21, Poly-silicon germanium film doped with VLCVD (Very LPCVD), PE-VLPCVD (Plasma Enhanced-VLPCVD), UHVCVD (Ultrahigh Vacuum CVD), RTCVD (Rapid Thermal CVD), APCVD (Atmosphere Pressure CVD) or MBE (Molecular Beam Epitaxy) (22) is deposited. At this time, the deposition temperature of the polysilicon germanium film 22 is 500 to 700 ° C, the deposition thickness is 5,000 to 7,000 kPa, and the germanium content in the polysilicon germanium film 22 is 10 to 70%. In addition, the polysilicon germanium film 22 is doped in-situ using a dopant gas or doped with ex-situ for ion implantation of the dopant after deposition.
도 2b를 참조하면, 화학기계연마(chemical mechanical polishing; CMP)로 폴리 실리콘저마늄막(22)을 일정 두께, 바람직하게 500 내지 1,000Å의 두께만큼 남도록 식각하여 폴리 실리콘저마늄막(22)의 표면을 평탄화시킨다. 그런 다음, 평탄화된 폴리 실리콘저마늄(22) 상에 발생되는 자연산화막(미도시)을 제거하고, 그 상부에 캡핑층(capping layer)으로서 폴리실리콘막(23)을 비교적 얇게, 바람직하게 100 내지 300Å의 두께로 형성한다. 즉, 폴리 실리콘저마늄막(22)의 표면을 평탄화시킨후 그 상부에 폴리실리콘막(23)을 증착함으로써, 양호한 표면 거칠기를 얻을 수 있게 된다.Referring to FIG. 2B, the surface of the polysilicon germanium film 22 is etched by chemical mechanical polishing (CMP) by etching the polysilicon germanium film 22 to a predetermined thickness, preferably 500 to 1,000 mm 3. Planarize. Then, a natural oxide film (not shown) generated on the planarized polysilicon germanium 22 is removed, and the polysilicon film 23 is relatively thin, preferably 100 to 100, as a capping layer thereon. It is formed to a thickness of 300Å. That is, by smoothing the surface of the polysilicon germanium film 22 and depositing the polysilicon film 23 thereon, good surface roughness can be obtained.
도 2c를 참조하면, 폴리실리콘막(23) 상에 포토리소그라피로 게이트 형태로포토레지스트 패턴(미도시)을 형성하고, 상기 포토레지스트 패턴을 식각 마스크로하여 폴리실리콘막(23), 폴리 실리콘저마늄막(22) 및 게이트 산화막(21)을 식각하여, 폴리 실리콘저마늄(22) 및 폴리실리콘막(23)으로 이루어진 게이트(100)를 형성한다.Referring to FIG. 2C, a photoresist pattern (not shown) is formed on the polysilicon film 23 in the form of a photolithography gate, and the polysilicon film 23 and the polysilicon film are formed using the photoresist pattern as an etching mask. The nium film 22 and the gate oxide film 21 are etched to form a gate 100 made of the polysilicon germanium 22 and the polysilicon film 23.
도 2d를 참조하면, 도 2c의 구조를 산화분위기에서 열처리하여 게이트(100)및 기판 표면 상에 LDD(lightly doped drain) 산화막(24)을 형성하고, 게이트(100)를 이온주입 마스크로하여 기판(20)으로 LDD 이온을 주입하여, 게이트(100) 양측의기판(20)에 LDD 영역(25A, 25B)을 형성한다.Referring to FIG. 2D, the structure of FIG. 2C is heat-treated in an oxidizing atmosphere to form a lightly doped drain (LDD) oxide film 24 on the gate 100 and the substrate surface, and the substrate 100 using the gate 100 as an ion implantation mask. LDD ions are implanted into the gate 20 to form the LDD regions 25A and 25B on the substrates 20 on both sides of the gate 100.
도 2e를 참조하면, 기판 전면에 CVD로 산화막을 두껍게 증착하고, 건식식각으로 식각하여 LDD 산화막(24)이 형성된 게이트(100)의 측벽에 스페이서(26)를 형성한다. 그런 다음, 게이트(100) 및 스페이서(26)를 이온주입 마스크로하여기판(20) 으로 고농도 불순물 이온을 주입하여 소오스 및 드레인(27A, 27B)을 형성한다.Referring to FIG. 2E, a thick oxide film is deposited on the entire surface of the substrate by CVD and etched by dry etching to form spacers 26 on sidewalls of the gate 100 on which the LDD oxide film 24 is formed. Then, high concentration impurity ions are implanted into the substrate 20 using the gate 100 and the spacers 26 as ion implantation masks to form the source and drains 27A and 27B.
상기한 본 발명에 의하면, 폴리 실리콘저마늄막을 두껍게 증착하고 그의 표면을 평탄화시킨 후 그 상부에 캡핑층으로서 폴리실리콘막을 증착함으로써, 양호한표면 거칠기를 얻을 수 있게 된다. 이에 따라, 소자특성의 열화가 방지되고 제조공정이 용이해짐으로써, 소자의 경박단소화 및 고집적화를 이룰 수 있게 된다.According to the present invention described above, a good surface roughness can be obtained by depositing a thick polysilicon germanium film and flattening its surface and then depositing a polysilicon film as a capping layer thereon. Accordingly, deterioration of device characteristics is prevented and the manufacturing process is facilitated, thereby making it possible to reduce the thickness of the device and to achieve high integration.
또한, 본 발명은 상기 실시예에 한정되지 않고, 본 발명의 기술적 요지를 벗어나지 않는 범위내에서 다양하게 변형시켜 실시할 수 있다.In addition, this invention is not limited to the said Example, It can variously deform and implement within the range which does not deviate from the technical summary of this invention.
Claims (11)
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