KR970054435A - Semiconductor device and manufacturing method - Google Patents

Semiconductor device and manufacturing method Download PDF

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Publication number
KR970054435A
KR970054435A KR1019950064535A KR19950064535A KR970054435A KR 970054435 A KR970054435 A KR 970054435A KR 1019950064535 A KR1019950064535 A KR 1019950064535A KR 19950064535 A KR19950064535 A KR 19950064535A KR 970054435 A KR970054435 A KR 970054435A
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KR
South Korea
Prior art keywords
gate
forming
oxide film
layer
gate oxide
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KR1019950064535A
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Korean (ko)
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KR100228330B1 (en
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김천수
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김주용
현대전자산업 주식회사
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Priority to KR1019950064535A priority Critical patent/KR100228330B1/en
Publication of KR970054435A publication Critical patent/KR970054435A/en
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Publication of KR100228330B1 publication Critical patent/KR100228330B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02293—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process formation of epitaxial layers by a deposition process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823412—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823418—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures

Abstract

본 발명은 반도체 소자 및 그 제조방법에 관한 것으로, 숏채널 효과를 억제하고 면저항을 감소시키기 위한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, to suppress short channel effects and reduce sheet resistance.

이를 위해 본 발명은 반도체 기판상에 에피택시층을 형성하는 단계와, 상기 에피택시층상에 게이트 산화막과 게이트 형성용 도전층을 차례로 형성하는 단계, 상기 도전층과 게이트 산화막 및 에피택시층을 소정의 게이트 패턴으로 패터닝하여 게이트를 형성하는 단계, 및 기판에 기판과 반대 도전형의 불순물을 이온주입하고 RTA처리를 행하여 소오스 및 드레인 영역을 형성하는 단계를 포함하여 이루어지는 것을 특징으로 하는 반도체 소자 제조방법을 제공한다.To this end, the present invention comprises the steps of forming an epitaxy layer on a semiconductor substrate, sequentially forming a gate oxide film and a gate forming conductive layer on the epitaxial layer, and forming the conductive layer, the gate oxide film and the epitaxy layer in a predetermined manner. Forming a gate by patterning the gate pattern; and implanting impurities of opposite conductivity type to the substrate and performing a RTA process to form source and drain regions. to provide.

Description

반도체 소자 및 그 제조방법Semiconductor device and manufacturing method

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도는 본 발명의 일실시예에 의한 반도체 소자 제조방법을 도시한 공정순서도이다.1 is a process flowchart showing a method of manufacturing a semiconductor device according to an embodiment of the present invention.

Claims (9)

반도체 기판과, 상기 반도체 기판 상부의 소정영역에 형성된 게이트 산화막, 상기 게이트 산화막상에 형성된 게이트, 상기 게이트 산화막과 기판 사이에 형성된 에피택시층, 및 상기 게이트 양단의 기판부위에 형성된 소오스 및 드레인 영역을 포함하는 것을 특징으로 하는 반도체 소자.A semiconductor substrate, a gate oxide film formed on a predetermined region over the semiconductor substrate, a gate formed on the gate oxide film, an epitaxy layer formed between the gate oxide film and the substrate, and a source and drain region formed on a substrate portion across the gate. A semiconductor device comprising a. 제1항에 있어서, 상기 에피택시층은 MOSFET의 채널영역에 형성되는 것을 특징으로 하는 반도체 소자.The semiconductor device of claim 1, wherein the epitaxy layer is formed in a channel region of a MOSFET. 제1항에 있어서, 상기 게이트와 소오스 및 드레인 영역의 표면상에 각각 형성된 에피택시층을 더 포함하는 것을 특징으로 하는 반도체 소자.The semiconductor device of claim 1, further comprising an epitaxial layer formed on surfaces of the gate and the source and drain regions, respectively. 반도체 기판상에 에피택시층을 형성하는 단계와, 상기 에피택시층상에 게이트 산화막과 게이트 형성용 도전층을 차례로 형성하는 단계, 상기 도전층과 게이트 산화막 및 에피택시층을 소정의 게이트패턴으로 패터닝하여 게이트를 형성하는 단계, 및 기판에 반대 도전형의 불순물을 이온주입하고 RTA 처리를 행하여 소오스 및 드레인 영역을 형성하는 단계를 포함하여 이루어지는 것을 특징으로 하는 반도체 소자 제조방법.Forming an epitaxial layer on the semiconductor substrate, sequentially forming a gate oxide film and a gate forming conductive layer on the epitaxial layer, and patterning the conductive layer, the gate oxide film, and the epitaxy layer with a predetermined gate pattern. Forming a gate; and forming a source and a drain region by implanting impurities of opposite conductivity into a substrate and performing RTA treatment. 제4항에 있어서, 상기 에피택시층은 UHV-CVD을 이용하여 형성하는 것을 특징으로 하는 반도체 소자 제조방법.The method of claim 4, wherein the epitaxy layer is formed using UHV-CVD. 제4항에 있어서, 상기 에피택시층은 보론을 도핑하여 형성하는 것을 특징으로 하는 반도체 소자 제조방법.The method of claim 4, wherein the epitaxy layer is formed by doping boron. 제6항에 있어서, 상기 보론의 농도는 1×1018cm-3정도로 유지하는 것을 특징으로 하는 반도체 소자 제조방법.The method of claim 6, wherein the concentration of boron is maintained at about 1 × 10 18 cm −3 . 제4항에 있어서, 상기 RTA처리는 1050℃ 정도의 온도에서 약 10초간 행하는 것을 특징으로 하는 반도체 소자 제조방법.The method of claim 4, wherein the RTA process is performed at a temperature of about 1050 ° C. for about 10 seconds. 제4항에 있어서, 상기 소오스 및 드레인 영역을 형성하는 단계후에 상기 게이트와 소오스 및 드레인 영역 표면상에 선택 에피택시층을 형성하는 단계가 더 포함되는 것을 특징으로 하는 반도체 소자 제조방법.5. The method of claim 4, further comprising forming a selective epitaxy layer on surfaces of the gate and source and drain regions after forming the source and drain regions. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950064535A 1995-12-29 1995-12-29 Mosfet device and a manufacturing method thereof KR100228330B1 (en)

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KR1019950064535A KR100228330B1 (en) 1995-12-29 1995-12-29 Mosfet device and a manufacturing method thereof

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KR1019950064535A KR100228330B1 (en) 1995-12-29 1995-12-29 Mosfet device and a manufacturing method thereof

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100498592B1 (en) * 1997-12-27 2006-04-28 주식회사 하이닉스반도체 Most transistors and manufacturing method thereof

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63284864A (en) * 1987-05-15 1988-11-22 Seiko Instr & Electronics Ltd Manufacture of insulated-gate field-effect transistor
JPS63269577A (en) * 1987-04-27 1988-11-07 Seiko Instr & Electronics Ltd Manufacture of insulated-gate field-effect transistor

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100498592B1 (en) * 1997-12-27 2006-04-28 주식회사 하이닉스반도체 Most transistors and manufacturing method thereof

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