KR920017241A - Manufacturing method of bi-mos SRAM cell - Google Patents

Manufacturing method of bi-mos SRAM cell Download PDF

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Publication number
KR920017241A
KR920017241A KR1019910002467A KR910002467A KR920017241A KR 920017241 A KR920017241 A KR 920017241A KR 1019910002467 A KR1019910002467 A KR 1019910002467A KR 910002467 A KR910002467 A KR 910002467A KR 920017241 A KR920017241 A KR 920017241A
Authority
KR
South Korea
Prior art keywords
sram cell
manufacturing
forming
mos
mos sram
Prior art date
Application number
KR1019910002467A
Other languages
Korean (ko)
Other versions
KR0161846B1 (en
Inventor
이용훈
Original Assignee
문정환
금성일렉트론 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 문정환, 금성일렉트론 주식회사 filed Critical 문정환
Priority to KR1019910002467A priority Critical patent/KR0161846B1/en
Publication of KR920017241A publication Critical patent/KR920017241A/en
Application granted granted Critical
Publication of KR0161846B1 publication Critical patent/KR0161846B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
    • H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
    • H01L27/0623—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with bipolar transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8248—Combination of bipolar and field-effect technology
    • H01L21/8249—Bipolar and MOS technology

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Memories (AREA)

Abstract

내용 없음No content

Description

바이-모스 에스램 셀의 제조방법Manufacturing method of bi-mos SRAM cell

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제3도는 본 발명의 바이-모스 에스램 셀의 기본 회로도, 제4도는 제3도에 있어서, 바이-모스 에스램 셀의 프로세스 공정도.3 is a basic circuit diagram of a bi-MOS SRAM cell of the present invention, and FIG. 4 is a process flowchart of a bi-MOS SRAM cell according to FIG. 3.

Claims (1)

실리콘 기판위에 선택적 산화에 의해 산화막을 형성한 후 포토레지스트에 의해 선택 에치하는 단계와, 상기 공정후 채널 이온을 주입하고 드레인을 형성한 후 폴리실리콘 게이트를 증착하는 단계와, 상기 공정후 포토레지스트에 의해 선택 에치하여 에피택셜을 성장시켜 소오스를 형성한 모스트랜지스터 및 바이폴라 트랜지스터를 형성하는 단계와, 상기 공정후 얇은 산화막을 형성하여 콘택홈을 파고 알루미늄 금속을 증착시키는 단계를 포함하여 이루어진 것을 특징으로 하는 바이-모스 에스램 셀의 제조방법.Forming an oxide film on the silicon substrate by selective oxidation, and then etching it by photoresist, implanting channel ions after the process and forming a drain, and then depositing a polysilicon gate; Forming an MOS transistor and a bipolar transistor in which a source is formed by growing the epitaxial layer by selective etching; Method for producing a bi-mos SRAM cell. ※참고사항:최초출원 내용에 의하여 공개하는 것임.※ Note: This is to be disclosed based on the first application.
KR1019910002467A 1991-02-13 1991-02-13 Fabricating method of bi-cmos sram KR0161846B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019910002467A KR0161846B1 (en) 1991-02-13 1991-02-13 Fabricating method of bi-cmos sram

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019910002467A KR0161846B1 (en) 1991-02-13 1991-02-13 Fabricating method of bi-cmos sram

Publications (2)

Publication Number Publication Date
KR920017241A true KR920017241A (en) 1992-09-26
KR0161846B1 KR0161846B1 (en) 1998-12-01

Family

ID=19311125

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019910002467A KR0161846B1 (en) 1991-02-13 1991-02-13 Fabricating method of bi-cmos sram

Country Status (1)

Country Link
KR (1) KR0161846B1 (en)

Also Published As

Publication number Publication date
KR0161846B1 (en) 1998-12-01

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