JPS6327947U

JPS6327947U -

Info

Publication number: JPS6327947U
Application number: JP12116386U
Authority: JP
Priority date: 1986-08-07
Filing date: 1986-08-07
Publication date: 1988-02-24

Description

[Brief explanation of the drawing]

第１図は本考案の実施例を示す回路図、第２図
は第１図の動作を示すタイミング図である。１……割込み要求ＦＦ、２……エツヂ切出し回
路、３……割込み許可ＦＦ、５，６……割込み受
付ＦＦ、８……第１のＦＦ、９……第２のＦＦ、
１０……タイマカウンタ、１１……異常動作受付
ＦＦ、１２……Ｒ―ＳＦＦ。 FIG. 1 is a circuit diagram showing an embodiment of the present invention, and FIG. 2 is a timing diagram showing the operation of FIG. 1. 1... Interrupt request FF, 2... Edge extraction circuit, 3... Interrupt permission FF, 5, 6... Interrupt reception FF, 8... First FF, 9... Second FF,
10...Timer counter, 11...Abnormal operation reception FF, 12...R-SFF.

Claims

[Scope of utility model registration request]

Interrupt request F set when an interrupt occurs
In the abnormal operation prevention circuit of a microprocessor having an interrupt function realized by F and an interrupt acceptance FF that executes an interrupt in an interrupt enabled state, the first signal is set by a signal generated at a constant cycle. FF, and a second FF that is set by the constant cycle signal generated when the first FF is in the set state.
FF, an abnormal operation reception FF that recognizes an abnormal operation by the set output of the second FF, and address specifying means for selecting a predetermined address of the program memory by the set output of the FF, and the abnormal operation reception FF An abnormal operation prevention circuit characterized in that interrupt processing of a program designated by the address designation means is executed by setting the interrupt acceptance FF with the set output of the address designation means.