JPS63273330A - Semiconductor device - Google Patents

Abstract

PURPOSE:To perform the failure analysis while preventing the destruction of the fine internal circuit wirings by the probe needles, the offset of the probe needles and the short circuit by contact with the adjoining wirings by providing lead wirings intersecting the internal circuit wirings through an insulating film, and small pads to be connected to the lead wirings. CONSTITUTION:On a semiconductor substrate 1, an internal circuit 2 is constituted by element regions 3a-3c and circuit wirings 5a-5d connected to the element electrodes 4a-4h thereof, and a plurality of bonding pads 6 are provided which are connected to the above predetermined circuit wirings to perform the transmission of the signal with external circuits and the supply of power. On the circuit 2, lead wirings 7a-7d intersecting the wirings 5a-5d through an insulating film are formed, and in the neighborhood of the pads 6, there are formed small pads 8a-8d which are respectively connected to the wirings 7a-7d and have an area smaller than the pads 6. And with the needles 9 of a testing equipment brought into contact with the pads 8a-8d, respectively, the signal transmission with the circuit 2 is performed to determine the operating condition of the circuit 2.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and particularly to a semiconductor device having fine circuit wiring.

[Conventional technology]

Conventionally, this type of semiconductor device has an internal circuit including a plurality of element regions formed on a semiconductor substrate, a plurality of circuit wirings connected to each element electrode of these element regions, and a predetermined circuit of this internal circuit. It is equipped with a bonding pad that connects to circuit wiring to transmit signals to external circuits, supply power, etc. When performing failure analysis, etc., the probe of the test equipment can be brought into contact with minute circuit wiring to transmit signals. and checked the operating status of the internal circuits.

[Problem that the invention seeks to solve]

In the conventional semiconductor device described above, during failure analysis, etc.
Since the probe of the test equipment is configured to touch fine circuit wiring to check the operating status of the internal circuit, there is no possibility that fine circuit wiring may break due to the stress caused by the pressure of the probe of the test equipment. However, there were disadvantages in that the probe could be displaced due to vibrations during testing or contact with the probe by an operator, and this could cause short circuits with adjacent circuit wiring.

Furthermore, there is a drawback in that it is difficult to bring a plurality of probes into contact with circuit wiring in a dense area.

An object of the present invention is to provide a semiconductor device that can prevent disconnection of circuit wiring, displacement of a probe, short circuit with adjacent wiring, etc. even in a dense area, and allows easy failure analysis. It is in.

[Means for solving problems]

A semiconductor device of the present invention includes an internal circuit including a plurality of element regions formed on a semiconductor substrate, a plurality of circuit wirings connected to each element electrode of these element regions, and a predetermined circuit wiring of this internal circuit. A plurality of bonding pads are connected to a plurality of bonding pads for transmitting signals with an external circuit, and a specific circuit wiring among the plurality of circuit wirings is disconnected from 8! It has a plurality of lead wires that intersect with each other through the film, and small pads that are connected to each of these lead wires and have a smaller area than the bonding pad and are used to contact the probe of the test device.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a layout diagram of a semiconductor chip showing an embodiment of the present invention.

On the semiconductor substrate, an internal circuit 2 is configured including element regions 3a to 3c and circuit wirings 5a to 5d that connect to element electrodes 4a to 4b of these element regions 3a to 3c. A plurality of bonding pads 6 are formed which are connected to predetermined circuit wiring to transmit signals to external circuits, supply power, and the like.

Circuit wirings 5a to 5d are provided on the internal circuit 2 via an insulating film.
Lead wires 7a to 7d intersecting with the bonding pads 6 are formed near the bonding pad 6, and are connected to the lead wires 7a to 7d, respectively, and have a smaller area than the bonding pads 6, and are used for contacting the probe of the test device. Small pad 8a
~8d is formed.

Next, the failure analysis method of this embodiment will be explained.

FIG. 2 is a plan view of the main parts of the semiconductor chip and test equipment for explaining the failure analysis method of this embodiment.

First, the part marked χ shown in the second diagram, that is, the circuit wiring 5a to
5d and the lead wires 7a to 7d are pressed somewhat strongly with a probe or the like to break the insulating film, thereby short-circuiting and connecting the circuit wires 5a to 5d and the lead wires 7a to 7d, respectively.

The probe 9 of the test device is brought into contact with each of the small pads 8a to 8d to transmit signals between the test device and the internal circuit 2, thereby confirming the operating state of the internal circuit 2.

FIG. 3 is an example of a circuit diagram centered on the element region 3a when the insulating film is destroyed and the circuit wires 5a to 5d and the lead wires 7a to 7d are connected. A case of a NAND circuit operated by three people is shown as the element region 3a.

As mentioned above, since the probe 9 is in contact with the small pads 8a to 8d, the fine circuit wiring 5a to 5d is not destroyed, and even if there is some vibration, the probe 9 is in contact with the small pads 8a to 8d.
It does not shift from 8d or come into contact with adjacent circuit wiring, and small pads can be pulled out to appropriate positions even in crowded areas, making it easy to analyze faulty wiring using multiple probes. become.

In the above embodiment, the circuit wiring and the lead wiring are connected one to one.
Although the configuration is such that one lead-out wiring can be connected to a plurality of circuit wirings, the configuration may be such that one lead-out wiring is provided for a plurality of circuit wirings, or vice versa. The multiple-to-one configuration has the advantage that the number of probes can be reduced.

Further, in the above embodiments, the small pads are placed between the bonding pads, but the small pads are not limited to this position, and may be placed at any other position as long as the probe can easily come into contact with them. Therefore, it is smaller than the bonding pad.

〔Effect of the invention〕

As explained above, the present invention includes a lead wire that intersects with a circuit wire constituting an internal circuit via an insulating film, and a small pad that connects to this lead wire. By destroying the small pad to connect the circuit wiring and the lead wiring, and transmitting the signal by contacting the probe of the test equipment with the small pad, it is possible to avoid the destruction of minute circuit wiring by the probe and the displacement of the probe. Also, it is possible to prevent short circuits due to contact with adjacent wiring, and it is possible to easily perform failure analysis even in a crowded area.

[Brief explanation of drawings]

FIG. 1 is a layout diagram of a semiconductor chip showing an embodiment of the present invention, and FIG. 2 is a plan view of main parts of a semiconductor chip and test equipment for explaining the failure analysis method of the embodiment shown in FIG. ,
FIG. 3 is a circuit diagram when each circuit wiring and lead wiring of the embodiment shown in FIG. 1 are connected. DESCRIPTION OF SYMBOLS 1... Semiconductor substrate, 2... Internal circuit, 3a-3b.
...Element area, 4a to 4h...Element electrode, 5a to 5d
...Circuit wiring, 6...Bonding pad, 7a~
7d...Output wiring, 8a-8d...Small pad, 9.
... Probe.

Claims (1)

[Claims] An internal circuit including a plurality of element regions formed on a semiconductor substrate, a plurality of circuit wirings connected to each element electrode of these element regions, and an external circuit connected to a predetermined circuit wiring of this internal circuit. a plurality of bonding pads that transmit signals; a plurality of lead wires that intersect with a specific circuit wire of the plurality of circuit wires via an insulating film; 1. A semiconductor device comprising a small pad smaller than the pad and for contacting a probe of a test device.