JPH0577333B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and particularly to a semiconductor device having fine circuit wiring.

[Conventional technology]

Conventionally, this type of semiconductor device has an internal circuit including a plurality of element regions formed on a semiconductor substrate, a plurality of circuit wirings connected to each element electrode of these element regions, and a predetermined circuit of this internal circuit. Equipped with a bonding pad that connects to circuit wiring to transmit signals to external circuits, supply power, etc. When performing failure analysis, etc., the probe of the test equipment can be brought into contact with minute circuit wiring to transmit signals. to check the operating status of the internal circuits.

[Problem that the invention seeks to solve]

The conventional semiconductor device described above is configured to check the operating state of the internal circuit by touching the probe of the test equipment to minute circuit wiring during failure analysis. Microcircuit wiring may break due to the stress caused by the pressure of the probe, the probe may become displaced due to vibration during testing or contact with the probe by the operator, or short circuits may occur with adjacent circuit wires. There was a drawback.

Another drawback is that it is difficult to bring a plurality of probes into contact with circuit wiring in a dense area.

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device that can prevent disconnection of circuit wiring, displacement of a probe, short circuit with adjacent wiring, etc. even in a crowded area, and allows easy failure analysis. It is in.

[Means for solving problems]

A semiconductor device of the present invention includes an internal circuit including a plurality of element regions formed on a semiconductor substrate, a plurality of circuit wirings connected to each element electrode of these element regions, and a predetermined circuit wiring of this internal circuit. A plurality of bonding pads that connect with the circuit to transmit signals with an external circuit, a plurality of lead wires that intersect with a specific circuit wire of the plurality of circuit wires via an insulating film, and each of these lead wires. and a small pad having a smaller area than the bonding pad and for contacting the probe of the test device.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a layout diagram of a semiconductor chip showing an embodiment of the present invention.

On the semiconductor substrate 1, element regions 3a to 3c,
Device electrodes 4a to 4b in these device regions 3a to 3c
The internal circuit 2 includes circuit wirings 5a to 5d connected to the internal circuit 2, and a plurality of bonding parts that connect to predetermined circuit wirings of the internal circuit 2 to transmit signals with external circuits, supply power, etc. 6 is formed.

Circuit wiring 5 is placed on the internal circuit 2 via an insulating film.
Lead wires 7a to 7d intersecting with the wires a to 5d are formed, and near the bonding pad 6 there are probes of the test equipment connected to the lead wires 7a to 7d, respectively, and having a smaller area than the bonding pads 6. Small pads 8a to 8d are formed for contacting.

Next, the failure analysis method of this embodiment will be explained.

FIG. 2 is a plan view of the main parts of the semiconductor chip and test equipment for explaining the failure analysis method of this embodiment.

First, the parts marked with X shown in the second diagram, that is, the intersections of the circuit wirings 5a to 5d and the extraction wirings 7a to 7d, are pushed a little forcefully with a probe or the like to break the insulating film, and the circuit wirings 5a to 5d and the extraction wirings are 7a to 7d are short-circuited and connected, respectively.

Then, connect the probe 9 of the test device to the small pads 8a to 8d.
The configuration is such that signals are transmitted between the test device and the internal circuit 2, and the operating state of the internal circuit 2 is confirmed.

Figure 3 shows circuit wiring 5a to 5d after the insulating film is destroyed.
This is an example of a circuit diagram centered on the element region 3a when the lead wires 7a to 7d are connected. A three-input NAND circuit is shown as the element region 3a.

As mentioned above, the probe 9 has small pads 8a to 8d.
Because it is in contact with the fine circuit wiring 5a to 5d
Even if there is some vibration, the probe 9 will not shift from the small pads 8a to 8d or come into contact with adjacent circuit wiring, and it will not damage the small pads even in dense areas. Since it can be pulled out to an appropriate position, failure wiring analysis using multiple probes can be easily performed.

In the above embodiment, the circuit wiring and the extraction wiring are connected one-to-one, but one extraction wiring may be provided for a plurality of circuit wirings, or vice versa. . The multiple-to-one configuration has the advantage that the number of probes can be reduced.

Further, in the above embodiment, the small pad is placed between the bonding pads, but it is not limited to this position, and may be placed at any other position as long as it is easily contacted by the probe. For this reason, it is made smaller than the bonding pad.

〔Effect of the invention〕

As explained above, the present invention provides a lead wire that intersects with a circuit wire constituting an internal circuit via an insulating film, and a small pad to which the lead wire connects.
For failure analysis, etc., the insulating film at the intersection is destroyed, the circuit wiring and the lead wiring are connected, and the probe of the test equipment is brought into contact with the small pad to transmit the signal. It is possible to prevent destruction of circuit wiring, displacement of the probe, contact short circuit with adjacent wiring, etc., and it is possible to easily perform failure analysis even in a crowded area.

[Brief explanation of drawings]

FIG. 1 is a layout diagram of a semiconductor chip showing an embodiment of the present invention, and FIG. 2 is a plan view of essential parts of a semiconductor chip and test equipment for explaining the failure analysis method of the embodiment shown in FIG. , FIG. 3 is a circuit diagram when each circuit wiring and lead wiring of the embodiment shown in FIG. 1 are connected, respectively. 1...Semiconductor substrate, 2...Internal circuit, 3a-3
b...Element region, 4a to 4h...Element electrode, 5a
~5d...Circuit wiring, 6...Bonding pad, 7a-7d...Outgoing wiring, 8a-8d...Small pad, 9...Tip.

Claims (1)

[Claims] 1. An internal circuit including a plurality of element regions formed on a semiconductor substrate, a plurality of circuit wirings connected to each element electrode of these element regions, and an external circuit connected to a predetermined circuit wiring of this internal circuit. a plurality of bonding pads for transmitting signals to and from a plurality of bonding pads, a plurality of lead wires that intersect with a specific circuit wire of the plurality of circuit wires via an insulating film, and a wire connected to each of the lead wires and having an area of 1. A semiconductor device comprising a small pad smaller than the bonding pad and for contacting a probe of a test device.