JPS63268256A - Diffusion method for aluminum - Google Patents

Diffusion method for aluminum

Info

Publication number
JPS63268256A
JPS63268256A JP10194687A JP10194687A JPS63268256A JP S63268256 A JPS63268256 A JP S63268256A JP 10194687 A JP10194687 A JP 10194687A JP 10194687 A JP10194687 A JP 10194687A JP S63268256 A JPS63268256 A JP S63268256A
Authority
JP
Japan
Prior art keywords
aluminum
polycrystalline silicon
wiring
etching
stuck
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10194687A
Other languages
Japanese (ja)
Inventor
Atsushi Numata
敦 沼田
Yutaka Misawa
三沢 豊
Hideo Honma
本間 秀男
Naohiro Monma
直弘 門馬
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Hitachi Power Semiconductor Device Ltd
Original Assignee
Hitachi Ltd
Hitachi Haramachi Electronics Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd, Hitachi Haramachi Electronics Ltd filed Critical Hitachi Ltd
Priority to JP10194687A priority Critical patent/JPS63268256A/en
Publication of JPS63268256A publication Critical patent/JPS63268256A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE:To enable the aluminum wiring with fine wiring width dimension, by turning polycrystalline silicon into amorphous silicon, or making the crystal grain diameter sufficiently smaller than the wiring width, and making aluminum grow uniformly in the polycrystalline silicon. CONSTITUTION:In the active region of a semiconductor substrate 1, a gate oxide film 2 is formed with a thickness of, e.g., 100Angstrom a contact part is subjected to etching, and an N<+> region 3 is formed by applying the mask used in said etching. Polycrystalline silicon 4 is stuck with a thickness of 2000Angstrom , and element to turn the polycrystalline silicon into amorphous silicon, e.g., oxygen 5 is introduced. By etching the polycrystalline silicon 4, a wiring pattern is formed. By applying this wiring pattern to a mask, an N<-> region 6 is formed to constitute an LDD structure. An interlayer insulating film, e.g., an oxide film 7 is stuck with a thickness of 3000Angstrom to form a contact part. Aluminum 8 is stuck and subjected to etching to form a pattern. When a MOSFET formed in this manner is subjected to a heat-treating for about 10 hours at a temperature of 450 deg.C, aluminum diffuses uniformly into the polycrystalline silicon, and an aluminum wiring is formed.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明はアルミニウム拡散方法に係り、特に半導体装置
の配線を形成するのに好適なアルミニウム拡散方法に関
する。
DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to an aluminum diffusion method, and particularly to an aluminum diffusion method suitable for forming wiring of a semiconductor device.

〔従来の技術〕[Conventional technology]

従来、アルミニウム配線形成方法については、アイ・イ
ー・イー・イー、トランザクション オン エレクトロ
ン、デバイス ポル イー・ディー31.ナンバー6、
シュン 1984年 第828頁から第831頁(IE
EE、 Trans、 o n 。
Conventional methods for forming aluminum wiring are described in IE, Transaction on Electron, Device Pol ED 31. number 6,
Shun 1984, pp. 828-831 (IE
EE, Trans, on.

Electron  Device、Vol、ED−3
]、No6 JUNE1984P828〜831)にお
いて論じられている。すなわち多結晶シリコンゲートの
MOSFETを、アルミニウムと多結晶シリコンの低温
熱処理での反応を利用して、アルミニウムゲートに置き
変える技術である。この技術は、アルミニウムの融点以
下の温度が熱処理することにより、多結晶シリコンとア
ルミニウムの接触部分からアルミニウムが多結晶シリコ
ン中へ成長することにより形成される。
Electron Device, Vol, ED-3
], No. 6 JUNE 1984 P828-831). In other words, this is a technique for replacing a polycrystalline silicon gate MOSFET with an aluminum gate by utilizing the reaction between aluminum and polycrystalline silicon during low-temperature heat treatment. In this technique, aluminum is formed from a contact area between polycrystalline silicon and aluminum by growing into polycrystalline silicon through heat treatment at a temperature below the melting point of aluminum.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

上記従来技術では、多結晶シリコンの結晶粒の大きさの
違いによりアルミニウムが均一に成長しない点について
配慮がされておらず、アルミニウムの成長が多結晶シリ
コンの結晶粒界を通る成長のため、配線幅が結晶粒径と
同等に狭いとアルミニウムの成長がその部分で止まって
しまうことから、ゲート長が微細な寸法のアルミニウム
ゲートのMOSFETを形成できないという問題があっ
た。
In the above conventional technology, no consideration is given to the fact that aluminum does not grow uniformly due to differences in the crystal grain size of polycrystalline silicon, and because aluminum grows through the grain boundaries of polycrystalline silicon, wiring If the width is as narrow as the crystal grain size, the growth of aluminum will stop at that portion, so there is a problem that an aluminum gate MOSFET with a minute gate length cannot be formed.

本発明の目的は、多結晶シリコンをアモリファス化或い
は結晶粒径を配線幅より十分小さくし、アルミニウムが
多結晶シリコン中を均一に成長することにより、配線幅
が微細な寸法のアルミニウム配線を形成するのに好適な
アルミニウム拡散方法を提供することにある。
The purpose of the present invention is to form aluminum wiring with a fine wiring width by making polycrystalline silicon amorphous or making the crystal grain size sufficiently smaller than the wiring width so that aluminum grows uniformly in the polycrystalline silicon. The object of the present invention is to provide an aluminum diffusion method suitable for

〔問題点を解決するための手段〕[Means for solving problems]

上記目的は、多結晶シリコン被膜時と高温熱処理時に多
結晶シリコンの結晶粒径が成長しないように、多結晶シ
リコン被膜時に酸素、窒素、フッ素、アルゴンを添加さ
せておくことにより達成される。或いは多結晶シリコン
を被膜後にイオン打込み法により酸素、窒素、フッ素、
アルゴンを注入して、多結晶シリコンの結晶粒径を小さ
くするか、多量に注入することによりアモルファス化し
てもよい。ここで好ましくは、多結晶シリコンをアモル
ファス化する注2人量としては]−Q20個/d以上で
あることが望ましい。
The above object is achieved by adding oxygen, nitrogen, fluorine, and argon during the polycrystalline silicon coating so that the crystal grain size of the polycrystalline silicon does not grow during the polycrystalline silicon coating and high-temperature heat treatment. Alternatively, after coating polycrystalline silicon, oxygen, nitrogen, fluorine,
Argon may be implanted to reduce the crystal grain size of polycrystalline silicon, or it may be made amorphous by implanting a large amount of argon. Here, it is preferable that the number of people needed to turn the polycrystalline silicon into amorphous is -Q20 pieces/d or more.

〔作用〕[Effect]

多結晶シリコンで形成した配線部に多結晶シリコンをア
モルファス化する元素を、少なくとも一種類含有せしめ
ることにより多結晶シリコンがアモルファス化しアルミ
ニウムが多結晶シリコン中を均一に成長する。それによ
って、多結晶シリコンで形成した配線部がアルミニウム
に置き換わり配線幅が微細な寸法のアルミニウム配線を
形成することができる。また、アルミニウムの成長速度
は多結晶シリコンをアモルファス化する元素を含有しな
い場合と同等以上であるため、配線長が長い場合でも歩
留りは高い。
By containing at least one element that makes polycrystalline silicon amorphous in a wiring portion formed of polycrystalline silicon, polycrystalline silicon becomes amorphous and aluminum grows uniformly in polycrystalline silicon. As a result, the wiring portion formed of polycrystalline silicon is replaced with aluminum, and an aluminum wiring with a fine wiring width can be formed. In addition, the growth rate of aluminum is equal to or higher than that in the case where the element that turns polycrystalline silicon into an amorphous state is not included, so the yield is high even when the wiring length is long.

〔実施例〕〔Example〕

以下、本発明の実施例を図面を用いて説明する。 Embodiments of the present invention will be described below with reference to the drawings.

第1図は本発明を用いてアルミニウムゲートのMOSF
ETを形成した例である。まず第1図(a)に示すよう
に半導体基板1の活性領域にゲート酸化膜2を例えば1
00人を形成し、コンタクト部をエツチングし、さらに
この時のマスクを用いて例えばn十領域3を形成する。
Figure 1 shows an aluminum gate MOSF using the present invention.
This is an example of forming an ET. First, as shown in FIG.
00 layers are formed, a contact portion is etched, and further, using the mask used at this time, for example, an n+ region 3 is formed.

次に多結晶シリコン4を2000人被着し、その後多結
晶シリコンをアモルファス化する元素、例えば酸素5を
・例えば1019個/d導入する。次に第1図(b)に
示すように多結晶シリコン4をエツチングし配線バタ−
ンを形成する。次にこの配線パターンをマスクにn−領
域6を形成しLDD構造とする。次に第1図(c)に示
すように層間絶縁膜例えば酸化膜7を3000 A被着
し、アルミニウム8と多結晶シリコン4を接触させるべ
きコンタク!・部を形成する。
Next, 2000 layers of polycrystalline silicon 4 are deposited, and then an element for making the polycrystalline silicon amorphous, such as oxygen 5, is introduced at 1019 atoms/d. Next, as shown in FIG. 1(b), the polycrystalline silicon 4 is etched to form a wiring pattern.
form a formation. Next, using this wiring pattern as a mask, an n- region 6 is formed to form an LDD structure. Next, as shown in FIG. 1(c), an interlayer insulating film such as an oxide film 7 is deposited at a thickness of 3000 A, and a contact is made to bring the aluminum 8 and the polycrystalline silicon 4 into contact!・Form a part.

次にアルミニウム8を被着しエツチングしてパターンを
形成する。このようにして形成したMOSFETを例え
ば450℃で10時間程度熱処理すると第1図(d)に
示すようにアルミニウムが多結晶シリコン中を均一に拡
散してアルミニウム配線が形成される。このようにして
形成したアルミニウム配線のMOSFETは、配線抵抗
を低減する効果があり、さらに仕事関数も小さくするこ
とができる6〔発明の効果〕 本発明によればアルミニウムが拡散した配線抵抗は、多
結晶シリコンの配線抵抗より充分小さく仕事関数も小さ
いので、LSI素子の性能が向−ヒする。
Next, aluminum 8 is deposited and etched to form a pattern. When the MOSFET thus formed is heat-treated at, for example, 450° C. for about 10 hours, aluminum is uniformly diffused in the polycrystalline silicon to form an aluminum wiring as shown in FIG. 1(d). The MOSFET with aluminum wiring formed in this way has the effect of reducing the wiring resistance and can further reduce the work function.6 [Effects of the Invention] According to the present invention, the wiring resistance in which aluminum is diffused is Since it is sufficiently smaller than the wiring resistance of crystalline silicon and has a smaller work function, it improves the performance of LSI devices.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明を適用したアルミニウム配線形成工程図
である。 1・・・半導体基板、2・ゲート酸化膜、3・・・n十
領域、4・・・多結晶シリコン、5・・・酸素、6・・
n−領域、7・・・酸化膜、8・・・アルミニウム。
FIG. 1 is a process diagram for forming aluminum wiring to which the present invention is applied. DESCRIPTION OF SYMBOLS 1... Semiconductor substrate, 2... Gate oxide film, 3... N+ region, 4... Polycrystalline silicon, 5... Oxygen, 6...
n- region, 7... Oxide film, 8... Aluminum.

Claims (1)

【特許請求の範囲】[Claims] 1、アルミニウムを多結晶シリコン中へ拡散させる方法
において、前記多結晶シリコン中へ酸素、窒素、フッ素
、アルゴンのうちの少なくとも一種類の元素を導入させ
ることを特徴とするアルミニウムの拡散方法。
1. A method for diffusing aluminum into polycrystalline silicon, the method comprising introducing at least one element among oxygen, nitrogen, fluorine, and argon into the polycrystalline silicon.
JP10194687A 1987-04-27 1987-04-27 Diffusion method for aluminum Pending JPS63268256A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10194687A JPS63268256A (en) 1987-04-27 1987-04-27 Diffusion method for aluminum

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10194687A JPS63268256A (en) 1987-04-27 1987-04-27 Diffusion method for aluminum

Publications (1)

Publication Number Publication Date
JPS63268256A true JPS63268256A (en) 1988-11-04

Family

ID=14314063

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10194687A Pending JPS63268256A (en) 1987-04-27 1987-04-27 Diffusion method for aluminum

Country Status (1)

Country Link
JP (1) JPS63268256A (en)

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