JPS63263736A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS63263736A
JPS63263736A JP62097329A JP9732987A JPS63263736A JP S63263736 A JPS63263736 A JP S63263736A JP 62097329 A JP62097329 A JP 62097329A JP 9732987 A JP9732987 A JP 9732987A JP S63263736 A JPS63263736 A JP S63263736A
Authority
JP
Japan
Prior art keywords
semiconductor chip
wiring
chip
semiconductor
mounting substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62097329A
Other languages
Japanese (ja)
Inventor
Keiji Sasaki
佐々木　圭治
Minoru Enomoto
榎本　実
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP62097329A priority Critical patent/JPS63263736A/en
Priority to KR88003425A priority patent/KR960012649B1/en
Priority to DE88303160T priority patent/DE3882074T2/en
Priority to EP88303160A priority patent/EP0288186B1/en
Priority to SG1995905451A priority patent/SG36588G/en
Priority to DE3856019T priority patent/DE3856019T2/en
Priority to EP92112517A priority patent/EP0516185B1/en
Publication of JPS63263736A publication Critical patent/JPS63263736A/en
Priority to US07/627,881 priority patent/US5191224A/en
Priority to US07/960,848 priority patent/US5309011A/en
Priority to KR93004115A priority patent/KR970001885B1/en
Priority to HK28096A priority patent/HK28096A/en
Priority to HK98101603A priority patent/HK1003348A1/en
Pending legal-status Critical Current

Links

Classifications

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE:To enhance the reliability upon the connection between semiconductor chips and a mounting substrate by a method wherein the semiconductor chips and the mounting substrate are connected with bonding wires. CONSTITUTION:A plurality of pads 5 composed of laminate of the first layer aluminum films and the second layer aluminum films are arranged around semiconductor chips on a mounting substrate 1. Likewise, a plurality of bonding pads 7 composed of laminate of the first layer aluminum films and the second layer aluminum films are arranged. Then, bonding pads 5 on the mounting substrate 1 are connected by bonding wires 6 made of e.g. gold (Au) wires, silver plated aluminum wires etc. Thus, said connections can be reinforced to enhance the reliability upon the connection between the semiconductor chips and the mounting substrate 1.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、半導体装置に関し、特に、複数の半導体チッ
プを塔載基板に塔載（モジュール）シ。DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a semiconductor device, and particularly to a module in which a plurality of semiconductor chips are mounted on a mounting substrate.

それらを同一のパッケージで封止する半導体装置に適用
して有効な技術に関するものである。The present invention relates to a technique that is effective when applied to semiconductor devices in which these devices are sealed in the same package.

〔従来技術〕[Prior art]

半導体チップの高密度実装を図るために、１つのパッケ
ージ内に複数の半導体チップをモジュールすることが行
なわれている。パッケージ内のそれぞれの半導体チップ
は、マザーチップ上にマウントされる。マザーチップ上
にはアルミニウム配線が延在し、半導体チップの間を接
続している。In order to achieve high-density packaging of semiconductor chips, a plurality of semiconductor chips are modularized within one package. Each semiconductor chip within the package is mounted on a mother chip. Aluminum wiring extends over the mother chip and connects the semiconductor chips.

アルミニウム配線と半導体チップの間は、金（ＡＵ）や
半田等からなるバンプ電極によって接続している。The aluminum wiring and the semiconductor chip are connected by bump electrodes made of gold (AU), solder, or the like.

なお、１つのパッケージ内に複数の半導体チップをマウ
ントした例は１例えば、特願昭５９−５４２０８号に記
載されている。An example of mounting a plurality of semiconductor chips in one package is described in, for example, Japanese Patent Application No. 59-54208.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

本発明者は、半導体チップをバンプ電極によってマザー
チップに接続した半導体装置について検討した結果１次
の問題点を見出した。The inventor of the present invention discovered the first problem as a result of studying a semiconductor device in which a semiconductor chip is connected to a mother chip by a bump electrode.

前記バンプ電極を構成する金や半田と、アルミニウム配
線の１■ｉにはタングステンやチタン等からなる下地膜
が設けられる。これは、金や半田がアルミニウム膜を覆
う酸化シリコン膜から剥がれ易いためである。ところが
、金や半田と、下地膜としてのタングステンやチタンと
の被着性は、アルミニウム膜又は金等からなるボンディ
ングワイヤと、アルミニウム膜からなるボンディングパ
ッドとの被着力より弱く、剥れやすい。このため、半導
体チップがマザーチップから剥れることが起る。A base film made of tungsten, titanium, or the like is provided on the gold or solder constituting the bump electrode and on the aluminum wiring 1i. This is because gold and solder easily peel off from the silicon oxide film covering the aluminum film. However, the adhesion between gold or solder and tungsten or titanium as a base film is weaker than the adhesion between an aluminum film or a bonding wire made of gold, etc., and a bonding pad made of an aluminum film, and is easily peeled off. As a result, the semiconductor chip may peel off from the mother chip.

また、半導体チップとマザーチップの間にバンプ？Ｉｉ
極が介在するため、半導体チップとマザーチップの間に
間隙を生じ、放熱効果が低下する。これは、同一パッケ
ージ内に複数の半導体チップを設けた場合、パッケージ
内の温度を著しく上昇させる。Also, a bump between the semiconductor chip and the mother chip? Ii
Due to the presence of the poles, a gap is created between the semiconductor chip and the mother chip, reducing the heat dissipation effect. This significantly increases the temperature inside the package when a plurality of semiconductor chips are provided in the same package.

本発明の目的は、半導体チップと塔載基板との間の接続
の信頼性を高めることにある。An object of the present invention is to improve the reliability of the connection between a semiconductor chip and a mounting board.

本発明の他の目的は、複数の半導体チップを内蔵する半
導体装置の放熱効果を高めることにある。Another object of the present invention is to improve the heat dissipation effect of a semiconductor device incorporating a plurality of semiconductor chips.

本発明の前記ならびにその他の目的と新規な特徴は、不
明ｍ書の記述及び添付図面によって明らかになるであろ
う。The above-mentioned and other objects and novel features of the present invention will become apparent from the description of the book and the accompanying drawings.

〔問題点を解決するための手段〕[Means for solving problems]

本願において開示される発明のうち、代表的なものの概
要を簡単に説明すれば、下記のとおりである。A brief overview of typical inventions disclosed in this application is as follows.

すなわち、半導体チップとこれが接続される塔載基板上
の配線の間をボンディングワイヤで接続するものである
。That is, a bonding wire is used to connect a semiconductor chip and wiring on a mounting board to which it is connected.

〔作用〕[Effect]

上述した手段によれば、半導体チップ上のボンディング
パッドとボンディングワイヤの接続及びボンディングワ
イヤと塔載基板上のボンディングパッドの接続が強固で
あるので、半導体チップと塔載基板の間の接続の信頼性
を高めることができる。According to the above-mentioned means, since the connection between the bonding pad on the semiconductor chip and the bonding wire and the connection between the bonding wire and the bonding pad on the mounting board are strong, the reliability of the connection between the semiconductor chip and the mounting board is improved. can be increased.

また、半導体チップの裏面が塔載基板に接着されるので
、半導体チップから発する熱の放熱効果を高めることが
できる。Furthermore, since the back surface of the semiconductor chip is bonded to the mounting substrate, the heat dissipation effect of the heat emitted from the semiconductor chip can be enhanced.

〔発明の実施例〕[Embodiments of the invention]

以下１本発明の一実施例を図面を用いて説明する。 An embodiment of the present invention will be described below with reference to the drawings.

第１図は、半導体ウェハからなる塔載基板上に複数の半
導体チップを塔載したときの前記塔載基板の平面図。FIG. 1 is a plan view of a mounting substrate made of a semiconductor wafer when a plurality of semiconductor chips are mounted on the mounting substrate.

第２図は、前記塔載基板の一部を拡大して示した平面図
。FIG. 2 is an enlarged plan view of a part of the tower-mounted substrate.

第３図は、前記塔載基板を前記半導体チップを通る線で
切断したときの断面図である。FIG. 3 is a cross-sectional view of the mounting substrate taken along a line passing through the semiconductor chip.

第１図乃至第３図に示すように、本実施例の半導体装置
は、単結晶シリコンの半導体ウェハからなる塔載基板１
上に単結晶シリコンからなる半導体チップＣｈｉｐｔ！
：複数塔載して構成している。As shown in FIGS. 1 to 3, the semiconductor device of this embodiment has a mounting substrate 1 made of a single-crystal silicon semiconductor wafer.
On top is a semiconductor chip made of single crystal silicon.
: It is composed of multiple towers.

それぞれの半導体チップＣｈ　ｉ　ｐの間は、半導体チ
ップＣｈ　ｉ　ｐ間を接続する第１層目のアルミニウム
膜からなる配線４ｘ及び第２層目のアルミニウム膜から
なる配線４ｙが延在する配線領域３である。配線４ｘが
延在する方向をＸ方向とすると、配ａ４ｙが延在する方
向はＹ方向である。すなわち、配Ｍ４ｘ、４ｙは互いに
交差するように延在している。配線４ｘ、４ｙは、半導
体チップｃｈｉｐの下は延在していない。第１層目の配
線４Ｘは、塔載基板１に例えばＣＶＤ等によって形成し
た酸化シリコン膜等からなる絶ｍ膜８の上を延在してい
る。配線４ｘと第２層目の配ＩＩＡ４ｙのＩＩ＋は、例
えばＣＶＤによる酸化シリコン膜等からなる絶縁膜９が
絶縁している。さらに、配線４ｙの上は、例えばＣＶＤ
による酸化シリコン膜等からなる最終保護膜１０が覆っ
ている。なお、配線４ｘと配線４ｙの接続は、絶縁＋１
！！９を除去して形成した接続孔を通してなされる６塔
載基板１の周辺には、第１層目のアルミニウム膜２ｘと
第２層目のアルミニウム膜２ｙを積層して構成したボン
ディングパッド２が複数設けられている。アルミニウム
膜２Ｘは絶縁膜８の上に設けられ、またアルミニウム膜
２ｙは絶縁膜９を除去してなる接続孔１１を通して、ア
ルミニウム配線２ｘに接続される。ボンディングパッド
２に前記配線４Ｘまた４ｙが接続している。ボンディン
グパッド２に配ｍ４ｘが接続する場合には、その配線４
ｘはボンディングパッド２の下の部分を構成しているア
ルミニウム膜２Ｘと一体に形成される。ボンディングパ
ッド２に配線４ｙが接続する場合には、その配線４ｙは
ボンディングパッド２の上の部分を構成しているアルミ
ニウム膜２ｙと一体に形成されている。最終保護膜１０
はボンディングパッド２の上では除去されて、開口１２
となっている。Between the respective semiconductor chips Ch i p, there is a wiring region 3 in which a wiring 4x made of a first layer aluminum film and a wiring 4y made of a second layer aluminum film which connect the semiconductor chips Ch i p extend. It is. If the direction in which the wiring 4x extends is the X direction, the direction in which the wiring a4y extends is the Y direction. That is, the lines M4x and M4y extend to intersect with each other. The wirings 4x and 4y do not extend below the semiconductor chip chip. The first layer wiring 4X extends over an insulating film 8 made of a silicon oxide film or the like formed on the mounting substrate 1 by, for example, CVD or the like. The wiring 4x and II+ of the second layer wiring IIA4y are insulated by an insulating film 9 made of, for example, a silicon oxide film formed by CVD. Further, on the wiring 4y, for example, CVD
A final protective film 10 made of a silicon oxide film or the like is covered. Note that the connection between the wiring 4x and the wiring 4y is insulation +1
! ! A plurality of bonding pads 2 are formed by laminating a first layer of aluminum film 2x and a second layer of aluminum film 2y around the 6-layer substrate 1, which is formed through the connection hole formed by removing 9. It is provided. The aluminum film 2X is provided on the insulating film 8, and the aluminum film 2y is connected to the aluminum wiring 2x through a connection hole 11 formed by removing the insulating film 9. The wiring 4X or 4y is connected to the bonding pad 2. When wiring m4x is connected to bonding pad 2, the wiring 4
x is formed integrally with the aluminum film 2X constituting the lower part of the bonding pad 2. When the wiring 4y is connected to the bonding pad 2, the wiring 4y is formed integrally with the aluminum film 2y forming the upper part of the bonding pad 2. Final protective film 10
is removed above bonding pad 2 and opening 12 is removed.
It becomes.

塔載基板１の半導体チップＣｈｉｐの周囲に。Around the semiconductor chip Chip on the mounting board 1.

第１層目のアルミニウム膜５ｘと第２層目のアルミニウ
ム膜５ｙを積層して構成したボンディングパッド５が複
数配置されている。アルミニウム膜５Ｘは絶縁ｍ８上に
ある。アルミニウム膜５ｙは接続孔１１を通してアルミ
ニウム膜５ｘに接続している。ボンディングパッド５は
開口１２から露出している。ボンディングパッド５には
配線４ｘ又は４ｙが接続している。配線４ｘがボンディ
ングパッド５に接続する場合には、そのボンディングパ
ッド５の下の部分を構成するアルミニウム膜５ｘと配線
４ｘが一体に形成される。配線４ｙがボンディングパッ
ド５に接続する場合には、そのボンディングパッド５の
上の部分を構成するアルミニウム層５ｙと配線４ｙが一
体に形成される。塔載基板工の表面にはＭＩＳＦＥＴ、
バイポーラトランジスタ、抵抗素子、容量素子等の素子
が構成されていない、しかし、塔載基板１の表面部のう
ち、半導体チップＣｈ　ｉ　ｐを載置する領域以外の部
分には抵抗素子や容量素子を形成するようにしてもよい
。A plurality of bonding pads 5 are arranged by laminating a first layer of aluminum film 5x and a second layer of aluminum film 5y. The aluminum film 5X is on the insulation m8. The aluminum film 5y is connected to the aluminum film 5x through the connection hole 11. Bonding pad 5 is exposed through opening 12. A wiring 4x or 4y is connected to the bonding pad 5. When the wiring 4x is connected to the bonding pad 5, the aluminum film 5x forming the lower part of the bonding pad 5 and the wiring 4x are integrally formed. When the wiring 4y is connected to the bonding pad 5, the aluminum layer 5y forming the upper part of the bonding pad 5 and the wiring 4y are integrally formed. MISFET,
Elements such as bipolar transistors, resistive elements, and capacitive elements are not configured. However, resistive elements and capacitive elements are not configured on the surface of the mounting substrate 1 other than the area where the semiconductor chip Ch i p is mounted. You may form it.

半導体チップＣｈ　ｉ　ｐは、最終保護膜１０の上に例
えばシリコーンゴム等からなる接着剤１３によって接着
されている。接着剤１３にシリコーンゴムを用いること
によって半導体チップＣｈｉｐに加る応力を少くしてい
る。半導体チップＣｈｉｐの周辺に、ボンディングパッ
ド７が複数配置されている。このボンディングパッド７
は、例えば第１層目のアルミニウム膜と第２層目のアル
ミニウム膜を積層して構成しである。なお、半導体チッ
プＣｈｉｐの表面にはｌＭＩＳＦＥＴ、バイポーラトラ
ンジスタ、抵抗素子、容量素子が多数設けられている。The semiconductor chip Ch i p is bonded onto the final protective film 10 with an adhesive 13 made of silicone rubber or the like. By using silicone rubber for the adhesive 13, stress applied to the semiconductor chip is reduced. A plurality of bonding pads 7 are arranged around the semiconductor chip Chip. This bonding pad 7
For example, it is constructed by laminating a first layer of aluminum film and a second layer of aluminum film. Note that a large number of lMISFETs, bipolar transistors, resistance elements, and capacitance elements are provided on the surface of the semiconductor chip Chip.

また、それらの間を素子分離するために、例えば熱酸化
による酸化シリコン膜からなるフィールド絶縁膜が形成
されている。さらには、前記素子間を接続するために、
例えばＣＶＤによる多結晶シリコン膜、スパッタによる
アルミニウム膜等からなる配線が延在している。下の配
線と上の配線の間は、例えばＣＶＤによる酸化シリコン
膜からなる絶縁膜が絶縁している。すなわち１図示して
いないが、ボンディングパッド７の下の部分を構成して
いる第１層目のアルミニウム層の下には、例えばＣＶＤ
による酸化シリコン膜からなり例えばＭＩＳＦＥＴのゲ
ート電極を覆っている第１層目の絶縁膜がある。半導体
チップＣｈ　ｉ　ｐの上は１例えばＣＶＤによる酸化シ
リコン膜、塗布ガラス（ＳＯＧ）膜、スパッタによる窒
化シリコン膜等を積層して構成した最終保護膜１４が覆
っている。最終保護膜１４は、ボンディングパッド７の
上では選択的に除去されて開口１５となっている。Further, in order to isolate elements between them, a field insulating film made of, for example, a silicon oxide film formed by thermal oxidation is formed. Furthermore, in order to connect the elements,
For example, wiring made of a polycrystalline silicon film formed by CVD, an aluminum film formed by sputtering, etc. extends. An insulating film made of, for example, a silicon oxide film formed by CVD provides insulation between the lower wiring and the upper wiring. In other words, although not shown in the figure, under the first aluminum layer constituting the lower part of the bonding pad 7, for example, a CVD film is formed.
For example, there is a first layer insulating film made of a silicon oxide film and covering a gate electrode of a MISFET. The semiconductor chip Ch i p is covered with a final protective film 14 formed by laminating, for example, a silicon oxide film formed by CVD, a coated glass (SOG) film, a silicon nitride film formed by sputtering, or the like. The final protective film 14 is selectively removed over the bonding pad 7 to form an opening 15.

半導体チップＣｈｉｐのボンディングパッド７と塔載基
板１のボンディングパッド５の間は、例えば金（Ａｕ）
線、銀メッキを施したアルミニウム線等からるボンディ
ングワイヤ６が接続している。ボンディングワイヤ６と
ボンディングパッド７との接続及びボンディングワイヤ
６とボンディングパッド５の接続は、例えば超音波ボン
ディング、熱圧着等で接続する。Between the bonding pad 7 of the semiconductor chip Chip and the bonding pad 5 of the mounting board 1, for example, gold (Au) is used.
A bonding wire 6 made of wire, silver-plated aluminum wire, or the like is connected. The connection between the bonding wire 6 and the bonding pad 7 and the connection between the bonding wire 6 and the bonding pad 5 are performed, for example, by ultrasonic bonding, thermocompression bonding, or the like.

塔載基板１の周囲のボンディングパッド２に、例えば金
線又は銀メッキを施したアルミニウム線等からなるボン
ディングワイヤ１６が接続している。A bonding wire 16 made of, for example, a gold wire or a silver-plated aluminum wire is connected to the bonding pad 2 around the mounting substrate 1.

ボンディングワイヤ１６は、第４図に示したように、４
２７０イ等からなるリード２０に接続している。The bonding wire 16 has four wires as shown in FIG.
The lead 20 is connected to a lead 20 made of a 270 i or the like.

第４図は、塔載基板１、半導体チップＣｈ　ｉ　ｐ等を
封止するパッケージ基板１８Ａ、パッケージキャップ１
８Ｂの断面図である。FIG. 4 shows a mounting board 1, a package board 18A for sealing a semiconductor chip, etc., and a package cap 1.
8B is a cross-sectional view.

第４図において、パッケージ基板１８Ａは等えばセラミ
ック、アルミナ等からなっている。パッケージキャブ１
８Ｂは等えばセラミックからなっている。前記塔載基板
１は、例えばシリコーンゴム等からなる接着剤１７によ
ってパッケージキャブ１８Ａに接着している。接着剤１
７にシリコーンゴムを用いることによって単結晶シリコ
ンからなる塔載基板１に加る応力を少くしている。パッ
ケージ基板１８Ａとパッケージキャブ１８Ｂは１例えば
ガラス等からなる封止剤１９によって接着されている。In FIG. 4, the package substrate 18A is made of ceramic, alumina, etc., for example. package cab 1
8B is made of ceramic. The tower mounting board 1 is adhered to the package cab 18A with an adhesive 17 made of, for example, silicone rubber. Adhesive 1
By using silicone rubber for 7, the stress applied to the mounting substrate 1 made of single crystal silicon is reduced. The package substrate 18A and the package cab 18B are bonded together with a sealant 19 made of, for example, glass.

また、パッケージ基板１８Ａとパッケージキャップ１８
Ｂの間にはリード２０が介在している。リード２０によ
って生じるパッケージ基板１８Ａとパッケージキャブ１
８Ｂの間の隙間は、封止剤１９が封止している。In addition, the package board 18A and the package cap 18
A lead 20 is interposed between B. Package board 18A and package cab 1 caused by leads 20
A sealant 19 seals the gap between the holes 8B.

なお、半導体チップＣｈ　ｉ　ｐと塔載基板１の間の接
着は、半導体チップＣｈｉｐの下の部分の絶縁膜８，９
、最終保護膜１０を選択的に除去して塔載基板１の表面
を露出させ、そこに接着剤１３によって半導体チップＣ
ｈｉｐを接着するようにしてもよい。Note that the adhesion between the semiconductor chip Chip and the mounting substrate 1 is achieved by using the insulating films 8 and 9 in the lower part of the semiconductor chip Chip.
, the final protective film 10 is selectively removed to expose the surface of the mounting substrate 1, and the semiconductor chip C is attached thereto using an adhesive 13.
The hip may also be glued.

また、半導体チップＣｈｉｐと塔載基板１の接着は、例
えばＡｕペースト等で行ってもよい。Further, the semiconductor chip Chip and the mounting board 1 may be bonded together using, for example, Au paste.

以上、説明したように、本願によれば次の効果を得るこ
とができる。As described above, according to the present application, the following effects can be obtained.

半導体チップＣｈｉｐと塔載基板１の間をボンディング
パッド７、ボンディングワイヤ６、ボンディングパッド
５を用いて接続したことにより、それらの間の接続が強
固であるので、半導体チップＣｈｉｐと塔載基板１の間
の接続の信頼性を高めることができる。By connecting the semiconductor chip Chip and the mounting board 1 using the bonding pad 7, the bonding wire 6, and the bonding pad 5, the connection between them is strong. It is possible to increase the reliability of the connection between

また、半導体チップＣｈｉｐの裏面すなわちボンディン
グパッド７が設けられている面と反対側の面が塔載基板
１に接着しているので、すなわち半導体チップＣｈｉｐ
と塔載基板１の間が離隔されていないので、半導体チッ
プＣｈｉｐで生じた熱を塔載基板１を通してパッケージ
基板１８Ａへさらには外気中へ放出することができる。In addition, since the back surface of the semiconductor chip Chip, that is, the surface opposite to the surface on which the bonding pad 7 is provided, is bonded to the mounting substrate 1, that is, the semiconductor chip Chip
Since there is no separation between the semiconductor chip Chip and the mounting board 1, the heat generated in the semiconductor chip Chip can be released through the mounting board 1 to the package board 18A and further into the outside air.

すなわち。Namely.

放熱効果を高めることができる。これは、複数の半導体
チップＣｈｉｐを同一のパッケージ（１８Ａ、１８Ｂ）
で封止する半導体装置では、特に有効である。The heat dissipation effect can be enhanced. This allows multiple semiconductor chips to be packaged in the same package (18A, 18B).
This is particularly effective for semiconductor devices sealed with.

また、塔載基板１が半導体チップＣｈ　ｉ　ｐと同じ単
結晶シリコンからなるので、それらの間の熱膨張差をな
くすことができる。Further, since the mounting substrate 1 is made of the same single crystal silicon as the semiconductor chip Ch i p, the difference in thermal expansion between them can be eliminated.

また、ボンディングワイヤ６で半導体チップＣｈｉｐと
塔載基板１の間を接続することにより。Also, by connecting the semiconductor chip Chip and the mounting board 1 with the bonding wire 6.

半導体チップＣｈｉｐと塔載基板１の間の合せ余裕を大
きくすることができる。The alignment margin between the semiconductor chip Chip and the mounting board 1 can be increased.

また、塔載基板１を半導体ウェハとしていることにより
、塔載基板１の周辺への応力集中がなくなるので、塔載
基板１の破損をなくして信頼性を高めることができる。Further, by using a semiconductor wafer as the mounting substrate 1, stress concentration around the mounting substrate 1 is eliminated, so that damage to the mounting substrate 1 can be eliminated and reliability can be improved.

以上、本発明を実施例にもとづき具体的に説明したが１
本発明は、前記実施例に限定されるものではなく、その
要旨を逸脱しない範囲において種々変更可能であること
は言うまでもない。The present invention has been specifically described above based on examples, but 1.
It goes without saying that the present invention is not limited to the embodiments described above, and can be modified in various ways without departing from the spirit thereof.

例えば、塔載基板１は半導体ウェハでなく、半導体ウェ
ハの周辺を切り落して四角形の塔載基板１としてもよい
。For example, instead of using a semiconductor wafer, the mounting substrate 1 may be made into a rectangular mounting substrate 1 by cutting off the periphery of a semiconductor wafer.

また、ＩＣカード内に内蔵することも可能である。この
場合、塔載基板１はＩＣカード内に収納できる程度の大
きさとし、その上に半導体チップＣｈｉｐを複数塔載す
る。この半導体チップｃｈｉｐと塔載１の間は、ボンデ
ィングワイヤ６、ボンディングパッド７．５を用いて接
続する。また。It is also possible to incorporate it into an IC card. In this case, the mounting board 1 is made large enough to be accommodated in an IC card, and a plurality of semiconductor chips are mounted thereon. The semiconductor chip chip and the mount 1 are connected using bonding wires 6 and bonding pads 7.5. Also.

パッケージ基板１８Ａ、１８１３で封止しないでＩＣカ
ードの内に収納される。It is housed inside the IC card without being sealed with the package substrates 18A and 1813.

〔発明の効果〕〔Effect of the invention〕

本願において開示される発明のうち代表的なものによっ
て得られる効果を簡単に説明すれば、下記のとおりであ
る。A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows.

半導体チップと塔載基板の間をボンディングワイヤで接
続したことにより、それらの間の接続が強固であるので
、半導体チップと塔載基板の間の接続の信頼性を高める
ことができる。By connecting the semiconductor chip and the mounting board with the bonding wire, the connection between them is strong, so that the reliability of the connection between the semiconductor chip and the mounting board can be improved.

また、半導体チップの裏面すなわちボンディングパッド
が設けられている面と反対側の面が塔載基板に接着して
いるので、半導体チップで生じた熱を塔載基板を通して
パッケージへ、さらに外気中へ放出することができる。In addition, since the back side of the semiconductor chip, that is, the side opposite to the side where the bonding pads are provided, is bonded to the mounting board, the heat generated in the semiconductor chip is released through the mounting board to the package and then to the outside air. can do.

すなわち、放熱効果を高めることができる。That is, the heat dissipation effect can be enhanced.

【図面の簡単な説明】 第１図は、複数の半導体チップを塔載した塔載基板の平
面図、 第２図は、塔載基板の一部の平面図、 第３図は、塔載基板の半導体チップを通る線で切った断
面図、 第４図は、塔載基板を封止したパッケージの断面図であ
る。 図中、１・・・塔載基板、２．２ｘ、２ｙ、５．５Ｘ、
５ｙ、７・・・ボンディングパッド、３・・・配線領領
域、４ｘ、４ｙ・・・配線、６，１６・・・ボンディン
グワイヤ、８，９．１０．１４・・・絶縁膜、１１・・
・接続孔、１２．１５・・・開口、１３．１７・・・接
着剤、１８Ａ・・・パッケージ基板、１８Ｂ・・・パッ
ケージキャブ、１９・・・封止剤。 ２０・・・リード、Ｃｈ　ｉ　ｐ・・・半導体チップ。[Brief explanation of the drawings] Fig. 1 is a plan view of a mounting board on which a plurality of semiconductor chips are mounted, Fig. 2 is a plan view of a part of the mounting board, and Fig. 3 is a plan view of a mounting board on which a plurality of semiconductor chips are mounted. FIG. 4 is a sectional view taken along a line passing through the semiconductor chip. FIG. 4 is a sectional view of a package in which a mounting board is sealed. In the figure, 1... Tower-mounted board, 2.2x, 2y, 5.5X,
5y, 7... Bonding pad, 3... Wiring region, 4x, 4y... Wiring, 6, 16... Bonding wire, 8, 9.10.14... Insulating film, 11...
- Connection hole, 12.15... Opening, 13.17... Adhesive, 18A... Package board, 18B... Package cab, 19... Sealing agent. 20...Lead, Chip...Semiconductor chip.

Claims (1)

【特許請求の範囲】 １、塔載基板に複数の半導体チップを塔載し、該塔載基
板上に配線を延在させて前記半導体チップの間を電気的
に接続した半導体装置であって、前記半導体チップと塔
載基板上の配線の間をボンディングワイヤで接続したこ
とを特徴とする半導体装置。 ２、前記半導体チップ及び塔載基板は、同一のパッケー
ジの内に封止されることを特徴とする特許請求の範囲第
１項記載の半導体装置。 ３、前記半導体チップは、ボンディングパッドが設けら
れている方の面と反対側の面が前記塔載基板に接着され
ることを特徴とする特許請求の範囲第１項記載の半導体
装置。[Scope of Claims] 1. A semiconductor device in which a plurality of semiconductor chips are mounted on a mounting board, and wiring is extended on the mounting board to electrically connect the semiconductor chips, A semiconductor device characterized in that the semiconductor chip and the wiring on the mounting board are connected by a bonding wire. 2. The semiconductor device according to claim 1, wherein the semiconductor chip and the mounting substrate are sealed in the same package. 3. The semiconductor device according to claim 1, wherein a surface of the semiconductor chip opposite to the surface on which the bonding pad is provided is bonded to the mounting substrate.
JP62097329A 1987-04-22 1987-04-22 Semiconductor device Pending JPS63263736A (en)

Priority Applications (12)

Application Number Priority Date Filing Date Title
JP62097329A JPS63263736A (en) 1987-04-22 1987-04-22 Semiconductor device
KR88003425A KR960012649B1 (en) 1987-04-22 1988-03-29 Wafer scale or full wafer memory system, package, method thereof and wafer processing method employed therein
DE3856019T DE3856019T2 (en) 1987-04-22 1988-04-08 Integrated semiconductor circuits Device of slice size
EP88303160A EP0288186B1 (en) 1987-04-22 1988-04-08 Packaging of semiconductor integrated circuits
SG1995905451A SG36588G (en) 1987-04-22 1988-04-08 Packaging of semiconductor integrated circuits
DE88303160T DE3882074T2 (en) 1987-04-22 1988-04-08 Packaging of semiconductor integrated circuits.
EP92112517A EP0516185B1 (en) 1987-04-22 1988-04-08 Wafer-scale semiconductor integrated circuit device
US07/627,881 US5191224A (en) 1987-04-22 1990-12-13 Wafer scale of full wafer memory system, packaging method thereof, and wafer processing method employed therein
US07/960,848 US5309011A (en) 1987-04-22 1992-10-14 Wafer scale or full wafer memory system, packaging method thereof, and wafer processing method employed therein
KR93004115A KR970001885B1 (en) 1987-04-22 1993-03-18 Wafer scale semiconductor device
HK28096A HK28096A (en) 1987-04-22 1996-02-15 Packaging of semiconductor integrated circuits
HK98101603A HK1003348A1 (en) 1987-04-22 1998-03-02 Wafer-scale semiconductor integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62097329A JPS63263736A (en) 1987-04-22 1987-04-22 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS63263736A true JPS63263736A (en) 1988-10-31

Family

ID=14189447

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62097329A Pending JPS63263736A (en) 1987-04-22 1987-04-22 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS63263736A (en)

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