JPS63124425A - Semioonductor device - Google Patents
Semioonductor deviceInfo
- Publication number
- JPS63124425A JPS63124425A JP26854686A JP26854686A JPS63124425A JP S63124425 A JPS63124425 A JP S63124425A JP 26854686 A JP26854686 A JP 26854686A JP 26854686 A JP26854686 A JP 26854686A JP S63124425 A JPS63124425 A JP S63124425A
- Authority
- JP
- Japan
- Prior art keywords
- resin
- base substrate
- substrate
- powder
- film multilayer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000000758 substrate Substances 0.000 claims abstract description 39
- 229920005989 resin Polymers 0.000 claims abstract description 33
- 239000011347 resin Substances 0.000 claims abstract description 33
- 229910000679 solder Inorganic materials 0.000 claims abstract description 7
- 239000000843 powder Substances 0.000 claims description 20
- 239000004065 semiconductor Substances 0.000 claims description 17
- 239000008187 granular material Substances 0.000 claims description 8
- 239000010409 thin film Substances 0.000 abstract description 19
- 239000002245 particle Substances 0.000 abstract description 5
- 239000000126 substance Substances 0.000 abstract 3
- 238000004299 exfoliation Methods 0.000 abstract 2
- 239000000853 adhesive Substances 0.000 description 5
- 230000001070 adhesive effect Effects 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 239000000919 ceramic Substances 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 239000004642 Polyimide Substances 0.000 description 1
- 238000010420 art technique Methods 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明はＬＳＩ実装体に係り、とくにＬＳＩと配線基板
との接続の信頼性を向」ユするのに好適な半導体装置に
関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an LSI package, and particularly to a semiconductor device suitable for improving the reliability of the connection between an LSI and a wiring board.
従来よりＬＳＩを配線基板にはんだ溶融によって接続す
る技術は良く知られている。2. Description of the Related Art Techniques for connecting LSIs to wiring boards by melting solder are well known.
この技術における制限は、ＬＳＩと配線基板との熱膨張
の相異によって接続用はんだに大きな歪が繰返し発生し
て遂には断線に至る点である。A limitation of this technique is that due to the difference in thermal expansion between the LSI and the wiring board, large strains are repeatedly generated in the connecting solder, eventually leading to disconnection.
そこで、従来、前記の断線が発生しないようにＬＳＩサ
イズを小さくするなどの設計的工夫がなされている。Therefore, conventional design efforts have been made to reduce the size of the LSI so as to prevent the above-mentioned disconnection from occurring.
前記歪を小さくするための一例として特開昭６Ｏ−６３
９５Ｌ号に記載され、これを第４図に示すように、ＬＳ
ｌｌが配線基板２にはんだ４にて接続され、その周辺を
粉粒体の入った樹脂３により配線基板２に固着させるも
のが提案されている。As an example of reducing the distortion, Japanese Patent Application Laid-Open No. 60-63
95L, and as shown in Figure 4, LS
It has been proposed that ll is connected to the wiring board 2 with solder 4, and its periphery is fixed to the wiring board 2 with resin 3 containing powder.
この方式によれば、ＬＳＩＩの熱膨張をおさえ、はんだ
４の歪を少なくして熱疲労寿命を長くすることができる
利点がある。This method has the advantage of suppressing thermal expansion of the LSII, reducing distortion of the solder 4, and extending thermal fatigue life.
近年、この種の半導体装置においては、高密度化の要求
から配線基板として薄膜多層基板が使用されるようにな
ってきている。この薄膜多層基板はたとえば第５図に示
すようにセラミックなどのベース基板２上にポリイミド
などからなる樹脂を絶縁材料として多層化５をはかった
ものである。In recent years, in this type of semiconductor device, thin film multilayer substrates have been used as wiring substrates due to the demand for higher density. This thin film multilayer substrate is, for example, as shown in FIG. 5, in which a multilayer structure 5 is formed on a base substrate 2 made of ceramic or the like using a resin made of polyimide or the like as an insulating material.
しかるに、第５図に示すように、粉粒体の入った樹脂３
でＬＳＩＩの周囲を包囲した場合、粉粒体の入った樹脂
３とベース基板２との熱膨張の差のため、温度変化によ
って接着界面に応力が発生する。このとき、両樹脂３，
５間の接着強度に対して多層樹脂５とベース基板２との
接着強度は低く、とくに第６図に示すようにベース基板
２の端面では接着強度が弱く、反対に応力が最大になる
ため、薄膜多層部分５がベース基板２からはく離する問
題がある。However, as shown in FIG.
When surrounding the LSII, stress is generated at the adhesive interface due to temperature changes due to the difference in thermal expansion between the resin 3 containing the powder and the base substrate 2. At this time, both resins 3,
The adhesive strength between the multilayer resin 5 and the base substrate 2 is low compared to the adhesive strength between the multilayer resin 5 and the base substrate 2, and as shown in FIG. There is a problem that the thin film multilayer portion 5 peels off from the base substrate 2.
本発明の目的は、前記従来技術の問題点を解決し、優れ
た信頼性を有する半導体装置を提供することにある。An object of the present invention is to solve the problems of the prior art and provide a semiconductor device with excellent reliability.
前記の目的は、ベース基板上に粉粒体の入った樹脂と直
接接着するための直接接着部を設置することにより達成
される。The above object is achieved by providing a direct bonding section on the base substrate for directly bonding the resin containing the powder or granules.
前記薄膜多層部のはく離は、粉粒体の入った樹脂で接着
された部分の最外縁部に最も多く発生しやすいことがわ
かった。It has been found that peeling of the thin film multilayer part is most likely to occur at the outermost edge of the part bonded with the resin containing the powder.
これは、樹脂とベース基板との熱膨張の差が最も大きな
理由であって、この熱膨張の差によって大きな応力が薄
膜多層部に加わると同時にその大きな応力は最外縁部に
加わるので、ベース基板からはく離する方向に力が働く
ためである。The reason for this is that the difference in thermal expansion between the resin and the base substrate is the biggest. Due to this difference in thermal expansion, a large stress is applied to the thin film multilayer part, and at the same time, the large stress is applied to the outermost edge of the base substrate. This is because a force acts in the direction of peeling off.
そこで、本発明は、前記最外縁部の薄膜多層部を除去し
てセラミックなどからなるベース基板上に直接粉粒体の
入った樹脂を接着したので、応力に対する接着強度は、
薄膜多層部よりも大きくなって最外縁部の粉粒体の入っ
た樹脂がベース基板からはがれにくくなる。Therefore, in the present invention, the thin film multilayer portion at the outermost edge is removed and the resin containing the powder is bonded directly onto the base substrate made of ceramic or the like, so that the adhesive strength against stress is
It is larger than the thin film multilayer part, and the resin containing the powder at the outermost edge becomes difficult to peel off from the base substrate.
また粉粒体の入った樹脂の内側に位置する薄膜多層部は
最外縁部の粉粒体の入った樹脂がベース基板上からはが
れない限りこの樹脂に包囲され、ベース基板からはく離
する力が働かないので、ベ−大基板からはく離すること
がない。In addition, the thin film multilayer part located inside the resin containing powder particles will be surrounded by this resin unless the resin containing powder particles at the outermost edge peels off from the base substrate, and there will be no force acting to separate it from the base substrate. There is no possibility of peeling off from the large substrate.
以下、本発明の一実施例を示す第１図について説明する
。第１図は本発明の一実施例である半導体を示す図であ
る。Hereinafter, FIG. 1 showing an embodiment of the present invention will be described. FIG. 1 is a diagram showing a semiconductor which is an embodiment of the present invention.
第１図に示すようにベース基板２上のはんだ４にてＬＳ
ＩＩと接続する薄膜多層部５の一部（最外縁部）が除去
され、その部分２ａのベース基板２上を露出させたのち
、ＬＳＩＩを包囲するための粉粒体の入った樹脂３が前
記ベース基板２上の露出部分に直接接着している。As shown in Figure 1, solder 4 on base board 2
After a part (outermost edge) of the thin film multilayer part 5 connected to the LSII is removed and the top of the base substrate 2 in that part 2a is exposed, the resin 3 containing powder for surrounding the LSII is applied to the base substrate 2. It is directly bonded to the exposed portion on the base substrate 2.
本発明による半導体は前記の如く構成されているから、
粉粒体の入った樹脂３とベース基板２との熱膨張の差に
よって発生する応力に対する接着強度が薄膜多層部５の
それよりも大きくなるので、粉粒体の入った樹脂３がベ
ース基板２からはがれるのを防止することができる。Since the semiconductor according to the present invention is configured as described above,
Since the adhesive strength against the stress generated by the difference in thermal expansion between the resin 3 containing the powder and the base substrate 2 is greater than that of the thin film multilayer part 5, the resin 3 containing the powder and the base substrate 2 It can prevent it from peeling off.
また、薄膜多層部５は粉粒体の入った樹脂３に包囲され
ているため、粉粒体の入った樹脂３がベース基板２から
はがれない限りベース基板２から−５−−ｉｎ乏
はく離する力が働かないのでベース基板２がらはく離す
るのを防止することができる。Moreover, since the thin film multilayer part 5 is surrounded by the resin 3 containing powder and granules, unless the resin 3 containing powder and granules peels off from the base substrate 2, it will peel off from the base substrate 2 by -5 inches. Since no force is applied, it is possible to prevent the base substrate 2 from peeling off.
つぎに第２図は本発明の他の一実施例であるベース基板
上に複数のＬＳＩを搭載した半導体を示し、第３図は第
２図に示す半導体の他の一実施例を示す。Next, FIG. 2 shows another embodiment of the present invention, which is a semiconductor in which a plurality of LSIs are mounted on a base substrate, and FIG. 3 shows another embodiment of the semiconductor shown in FIG. 2.
第２図においては、ＬＳＩＩ毎に薄膜多層部５′が分割
され、かつ各薄膜多層部５′の最外縁部を除去してその
部分２ａのベース基板２上を露出し、この部分２ａに薄
膜多層部５′を包囲する粉粒体の入った樹脂３が直接接
着している。In FIG. 2, the thin film multilayer part 5' is divided for each LSII, and the outermost edge of each thin film multilayer part 5' is removed to expose the base substrate 2 in that part 2a. The resin 3 containing powder and granules surrounding the multilayer part 5' is directly bonded to the multilayer part 5'.
また第３図においては、複数個のＬＳＩＩと接続する１
個の薄膜多層部５′の最外縁部を除去してその部分２ａ
のベース基板２上を露出し、この部分２ａに薄膜多層部
５′を包囲する粉粒体の入った樹脂３が直接接着してい
る。In addition, in Fig. 3, one
The outermost edge of each thin film multilayer part 5' is removed and the part 2a is removed.
The top of the base substrate 2 is exposed, and a resin 3 containing powder and granules surrounding the thin film multilayer portion 5' is directly adhered to this portion 2a.
したがって、第２図および第３図に示す半導体において
も前記第１図に示す半導体と同様の効果を得ることがで
きる。Therefore, the same effects as those of the semiconductor shown in FIG. 1 can be obtained in the semiconductors shown in FIGS. 2 and 3 as well.
本発明によれば粉粒体の入った樹脂および薄膜多層部が
ベース基板上からはく離するのを防止することができる
ので、優れた信頼性を得ることができる。According to the present invention, it is possible to prevent the resin containing the powder and the thin film multilayer portion from peeling off from the base substrate, so that excellent reliability can be obtained.
第１図は本発明の一実施例である半導体装置を示す図、
第２図は本発明の他の一実施例である半導体装置を示す
図、第３図は本発明のさらに他の一実施例である半導体
装置を示す図、第４図は従来の半導体装置の一例を示す
図、第５図は従来の半導体装置の他の一例を示す図、第
６図は従来の半導体装置のさらに他の一例を示す図であ
る。
１・・・ＬＳＩ、２・・・ベース基板、３・・・粉粒体
の入った樹脂、５・・薄膜多層部。FIG. 1 is a diagram showing a semiconductor device which is an embodiment of the present invention;
FIG. 2 shows a semiconductor device according to another embodiment of the present invention, FIG. 3 shows a semiconductor device according to still another embodiment of the invention, and FIG. 4 shows a conventional semiconductor device. FIG. 5 is a diagram showing another example of the conventional semiconductor device, and FIG. 6 is a diagram showing still another example of the conventional semiconductor device. DESCRIPTION OF SYMBOLS 1...LSI, 2...Base substrate, 3...Resin containing powder and granules, 5...Thin film multilayer part.
Claims (1)
線基板と、この多層配線基板上にはんだにて溶融接続す
るＬＳＩと、このＬＳＩを包囲する粉粒体の入った樹脂
とを有し、かつ、前記粉粒体の入った樹脂を前記ベース
基板上に直接接着するように構成したことを特徴とする
半導体装置。 ２、前記ベース基板上に前記粉粒体の入った樹脂が直接
接着している領域は、前記多層配線基板の最外周部であ
ることを特徴とする特許請求の範囲第１項記載の半導体
装置。[Claims] 1. A multilayer wiring board formed of a resin as an insulating layer on a base substrate, an LSI to be melted and connected to the multilayer wiring board by solder, and a powder containing a granular material surrounding the LSI. 1. A semiconductor device comprising: a resin, and configured such that the resin containing the powder or granules is directly adhered onto the base substrate. 2. The semiconductor device according to claim 1, wherein the area where the powder-containing resin is directly adhered to the base substrate is the outermost periphery of the multilayer wiring board. .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61268546A JPH0669075B2 (en) | 1986-11-13 | 1986-11-13 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61268546A JPH0669075B2 (en) | 1986-11-13 | 1986-11-13 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS63124425A true JPS63124425A (en) | 1988-05-27 |
| JPH0669075B2 JPH0669075B2 (en) | 1994-08-31 |
Family
ID=17460030
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61268546A Expired - Lifetime JPH0669075B2 (en) | 1986-11-13 | 1986-11-13 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0669075B2 (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5469333A (en) * | 1993-05-05 | 1995-11-21 | International Business Machines Corporation | Electronic package assembly with protective encapsulant material on opposing sides not having conductive leads |
| US6946741B2 (en) | 2002-08-30 | 2005-09-20 | Kabushiki Kaisha Toshiba | Semiconductor device and manufacturing method thereof |
| JP2006310880A (en) * | 1998-07-01 | 2006-11-09 | Seiko Epson Corp | Semiconductor apparatus and its manufacturing method, circuit substrate as well as electronic apparatus |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60182752A (en) * | 1984-02-29 | 1985-09-18 | Hitachi Ltd | Resin-coated electronic device |
-
1986
- 1986-11-13 JP JP61268546A patent/JPH0669075B2/en not_active Expired - Lifetime
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60182752A (en) * | 1984-02-29 | 1985-09-18 | Hitachi Ltd | Resin-coated electronic device |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5469333A (en) * | 1993-05-05 | 1995-11-21 | International Business Machines Corporation | Electronic package assembly with protective encapsulant material on opposing sides not having conductive leads |
| JP2006310880A (en) * | 1998-07-01 | 2006-11-09 | Seiko Epson Corp | Semiconductor apparatus and its manufacturing method, circuit substrate as well as electronic apparatus |
| US6946741B2 (en) | 2002-08-30 | 2005-09-20 | Kabushiki Kaisha Toshiba | Semiconductor device and manufacturing method thereof |
| US7368323B2 (en) | 2002-08-30 | 2008-05-06 | Kabushiki Kaisha Toshiba | Semiconductor device and manufacturing method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0669075B2 (en) | 1994-08-31 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP3578770B2 (en) | Semiconductor device | |
| JPH10178028A (en) | Reprocessable assembly for directly fitting chip | |
| CA2272434A1 (en) | Chip scale ball grid array for integrated circuit package | |
| JPS6324647A (en) | Semiconductor package | |
| JPS5940560A (en) | Multilayer circuit device | |
| JPS5992556A (en) | Semiconductor device | |
| JP2003218148A (en) | Semiconductor integrated circuit and its manufacturing method, circuit board, and electronic instrument | |
| JPS63124425A (en) | Semioonductor device | |
| JP2001068512A (en) | Tab tape with stiffener and bga package | |
| JP2007165836A (en) | Semiconductor device | |
| JPH065769A (en) | Laminated film base material and lead frame for mounting electronic circuit element employing the film base material | |
| JP3672885B2 (en) | Semiconductor device | |
| JPH08222828A (en) | Printed wiring board and manufacture thereof | |
| JPS58125859A (en) | Substrate for mounting of semiconductor element | |
| JPH0786459A (en) | Semiconductor device | |
| JP2003007904A (en) | Semiconductor device | |
| JPH02222598A (en) | Semiconductor device module | |
| JP3933910B2 (en) | Manufacturing method of semiconductor device and manufacturing method of laminated structure | |
| JP3257931B2 (en) | Semiconductor package, method of manufacturing the same, and semiconductor device | |
| JPS5848932A (en) | Preparation of semiconductor device | |
| JPH1154665A (en) | Composite package | |
| JPH04342162A (en) | Semiconductor integrated circuit device and its package structure | |
| JPS5824014B2 (en) | Manufacturing method of mounting body | |
| JPS6143435A (en) | Semiconductor device and manufacture thereof | |
| JPH02234449A (en) | Semiconductor device |