JPH1154665A - Composite package - Google Patents

Composite package

Info

Publication number
JPH1154665A
JPH1154665A JP20625097A JP20625097A JPH1154665A JP H1154665 A JPH1154665 A JP H1154665A JP 20625097 A JP20625097 A JP 20625097A JP 20625097 A JP20625097 A JP 20625097A JP H1154665 A JPH1154665 A JP H1154665A
Authority
JP
Japan
Prior art keywords
package
ceramic substrate
mounting
composite package
thickness
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP20625097A
Other languages
Japanese (ja)
Inventor
Keiichi Yano
圭一 矢野
Yasushi Iyogi
靖 五代儀
Hironori Asai
博紀 浅井
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP20625097A priority Critical patent/JPH1154665A/en
Publication of JPH1154665A publication Critical patent/JPH1154665A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors

Landscapes

  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

PROBLEM TO BE SOLVED: To facilitate bonding work of solder balls by mounting a semiconductor element on a ceramic substrate having a recess, bonding a resin board to the surface of the ceramic substrate and providing an opening corresponding to the recess. SOLUTION: The composite package comprises a resin board 2 and a ceramic substrate 1 bonded together wherein a recess for mounting a semiconductor chip 5 is made in the ceramic substrate 1 and an opening corresponding to the recess is made in the resin board 2. More specifically, the ceramic substrate 1 is provided with a cavity and boded with the resin board 2 having an opening at a part corresponding to the cavity. Subsequently a semiconductor chip 5 is mounted using a conductive adhesive 7 and wire bonded through a bonding wire before being sealed using a potting agent 4.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、多端子・狭ピッチ
の半導体素子用パッケージに係り、特に、セラミックス
基板と樹脂基板またはフィルムとを接着・接合した半導
体素子用複合パッケージに関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multi-terminal, narrow-pitch semiconductor device package, and more particularly to a semiconductor device composite package in which a ceramic substrate and a resin substrate or a film are bonded and bonded.

【0002】[0002]

【従来の技術】LSI等の半導体チップが実装されるセ
ラミックス、樹脂、金属などからなる各種のパッケージ
は、LSIの高集積化、高速化、大消費電力化、大型チ
ップ化により、高密度化、高速対応化、高放熱化が要求
される傾向にある。また、これらの半導体チップの用途
も、ワークステーション、パーソナルコンピューター、
コンピューター等の産業用から、携帯用機器、プリンタ
ー、コピー、カメラ、テレビ、ビデオ等の電子機器まで
多くの範囲に広がり、半導体素子の性能自体も向上して
いる。高性能、高集積密度のLSIチップを搭載するパ
ッケージには、LSIチップと多端子・狭ピッチで接続
ができること、配線密度が高いこと、放熱性がよいこ
と、高速の信号を扱うことができること、パッケージの
入出力端子を多端子・狭ピッチ化する事が可能であるこ
となどが求められている。さらに、これらの条件を満足
する高性能なパッケージを、簡単な工程でかつ高信頼性
の下で安価に作製する技術が必要になってきている。
2. Description of the Related Art Various types of packages, such as ceramics, resins, and metals, on which semiconductor chips such as LSIs are mounted, have been increased in density due to high integration, high speed, large power consumption, and large chips of LSIs. There is a tendency for higher speed and higher heat dissipation to be required. These semiconductor chips are also used for workstations, personal computers,
2. Description of the Related Art From industrial use such as computers to electronic devices such as portable devices, printers, copiers, cameras, televisions, and videos, the performance of semiconductor devices themselves has been improved. Packages that mount high-performance, high-integration-density LSI chips must be able to connect to the LSI chip with multiple terminals and a narrow pitch, have high wiring density, have good heat dissipation, and can handle high-speed signals. It is required that the number of input / output terminals of a package can be increased and the pitch can be reduced. Further, there is a need for a technique for producing a high-performance package satisfying these conditions at a low cost with a simple process and high reliability.

【0003】半導体素子を高機能化するためには多ビッ
ト化、大容量化、高速化の三つが柱となる。この中で特
に高速化の要求はパッケージに大きな影響を与えてき
た。半導体素子への入出力の端子数(ピン数)を増加さ
せ、データを並行処理することで高速化が図るからであ
る。このため、パッケージにおいても多端子化(多ピン
化)は一つの命題となってきている。また、携帯機器の
小型化や、高密度実装のためにパッケージの小型化も要
求されている。特にこれから大きく伸びるマルチメディ
アの分野、アミューズメントや通信機器などにおいてこ
の要求は大きい。多ピン化と小型化、この二つのニーズ
を満たすため様々なパッケージが開発されている。半導
体素子との接続技術を有効に機能させる上で、パッケー
ジ側も狭ピッチ・多端子のインナーリード部分が必要で
あると共に、プリント基板等の搭載ボードとパッケージ
との接続も、多端子・狭ピッチにする事が必要になって
いる。また、前述したように、LSIの高速化によりパ
ッケージも高速信号を扱う必要があるため、電気特性の
考慮も必要となる。
[0003] In order to enhance the function of a semiconductor element, three pillars of increasing the number of bits, increasing the capacity, and increasing the speed are the pillars. Among them, the demand for high speed has had a great influence on the package. This is because the number of input / output terminals (pins) to / from the semiconductor element is increased and data is processed in parallel to increase the speed. For this reason, multi-terminals (multi-pins) has become one proposition in packages. In addition, miniaturization of portable devices and miniaturization of packages for high-density mounting are also required. This demand is particularly great in the field of multimedia, amusement and communication equipment, which will greatly increase in the future. Various packages have been developed to meet these two needs of multi-pin and miniaturization. In order for the connection technology with semiconductor elements to function effectively, the package side must also have a narrow-pitch, multi-terminal inner lead, and the connection between the mounting board, such as a printed circuit board, and the package must also have a multi-terminal, narrow pitch It is necessary to do. Further, as described above, the package needs to handle high-speed signals due to the increase in the speed of the LSI, so that it is necessary to consider the electrical characteristics.

【0004】以上のようなパッケージの多端子・狭ピッ
チ化への要請を満足させるために、LSI用のパッケー
ジ構造は従来のピン挿入型やQFP(クウォド・フラッ
ド・パッケージ;Quad Flad Package )等の表面実装型
から、BGA(ボール・グリッド・アレイ;Ball Grid
Array )パッケージに移行の傾向にある。
In order to satisfy the above-mentioned demands for a package having a plurality of terminals and a narrow pitch, a package structure for an LSI is made of a conventional pin insertion type or a QFP (Quad Flood Package). From surface mount type to BGA (Ball Grid Array)
Array) tend to migrate to packages.

【0005】従来の表面実装型のパッケージにおいて、
多端子・狭ピッチ化を行うためには、端子の精度、リー
ドに起因するインダクタンス、リードそのものの強度あ
るいは実装時の精度等の点から限界が見えてきているか
らである。また表面実装型では多端子化にともないパッ
ケージが大型化せざるを得ない欠点を有している。
In a conventional surface mount type package,
This is because limits to the multi-terminal and narrow pitch are becoming apparent in terms of terminal accuracy, lead-induced inductance, lead strength, and mounting accuracy. Also, the surface mount type has a disadvantage that the package must be increased in size as the number of terminals increases.

【0006】BGAは、従来のパッケージに比べ、イン
ダクタンスを低減させ、パッケージ本体の多層配線構造
を高速対応させることが可能であり、大型コンピュータ
ーや、パーソナルコンピューター、携帯機器等の民生品
へと使用用途が広がっている。BGAは、パッケージの
入出力端子として半田からなる突起接続体(半田ボー
ル)を用いたパッケージ構造体を有し、上述したような
ピンやリードに起因するインダクタンスによる高速信号
の反射遅延等を改善するが可能である。また、半田ボー
ルによる接続距離の短縮化に加えて、半田ボール形成に
よる狭ピッチ・多端子化が容易となり、BGAは今後の
LSIパッケージとして有望である。たとえば0.9m
m中の半田ボールを用いれば、1.27mmピッチのL
SIパッケージが実現できる。更に、この半田ボール形
成による狭ピッチ・多端子化は、パッケージサイズその
ものを縮小化し、プリント基板等への実装密度の向上、
配線の寄生容量、インダクタンス、抵抗などの低減によ
る電気特性の向上、パッケージの小型化による高周波特
性の改善等が期待できる。一方、パッケージの放熱面か
ら見ると、LSIの高集積密度化と高速化にともない、
消費電力が向上し、発熱量は年々増加する傾向にある。
しかもコンピュータにおいては、本体の小型化が進む反
面、ボードの枚数は増加する傾向にあり、ボード間の隙
間も次第に狭くなってきている。
The BGA can reduce the inductance compared to the conventional package, and can correspond to the multilayer wiring structure of the package body at high speed, and is used for consumer products such as large computers, personal computers, and portable devices. Is spreading. The BGA has a package structure using a protrusion connection body (solder ball) made of solder as an input / output terminal of the package, and improves reflection delay of a high-speed signal due to inductance caused by pins and leads as described above. Is possible. Further, in addition to shortening the connection distance by the solder ball, it is easy to form a narrow pitch and multiple terminals by forming the solder ball, and the BGA is promising as an LSI package in the future. For example 0.9m
If a solder ball in m is used, a pitch of 1.27 mm
An SI package can be realized. In addition, the narrow pitch and the large number of terminals by the formation of solder balls reduce the package size itself, improve the mounting density on printed circuit boards, etc.
It can be expected to improve electrical characteristics by reducing the parasitic capacitance, inductance, resistance, etc. of the wiring, and to improve high-frequency characteristics by reducing the size of the package. On the other hand, from the viewpoint of the heat dissipation of the package, with the increase in the integration density and the speed of the LSI,
Power consumption is increasing and the amount of heat generated tends to increase year by year.
Moreover, in the computer, while the size of the main body has been reduced, the number of boards has been increasing, and the gap between the boards has been gradually narrowed.

【0007】このようなことから、パッケージ自体も薄
型で、放熱性に優れた構造や材料が必要となってきてい
る。高放熱性パッケージには、セラミックスパッケージ
が主として使用されている。セラミックスには、窒化ア
ルミニウム、窒化珪素、アルミナ、硝子セラミックス等
があり、発熱量や高周波特性等の仕様によりこれらをう
まく使い分けている。しかしながら、セラミックス製パ
ッケージでは、プリント基板に搭載した際に、パッケー
ジとプリント基板との熱膨張係数の差が大きいことか
ら、接続部である半田ボール部分の接続信頼性(実装信
頼性)が低いという問題を有している。この熱膨張差
は、BGAパッケージをプリント基板に搭載する際のリ
フロー半田付け工程で熱履歴をうけることにより起こる
ものと、通常の使用中における環境温度変化によるもの
とがあるが、いずれもセラミックスとプリント基板との
熱膨張差が大きいために、機械的強度が低い半田ボール
部分に熱応力が集中し、半田ボールにクラックが生じた
り、さらには半田ボールが破断する等して、接続部の実
装信頼性を低下させるという問題を有していた。
[0007] For these reasons, the package itself is required to be thin and to have a structure and material excellent in heat dissipation. Ceramic packages are mainly used for high heat dissipation packages. Ceramics include aluminum nitride, silicon nitride, alumina, glass ceramics and the like, and these are properly used depending on the specifications such as the calorific value and high frequency characteristics. However, in a ceramic package, when mounted on a printed circuit board, the connection reliability (mounting reliability) of the solder ball portion, which is a connection portion, is low because the difference in thermal expansion coefficient between the package and the printed circuit board is large. Have a problem. This difference in thermal expansion can be caused by thermal history in the reflow soldering process when mounting the BGA package on a printed circuit board, or by a change in environmental temperature during normal use. Due to the large difference in thermal expansion from the printed circuit board, thermal stress concentrates on the solder balls with low mechanical strength, causing cracks in the solder balls and breaking the solder balls. There was a problem that reliability was reduced.

【0008】この問題点を鑑み、近年セラミックス基板
にプリント基板と熱膨張係数の近い樹脂基板を接着剤等
で貼り合わせた複合パッケージとすることである程度の
信頼性の向上が図られている。すなわち、熱伝導率の高
いセラミックス基板と配線層を有する樹脂基板とを貼り
合わせて電気的機械的に接合した複合パッケージを形成
することで、樹脂基板の熱膨張係数とプリント基板の熱
膨脹係数がほぼ等しいという長所、さらには樹脂基板の
リソグラフィによる微細配線の容易性、あるいは樹脂基
板の低価格性等の長所と、セラミックス基板の持つ高熱
伝導特性という長所をともに生かした構造となってい
る。
In view of this problem, in recent years, a composite package in which a resin substrate having a thermal expansion coefficient close to that of a printed substrate is bonded to a ceramic substrate with an adhesive or the like has been improved to some extent. That is, by forming a composite package in which a ceramic substrate having high thermal conductivity and a resin substrate having a wiring layer are electrically and mechanically bonded to each other, the thermal expansion coefficient of the resin substrate and the thermal expansion coefficient of the printed circuit board are substantially reduced. The structure makes use of the advantage of equality, the ease of fine wiring by lithography of the resin substrate, the advantage of low cost of the resin substrate, and the advantage of the high thermal conductivity characteristic of the ceramic substrate.

【0009】[0009]

【発明が解決しようとする課題】図2は従来の半導体素
子用複合パッケージに半導体チップ5をマウントし、ボ
ンディングワイヤー6でボンディングし、その上からポ
ッティング剤4で封じた状態を示す。図2に示すような
樹脂基板2とセラミックス基板11とからなるキャビテ
ィダウンタイプの半導体素子用複合パッケージにおい
て、平板のセラミックス基板11では、チップの封止に
用いるポッティング剤4が、樹脂基板の表面から凸型に
出っ張るため、端子用の半田ボール3を所定の位置に配
置して接合する作業が不可能となる。図2に樹脂基板2
の厚みは0.15mmである。この場合ポッティング剤
4の凸部の高さは半導体チップの厚みにもよるが0.6
〜0.8mm程度となり、半田ボール3を配置・接合す
るための半田ペーストのスクリーン印刷が不可能とな
る。
FIG. 2 shows a state in which a semiconductor chip 5 is mounted on a conventional composite package for a semiconductor device, bonded with a bonding wire 6, and sealed with a potting agent 4 from above. In the composite package for a cavity-down type semiconductor device including the resin substrate 2 and the ceramic substrate 11 as shown in FIG. 2, in the flat ceramic substrate 11, the potting agent 4 used for chip sealing is removed from the surface of the resin substrate. Because of the protrusion, it is impossible to arrange the solder balls 3 for the terminals at predetermined positions and join them. FIG. 2 shows the resin substrate 2
Has a thickness of 0.15 mm. In this case, the height of the projection of the potting agent 4 is 0.6, although it depends on the thickness of the semiconductor chip.
It is about 0.8 mm, so that the screen printing of the solder paste for arranging and joining the solder balls 3 becomes impossible.

【0010】また、図2に示した構造の不都合を防ぐた
めに樹脂基板2の厚みを図3に示すように厚くすると、
熱抵抗が増加し、半導体素子の高消費電力化対応の要請
に反する。図3は樹脂基板12の厚みを0.45mmと
した複合パッケージである。図2と同様に半導体チップ
5を搭載し、ホンディングワイヤー6をワイヤーボンデ
ィングし、ポッティング剤4で封止し、半田ボール3を
所定の位置に接合する作業を行っている。図3に示す複
合パッケージの熱抵抗を測定したところ、20℃/Wと
大きく、また許容できる消費電力が約2.5Wまでと低
かった。
When the thickness of the resin substrate 2 is increased as shown in FIG. 3 to prevent the inconvenience of the structure shown in FIG.
Thermal resistance increases, which is contrary to the demand for high power consumption of semiconductor devices. FIG. 3 shows a composite package in which the thickness of the resin substrate 12 is 0.45 mm. As in FIG. 2, the semiconductor chip 5 is mounted, the bonding wire 6 is wire-bonded, the potting agent 4 is sealed, and the solder ball 3 is bonded to a predetermined position. When the thermal resistance of the composite package shown in FIG. 3 was measured, it was as large as 20 ° C./W, and the allowable power consumption was as low as about 2.5 W.

【0011】上記問題点を鑑み、本発明は半田ボールの
接合作業が容易でしかも熱放散の良好な半導体素子用複
合パッケージを提供することを目的とする。
SUMMARY OF THE INVENTION In view of the above problems, an object of the present invention is to provide a composite package for a semiconductor device in which a solder ball is easily joined and heat dissipation is good.

【0012】本発明の他の目的は半田ボールの接合作業
が容易で実装信頼性の高い半導体素子用複合パッケージ
を提供することである。
It is another object of the present invention to provide a composite package for a semiconductor device in which a solder ball is easily joined and mounting reliability is high.

【0013】[0013]

【課題を解決するための手段】上記目的を達成するた
め、この発明による複合パッケージは、半導体素子を搭
載するための凹部を有するセラミックス基板と、この凹
部に対応する開口部を有し、セラミックス基板表面に接
合された樹脂基板とからなることを特徴とする。
In order to achieve the above object, a composite package according to the present invention has a ceramic substrate having a concave portion for mounting a semiconductor element, and an opening corresponding to the concave portion. And a resin substrate bonded to the surface.

【0014】本発明の特徴によれば、セラミックス基板
の半導体チップ搭載部に、いわゆるキャビティと呼ばれ
る凹部を設けているので、ポッティング剤の出っ張りを
所定の値よりも低く抑えることができ、容易に半田ボー
ルの接合が可能となる。ポッティング剤の樹脂基板
(0.08〜0.3mm程度のフィルム状基板)の表面
からの出っ張りは0.2mm以下が好ましい。また、樹
脂基板の厚みを薄く抑えることが可能であることから、
熱抵抗が小さく、熱放散が良好となる。本発明者らの実
験結果によればキャビティダウンタイプの半導体素子用
複合パッケージの場合、熱抵抗はセラミックス基板の厚
みを薄くして行くと厚さ0.6mm近傍で最小値とな
り、さらに薄くすると再び増大することが発見された。
したがって、厚さ0.6mm近傍の厚みのセラミックス
基板が好ましいが、半導体チップの厚みを0.4mm,
半導体チップをセラミックス基板に固定するための導電
性接着剤の厚みを0.05mmとし、ポッティング剤の
出っ張りを0.2mmとするためにはセラミックス基板
中に形成する凹部の深さは0.35m〜0.45mm程
度が好ましい。この場合凹部の底部に残存するセラミッ
クス基板の厚みは0.25〜0.15mmとなり、機械
的強度が心配されるところである。しかし、本発明者ら
の実験によれば、機械的強度は周辺部の厚い部分で担保
され、しかも凹部の薄い部分の効果でパッケージの若干
のそりが生じて、実装時のパッケージとプリント基板間
の熱的歪みが緩和されることが見い出された。したがっ
て、セラミックス基板中の凹部は実装信頼性の向上に顕
著な効果を奏することが認められた。したがって実装信
頼性が高く高消費電力の半導体チップの搭載が可能な複
合パッケージが提供できる。
According to the feature of the present invention, since a so-called cavity is provided in the semiconductor chip mounting portion of the ceramic substrate, the protrusion of the potting agent can be suppressed to a value lower than a predetermined value, and soldering can be easily performed. Ball joining becomes possible. The protrusion of the potting agent from the surface of the resin substrate (a film-like substrate having a thickness of about 0.08 to 0.3 mm) is preferably 0.2 mm or less. Also, since the thickness of the resin substrate can be reduced,
Low heat resistance and good heat dissipation. According to the experimental results of the present inventors, in the case of a cavity-down type composite package for a semiconductor device, the thermal resistance becomes a minimum value near a thickness of 0.6 mm as the thickness of the ceramic substrate is reduced, and is further reduced when the thickness is further reduced. Was found to increase.
Therefore, a ceramic substrate having a thickness of about 0.6 mm is preferable.
In order to make the thickness of the conductive adhesive for fixing the semiconductor chip to the ceramic substrate 0.05 mm and to make the projection of the potting agent 0.2 mm, the depth of the concave portion formed in the ceramic substrate should be 0.35 m or more. It is preferably about 0.45 mm. In this case, the thickness of the ceramic substrate remaining at the bottom of the concave portion is 0.25 to 0.15 mm, and mechanical strength is a concern. However, according to the experiments performed by the present inventors, the mechanical strength is ensured by the thick portion at the peripheral portion, and the package is slightly warped due to the effect of the thin portion of the concave portion. It has been found that the thermal distortion of is reduced. Therefore, it was recognized that the concave portion in the ceramic substrate had a remarkable effect on improving the mounting reliability. Therefore, it is possible to provide a composite package capable of mounting a semiconductor chip with high mounting reliability and high power consumption.

【0015】セラミックス基板は、アルミナ、窒化アル
ミニウム、窒化珪素、ムライト、ガラスセラミックスの
いづれかであることが好ましい。
The ceramic substrate is preferably made of one of alumina, aluminum nitride, silicon nitride, mullite, and glass ceramic.

【0016】[0016]

【発明の実施の形態】以下、図面を参照して本発明の実
施の形態を説明する。図1は本発明の実施の形態に係る
複合パッケージの断面の概略図である。図1に示すよう
に本発明の実施の形態に係る複合パッケージは樹脂基板
2とセラミックス基板1とを接合させた樹脂・セラミッ
クス複合半導体素子用パッケージであってセラミックス
基板1に半導体チップ5を搭載するための凹部を形成し
ている。また樹脂基板2にはこの凹部に対応した開口部
が形成されている。
Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a schematic view of a cross section of a composite package according to an embodiment of the present invention. As shown in FIG. 1, the composite package according to the embodiment of the present invention is a package for a resin-ceramic composite semiconductor element in which a resin substrate 2 and a ceramic substrate 1 are joined, and a semiconductor chip 5 is mounted on the ceramic substrate 1. Recess is formed. The resin substrate 2 has an opening corresponding to the recess.

【0017】具体的には、図1に示す樹脂・セラミック
ス複合パッケージにおいて、31×31mmの大きさ
で、セラミックス基板として厚さ0.6mmの窒化アル
ミニウム(AIN)基板1を用い、この窒化アルミニウ
ム基板1に深さ0.4mmのキャビティを設けている。
キャビティはレーザー加工で開孔してもよいが、プレス
加工に所定の型を用いて加工する方法が容易である。こ
れにキャビティに対応する部分に窓部(開口部)を有し
た0.15mm厚の樹脂基板2を接着し、0.4mm厚
の半導体チップ5を厚さ0.05mmの導電性接着剤7
を用いて搭載後、ボンディングワイヤー6によりワイヤ
ーボンディングし、さらに、ポッティング剤4を用いて
ポッティング封止を行った。この場合、窒化アルミニウ
ム基板1にキャビティが設けられているため、ポッティ
ング剤4の樹脂基板2の表面からの出っ張りは0.1m
m以下に抑えることが可能となった。したがって半田ペ
ーストのスクリーン印刷が極めて容易となり、したがっ
て半田ボール3の接合が容易となった。また、このパッ
ケージの熱抵抗を測定したところ、13.6℃/Wと低
く、約4Wの許容消費電力まで対応可能であった。
Specifically, in the resin-ceramic composite package shown in FIG. 1, an aluminum nitride (AIN) substrate 1 having a size of 31 × 31 mm and a thickness of 0.6 mm as a ceramic substrate is used. 1 is provided with a cavity having a depth of 0.4 mm.
The cavity may be opened by laser processing, but a method of processing using a predetermined mold for press processing is easy. A 0.15 mm thick resin substrate 2 having a window (opening) at a portion corresponding to the cavity is bonded thereto, and a 0.4 mm thick semiconductor chip 5 is attached to a 0.05 mm thick conductive adhesive 7.
After mounting using, wire bonding was performed with a bonding wire 6, and further, potting sealing was performed using a potting agent 4. In this case, since the aluminum nitride substrate 1 has a cavity, the protrusion of the potting agent 4 from the surface of the resin substrate 2 is 0.1 m.
m or less. Therefore, the screen printing of the solder paste becomes extremely easy, and thus the joining of the solder balls 3 becomes easy. When the thermal resistance of this package was measured, it was as low as 13.6 ° C./W, and it was possible to cope with the allowable power consumption of about 4 W.

【0018】図3に示す構造において熱抵抗20℃/W
であったので、本発明の構造により6℃/Wの改善がさ
れていることがわかる。同様に図3の構造では許容消費
電力が2.5Wであるので約1.5Wの許容消費電力の
改善が得られた。
In the structure shown in FIG. 3, the thermal resistance is 20 ° C./W
It can be seen that the structure of the present invention has improved the temperature by 6 ° C./W. Similarly, in the structure of FIG. 3, the allowable power consumption is 2.5 W, so that the improvement of the allowable power consumption of about 1.5 W was obtained.

【0019】なお、キャビティの深さは0.3〜0.5
mmの範囲で適宜選んでよい。セラミックス基板1の厚
さは0.6mmに限られるものではなく、0.6mmの
近傍の厚さたとえば0.55〜1mmの値に選定しても
よい。又、樹脂基板2の厚さも0.05mm〜0.15
mm程度の範囲のものを用いてもよい。これらキャビテ
ィの深さ、セラミックス基板の厚さ、樹脂基板の厚さ等
は所定の半導体チップの厚さに対してポッティング剤の
出っ張りが0.2mm以下、好ましくは0.1mm以下
になるように設計すればよい。
The depth of the cavity is 0.3 to 0.5.
It may be appropriately selected within the range of mm. The thickness of the ceramic substrate 1 is not limited to 0.6 mm, and may be set to a thickness near 0.6 mm, for example, a value of 0.55 to 1 mm. Also, the thickness of the resin substrate 2 is 0.05 mm to 0.15.
A range of about mm may be used. The depth of these cavities, the thickness of the ceramic substrate, the thickness of the resin substrate, and the like are designed so that the protrusion of the potting agent is 0.2 mm or less, preferably 0.1 mm or less with respect to the predetermined semiconductor chip thickness. do it.

【0020】[0020]

【発明の効果】以上説明したように、本発明によれば、
半田ボール接合が容易でかつ熱抵抗の低い半導体素子用
複合パッケージを得ることができる。
As described above, according to the present invention,
It is possible to obtain a composite package for a semiconductor element in which solder ball bonding is easy and the thermal resistance is low.

【0021】また本発明によれば実装信頼性の高い半導
体素子用複合パッケージを提供することができる。
Further, according to the present invention, a composite package for a semiconductor device having high mounting reliability can be provided.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の実施の形態に係る半導体素子用複合パ
ッケージの構造を示す模式的な断面図である。
FIG. 1 is a schematic sectional view showing the structure of a composite package for a semiconductor device according to an embodiment of the present invention.

【図2】従来の半導体素子用複合パッケージの構造を示
す模式的な断面図である。
FIG. 2 is a schematic cross-sectional view showing the structure of a conventional composite package for a semiconductor device.

【図3】本発明に至る過程において本発明者らが検討し
た半導体素子用複合パッケージの構造を示す模式的な断
面図である。
FIG. 3 is a schematic cross-sectional view showing the structure of a composite package for a semiconductor device studied by the present inventors in the process leading to the present invention.

【符号の説明】[Explanation of symbols]

1 セラミックス基板 2 樹脂基板 3 半田ボール 4 ポッティング剤 5 半導体チップ 6 ボンディング・ワイヤー 7 導電性接着剤 Reference Signs List 1 ceramic substrate 2 resin substrate 3 solder ball 4 potting agent 5 semiconductor chip 6 bonding wire 7 conductive adhesive

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 半導体素子を搭載するための凹部を有す
るセラミックス基板と、 該凹部に対応する開口部を有し、前記セラミックス基板
表面に接合された樹脂基板とからなることを特徴とする
複合パッケージ。
1. A composite package comprising: a ceramic substrate having a concave portion for mounting a semiconductor element; and a resin substrate having an opening corresponding to the concave portion and bonded to a surface of the ceramic substrate. .
JP20625097A 1997-07-31 1997-07-31 Composite package Pending JPH1154665A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP20625097A JPH1154665A (en) 1997-07-31 1997-07-31 Composite package

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP20625097A JPH1154665A (en) 1997-07-31 1997-07-31 Composite package

Publications (1)

Publication Number Publication Date
JPH1154665A true JPH1154665A (en) 1999-02-26

Family

ID=16520232

Family Applications (1)

Application Number Title Priority Date Filing Date
JP20625097A Pending JPH1154665A (en) 1997-07-31 1997-07-31 Composite package

Country Status (1)

Country Link
JP (1) JPH1154665A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003500834A (en) * 1999-05-19 2003-01-07 テレフオンアクチーボラゲット エル エム エリクソン(パブル) Carrier for electronic component and method of manufacturing carrier
US6822339B2 (en) 2002-01-24 2004-11-23 Mitsubishi Denki Kabushiki Kaisha Semiconductor device
CN110137142A (en) * 2018-02-08 2019-08-16 浙江清华柔性电子技术研究院 Thermally conductive encapsulating structure, production method and the wearable device with it

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003500834A (en) * 1999-05-19 2003-01-07 テレフオンアクチーボラゲット エル エム エリクソン(パブル) Carrier for electronic component and method of manufacturing carrier
JP4758006B2 (en) * 1999-05-19 2011-08-24 テレフオンアクチーボラゲット エル エム エリクソン(パブル) Carrier for electronic component and method for manufacturing carrier
US6822339B2 (en) 2002-01-24 2004-11-23 Mitsubishi Denki Kabushiki Kaisha Semiconductor device
CN110137142A (en) * 2018-02-08 2019-08-16 浙江清华柔性电子技术研究院 Thermally conductive encapsulating structure, production method and the wearable device with it
CN110137087A (en) * 2018-02-08 2019-08-16 浙江清华柔性电子技术研究院 The production method and wearable device of thermally conductive encapsulating structure

Similar Documents

Publication Publication Date Title
JP2910670B2 (en) Semiconductor mounting structure
US6380048B1 (en) Die paddle enhancement for exposed pad in semiconductor packaging
JP3895880B2 (en) Cavity down IC package structure with thermal vias
US8487441B2 (en) Rigid wave pattern design on chip carrier substrate and printed circuit board for semiconductor and electronic sub-system packaging
JPH10256429A (en) Semiconductor package
JPH11274375A (en) Semiconductor device and its manufacture
JPH0573079B2 (en)
JPH1154665A (en) Composite package
JP3592515B2 (en) Package for semiconductor device
JPH10256428A (en) Semiconductor package
JP2000124366A (en) Mounting structure of electronic component
JP2903013B2 (en) Circuit package including metal substrate and mounting method
JPH1154646A (en) Package for semiconductor element and production thereof
JPH10256413A (en) Semiconductor package
TWI770879B (en) Electronic system, die assembly and device die
JPH1154532A (en) Package for semiconductor device
JP3470787B2 (en) Method of manufacturing composite package for semiconductor device
JPH10256414A (en) Semiconductor package
JP2831864B2 (en) Semiconductor package and manufacturing method thereof
JPH0462457B2 (en)
JP2501278B2 (en) Semiconductor package
JPS6219072B2 (en)
JP2531467B2 (en) Tape carrier package
JPH09266265A (en) Semiconductor package
TWM586454U (en) High heat dissipation performance circuit board for semiconductor module