JPS61269352A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS61269352A
JPS61269352A JP11035185A JP11035185A JPS61269352A JP S61269352 A JPS61269352 A JP S61269352A JP 11035185 A JP11035185 A JP 11035185A JP 11035185 A JP11035185 A JP 11035185A JP S61269352 A JPS61269352 A JP S61269352A
Authority
JP
Japan
Prior art keywords
substrate
full wafer
wafer
full
package
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11035185A
Other languages
Japanese (ja)
Inventor
Chiyoshi Kamata
千代士 鎌田
Kanji Otsuka
寛治 大塚
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP11035185A priority Critical patent/JPS61269352A/en
Publication of JPS61269352A publication Critical patent/JPS61269352A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE:To reduce the number of man-hours by a method wherein each full- wafer LSI fixed to several substrate is oppositely faced vertically and joined, input-output wiring leads are arranged on both surfaces of a package, a cap is fitted and a device is hermetically sealed. CONSTITUTION:A full wafer 3 is fastened onto a substrate 1 by adhesives 2. An assembly in which a full wafer 6 is fixed onto a substrate 4 consisting of the same structure by adhesives 5 is prepared, and the full wafer 3 and the full wafer 6 are oppositely faced vertically and bonded. The end sections of lead sections 9 on the upper surface of the substrate 1 and pads for the full wafer 3 mounted onto the substrate 1 are connected electrically by connector wires 10 in leads 8 extending over side surfaces and bases from upper surface at both end sections of respective substrate 1 and 4. Accordingly, the input- output signals of the full wafer 3 can be lead out of the lead sections positioned on the back of the substrate 1.

Description

【発明の詳細な説明】 〔技術分野〕 本発明は半導体装置、特に、％異な構造を備えた半導体
モジー−ルに関する。DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to semiconductor devices, and more particularly to semiconductor modules having % different structures.

〔背景技術〕[Background technology]

近時、電子回路ユニットはシステム機能の増大化にとも
なって、増々高密度、多機能化の方向にある。In recent years, as system functions have increased, electronic circuit units have become increasingly dense and multifunctional.

ＬＳＩチップの機能の増大にともなってチップから引出
すリード数も多くなってきている。As the functionality of LSI chips increases, the number of leads drawn out from the chips also increases.

ＬＳＩの１チツプ内圧すべての要求機能を収容すること
は困難な場合が多いため、実装密度を上げる手段として
、基板上に数多くのＩＣを搭載し、１つのパッケージに
したマルチチップ方式が多く行なわれている。Since it is often difficult to accommodate all the required functions within one LSI chip, a multi-chip method is often used in which many ICs are mounted on a board and packaged in one package as a means of increasing packaging density. ing.

しかし、従来のかかるマルチチップ方式は、数多くのＩ
Ｃを搭載するため、組立工数が急激に増加するし、ビン
数も増加せざるを得ないし、また、実装密度も低いもの
にとどまるなど未だ光分なものとはいえない。However, such a conventional multi-chip system has a large number of I/O
In order to mount C, the number of assembly steps increases rapidly, the number of bins has to increase, and the packaging density remains low, so it cannot be said that it is still optical.

なお、マルチチップ化について詳しく述べている文献の
例として工業調査会１９８０年１月１５日発行１’−Ｉ
Ｃ化実装技術ｊｐ１４５〜１４６及び２２６〜２２９、
工業調査会発行「電子材料」第２３巻第９号ｐ５０〜５
５並びに日経マグロウヒル社発行「日経エレクトロニク
スＪｍ２５３（１９８０）ｐ６８〜７０がある。An example of a document that describes multi-chip technology in detail is Kogyo Kenkyukai 1'-I published on January 15, 1980.
C implementation technology jp 145-146 and 226-229,
“Electronic Materials”, Vol. 23, No. 9, published by Kogyo Kenkyukai, p.50-5
5 and "Nikkei Electronics Jm253 (1980)" published by Nikkei McGraw-Hill, p.68-70.

〔発明の目的〕[Purpose of the invention]

本発明はかかる技術的背景の下新規な構造を有し、高密
度大モジエール化が可能で、パッケージ実装密度が高く
、組立工数が低減され、放熱効率が高く、高信頼性の半
導体装置（モジエール）を提供することを目的とする。The present invention has a novel structure based on this technical background, enables high-density and large modules, has high package mounting density, reduces assembly man-hours, has high heat dissipation efficiency, and is highly reliable. ).

本発明の前記ならびにそのほかの目的と新規な特徴は、
本明細書の記述および添付図面からあきらかになるであ
ろう。The above and other objects and novel features of the present invention include:
It will become clear from the description of this specification and the accompanying drawings.

〔発明の概要〕[Summary of the invention]

本願において開示される発明のうち代表的なものの概要
を簡単に説明すれば、下記のとおりである。A brief overview of typical inventions disclosed in this application is as follows.

すなわち、本発明半導体装置は、各基板に固着された各
フルウェハＬＳＩを上下に向い合わせに接合し、パッケ
ージ両面に入出力配線リードを配し、キャップを取付け
、ハーメチック封止を行って成る構造となしたもので、
クエハ同志の接合であるため従来のマルチチップに比し
て工程数が低減され、高密度大モジエール化が可能で、
パッケージ笑装密度が高くなり、パッケージ両面に入出
力配線リードを配したので入出力信号をパッケージ両面
から取り出すことができ、かつ、パッケージ両面から放
熱することができ放熱効率が高く、また、その構造上フ
ルウェハＬＳＩの接合の信頼度も高いなどの利点を有す
る半導体モジュールが得られた。That is, the semiconductor device of the present invention has a structure in which full wafer LSIs fixed to each substrate are bonded vertically facing each other, input/output wiring leads are arranged on both sides of the package, a cap is attached, and hermetic sealing is performed. What I did,
Since the chips are joined together, the number of steps is reduced compared to conventional multi-chips, and it is possible to create high-density large modules.
The packaging density of the package has been increased, and input/output wiring leads are arranged on both sides of the package, so input/output signals can be taken out from both sides of the package, and heat can be dissipated from both sides of the package, resulting in high heat dissipation efficiency. A semiconductor module having advantages such as high reliability of bonding of the upper full wafer LSI was obtained.

〔実施例〕〔Example〕

次に、本発明を、実施例に示す図面に基づいて説明する
。Next, the present invention will be explained based on drawings shown in examples.

第１図は本発明の実施例を示す断面図、第２図は、同平
面図である。なお、第１図は第２図１−１１１に沿う断
面を示す。FIG. 1 is a sectional view showing an embodiment of the present invention, and FIG. 2 is a plan view thereof. Note that FIG. 1 shows a cross section taken along the line 1-111 in FIG. 2.

基板１上に接着剤２によりフルフェノ・３を固着する。Fullfeno 3 is fixed onto the substrate 1 with adhesive 2.

同様の構造よりなる基板４に接着剤５によりフルウェハ
６が固着されたものを用意し、前記フルウェハ３と当該
フルウェハ６とを上下に向い合せにボンディングする。A full wafer 6 is fixed to a substrate 4 having a similar structure with an adhesive 5, and the full wafer 3 and the full wafer 6 are bonded vertically facing each other.

このボンディングは周知のＣＣＢ　（コントロールコラ
ップス・ボンディング）７技術により行うことができる
。このボンディングにより、基板１上にフルウェハ３が
固着され、該フルウェハ３上にフルウェハ６が向い合せ
にボンディングされ、該フルフェノ・６上に基板４が載
置された構造となる。各基板１及び４の両端部には、上
面から側面、さらに、底面にかけて、リード８を金属の
メッキ、蒸着技術などにより形成してあり、基板１の上
面のリード部９の端部と当該基板１上にマウントされた
フルウェハ３のパッド（図示せず）とをコネクタワイヤ
ｌＯにより電気的に接続する。これにより、フルフェノ
Ｓ３の入出力信号が基板１の裏面のリード部から取り出
しすることができるようになっている。This bonding can be performed by the well-known CCB (Controlled Collapse Bonding) 7 technique. By this bonding, the full wafer 3 is fixed on the substrate 1, the full wafer 6 is bonded to the full wafer 3 facing each other, and the substrate 4 is placed on the full wafer 6. Leads 8 are formed on both ends of each substrate 1 and 4 from the top surface to the side surface and further to the bottom surface by metal plating, vapor deposition technology, etc. A pad (not shown) of the full wafer 3 mounted on the wafer 1 is electrically connected to the pad (not shown) by a connector wire IO. This allows the input/output signals of the Fullpheno S3 to be taken out from the lead portion on the back surface of the board 1.

一方、基板４の表面に固着されたフルフェノ・６につい
ても、該ウェハ６のパッド（図示せず）と基板４の表面
に形成されたリード部１２の端部とをコネクタワイヤ１
０により電気的に接続し、上記フルウェハ３と同様に、
該ウェノ・６の入出力信号を基板４の裏面リード部１３
により取出しすることができるようにする。このようＫ
して形成されたパッケージ１４の端部に、第２図に示す
ように４分割されたキャップ部材１５，１６．１７゜１
８を取付け、これらキャップ部材１５〜１８と各基板１
及び４との間にできる空間（すきま）にシーリング材１
９を充填し、ハーメチックシールする。各キャップ１５
〜１８には、第１図に示すよ５Ｋ、各基板１及び４を支
持できるような溝が形成されており、当該溝内に各基板
１及び４の両端部を嵌合し、前記のごとく空間にシーリ
ング材１９を充填し、４分割された各キャップ１５〜１
８をリング状に集合させ、第２図に示すような円形形状
のキャップ２０を形成する。On the other hand, regarding the full phenol 6 fixed to the surface of the substrate 4, the connector wire 1 connects the pad (not shown) of the wafer 6 and the end of the lead part 12 formed on the surface of the substrate 4.
electrically connected by 0, similar to the above full wafer 3,
The input/output signals of the wafer 6 are connected to the back side lead part 13 of the board 4.
so that it can be taken out. K like this
At the end of the package 14 formed as shown in FIG.
8, and these cap members 15 to 18 and each board 1.
Apply sealant 1 to the space (gap) created between and 4.
9 and hermetically sealed. 15 caps each
-18, as shown in Fig. 1, are formed with grooves capable of supporting each of the substrates 1 and 4.Both ends of each of the substrates 1 and 4 are fitted into the grooves, and as described above. The space is filled with a sealant 19, and each cap 15 to 1 is divided into four parts.
8 are assembled in a ring shape to form a circular cap 20 as shown in FIG.

本発明においては、パッケージ１４０基板１の上面に冷
却フィン２１を取付けるとよい。尚第２図では該フィン
の図示を省略しである。In the present invention, it is preferable to attach the cooling fins 21 to the upper surface of the package 140 substrate 1. Note that the fins are not shown in FIG. 2.

本発明における各フルウェハ３及び６は、例えばシリコ
ン単結晶基板から成り、周知の技術によってこのウェハ
内には多数の回路素子が形成され、１つの回路機能が与
えられて跡る。Each full wafer 3 and 6 in the present invention consists of, for example, a silicon single crystal substrate, in which a large number of circuit elements are formed using well-known techniques and provided with a single circuit function.

回路素子の具体例は、例えばＭＯＳ）ランジスタから成
り、これらの回路素子によって、例えば論理回路の回路
機能が形成されている。A specific example of the circuit element is, for example, a MOS (MOS) transistor, and these circuit elements form the circuit function of, for example, a logic circuit.

本発明に使用される基板１及び４は、上記Ｓｉフルウェ
ハとの熱膨張係数をマツチングするために、ＳｉＣによ
り構成されていることが好ましい。The substrates 1 and 4 used in the present invention are preferably made of SiC in order to match the coefficient of thermal expansion with the Si full wafer.

接着剤２及び５も同様の理由からＳｉ系ゴムやゲル接着
剤を使用することが好ましい。For the same reason, it is preferable to use Si-based rubber or gel adhesive for the adhesives 2 and 5.

入出力配線リード８は、例えばタングステンにより構成
されている。The input/output wiring lead 8 is made of tungsten, for example.

コネクタワイヤ１０は例えばＡ！線やＡｕ線より成る。For example, the connector wire 10 is A! It consists of wires and Au wires.

キャップ２０は、上記基板と同様のＳｉＣにより構成す
ることが好ましい。The cap 20 is preferably made of SiC similar to the substrate described above.

シーリング材１９は、上記接着剤と同様のＳｉ系ゴムや
ゲルを使用することが好ましい。As the sealing material 19, it is preferable to use Si-based rubber or gel similar to the adhesive described above.

〔効果〕〔effect〕

［１１本発明によれば高密度大モジュール化が可能とな
った。[11 According to the present invention, high-density and large-scale modularization has become possible.

（２）本発明によればパッケージ実装が向上し、特に、
本発明パッケージをユニットとして次々と重ねて実装す
ることにより実装密度を飛躍的に向上させることが出来
た。(2) According to the present invention, package mounting is improved, and in particular,
By mounting the packages of the present invention one after another as a unit, it was possible to dramatically improve the packaging density.

（３１本発明によればウェハ同志の接合である為マルチ
チップモジュールに比べて組立工程を少なくすることが
できた。(31 According to the present invention, since wafers are bonded together, the number of assembly steps can be reduced compared to a multi-chip module.

（４１本発明によれば入出力信号をパッケージ両面から
取り出すことが可能となった。(41 According to the present invention, it has become possible to extract input/output signals from both sides of the package.

（５）本発明によればウェハが上下に接合されているの
で、当該接合部の信頼度が高いものとすることができた
。(5) According to the present invention, since the wafers are bonded vertically, the reliability of the bonded portion can be made high.

（６１本発明によれば両面から放熱することができ、放
熱効率を高いものとすることができた。(61 According to the present invention, heat can be radiated from both sides, and the heat radiation efficiency can be made high.

（７１本発明によれば大モジュールが可能で、大型コン
ビエータにも一個ないし二個程度組み込めば足りるとい
う利点ケ有する。(71) According to the present invention, a large module is possible, and it has the advantage that it is sufficient to incorporate one or two modules into a large comviator.

以上本発明者によってなされた発明を実施例にもとづ宮
具体的に説明したが、本発明は上記実施例に限定される
ものではなく、その要旨を逸脱しない範囲で檻々変更可
能であることはいうまでもない。Although the invention made by the present inventor has been specifically explained above based on examples, the present invention is not limited to the above-mentioned examples, and can be modified at will without departing from the gist of the invention. Needless to say.

例えば、前記実施例ではフルウェハＬＳＩを二個接合す
る例を示したが、二個以上でもよく、また、実施例に示
した装置を一ユニットとして複数個組み合せたものでも
よい。また、ウエノ・に代えてチップでもよい。For example, in the above embodiment, an example was shown in which two full wafer LSIs were bonded, but two or more full wafer LSIs may be bonded, or a plurality of devices shown in the embodiment may be combined as one unit. Also, chips may be used instead of Ueno.

また、キャップを四分割する例を示したが、その他二分
割等他の態様でもよい。Further, although an example in which the cap is divided into four parts has been shown, other embodiments such as two divisions may be used.

さらに、キャップを円形とした例を示したが、角形等地
の形状でもよい。Further, although an example is shown in which the cap is circular, it may also have a rectangular shape.

〔利用分野〕 本発明は各種の半導体モジュールに適用できる。[Application field] The present invention can be applied to various semiconductor modules.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は本発明の実施例を示す断面図、第２図は本発明
の実施例を示す平面図である。 １・・・基板、２・・・接着剤、３・・・ウェハ、４・
・・基板、５・・・接着剤、６・・・ウェハ、７・・・
ＣＣＢ、８・・・リード、９・・・リード部、１０−・
・コネクタワイヤ、１１・・・リード部、１２−・・リ
ード部、１３−・・リード部、１４・・・パッケージ、
１５・・・キャップ部材、１６・・・キャップ部材、１
７・・・キャップ部材、１８・・・キャップ部材、１９
・・・シーリング材、２０・・・キャップ。 第　　１　　図 第　　２　　図FIG. 1 is a sectional view showing an embodiment of the invention, and FIG. 2 is a plan view showing an embodiment of the invention. 1...Substrate, 2...Adhesive, 3...Wafer, 4...
... Substrate, 5... Adhesive, 6... Wafer, 7...
CCB, 8... Lead, 9... Lead part, 10-.
・Connector wire, 11... Lead part, 12-... Lead part, 13-... Lead part, 14... Package,
15... Cap member, 16... Cap member, 1
7... Cap member, 18... Cap member, 19
...Sealing material, 20...Cap. Figure 1 Figure 2

Claims (1)

【特許請求の範囲】 １、複数の半導体ウェハ又はチップを上下に向い合せに
接合してなる構造を有し、パッケージ両面に入出力配線
リードを有し、かつ、キャップにより、前記ウェハ又は
チップを固着している基板を支持し、封止して成ること
を特徴とする半導体装置。 ２、特許請求の範囲第１項記載の装置において、放熱フ
ィン又はスタッドをパッケージに取付してなることを特
徴とする、特許請求の範囲第１項記載の半導体装置。[Claims] 1. It has a structure in which a plurality of semiconductor wafers or chips are bonded vertically facing each other, has input/output wiring leads on both sides of the package, and has a cap that connects the wafers or chips. A semiconductor device characterized by supporting and sealing a fixed substrate. 2. The semiconductor device according to claim 1, characterized in that a radiation fin or a stud is attached to the package in the device according to claim 1.
JP11035185A 1985-05-24 1985-05-24 Semiconductor device Pending JPS61269352A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11035185A JPS61269352A (en) 1985-05-24 1985-05-24 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11035185A JPS61269352A (en) 1985-05-24 1985-05-24 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS61269352A true JPS61269352A (en) 1986-11-28

Family

ID=14533561

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11035185A Pending JPS61269352A (en) 1985-05-24 1985-05-24 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS61269352A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5150196A (en) * 1989-07-17 1992-09-22 Hughes Aircraft Company Hermetic sealing of wafer scale integrated wafer
US7112468B2 (en) 1998-09-25 2006-09-26 Stmicroelectronics, Inc. Stacked multi-component integrated circuit microprocessor

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5150196A (en) * 1989-07-17 1992-09-22 Hughes Aircraft Company Hermetic sealing of wafer scale integrated wafer
US7112468B2 (en) 1998-09-25 2006-09-26 Stmicroelectronics, Inc. Stacked multi-component integrated circuit microprocessor

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