JPS6129158A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS6129158A JPS6129158A JP14948684A JP14948684A JPS6129158A JP S6129158 A JPS6129158 A JP S6129158A JP 14948684 A JP14948684 A JP 14948684A JP 14948684 A JP14948684 A JP 14948684A JP S6129158 A JPS6129158 A JP S6129158A
- Authority
- JP
- Japan
- Prior art keywords
- dam
- cap
- semiconductor element
- substrate
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15312—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a pin array, e.g. PGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16195—Flat cap [not enclosing an internal cavity]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Engineering & Computer Science (AREA)
- Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔技術分野〕
本発明は半導体装置に関し、特に、半導体装置の効率の
良い放熱技術に関する。DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a semiconductor device, and more particularly to an efficient heat dissipation technique for a semiconductor device.
本発明者によって半導体素子（ベレット）にかかる応力
が少なくて済み、かつ、半導体素子や該素子の内部配線
を外部に引出するコネクタワイヤとの接合性が良く、さ
らに、耐湿性に優れた、シリコーンゲルを封止材とする
半導体装置が考えられて℃・る。The present inventor has developed a silicone material that requires less stress on the semiconductor element (bullet), has good bonding properties with the semiconductor element and the connector wire that leads the internal wiring of the element to the outside, and has excellent moisture resistance. Semiconductor devices using gel as an encapsulant have been considered.
しかし、シリコーンゲルを封止材として用いるため、半
導体素子から発生される熱の放出性があまり良くないこ
とがわかった。０ＭＯ８ＩＣ等のように発熱量の小さい
ＩＣを封止した場合はあまり問題とはならないが、高速
型バイポーラＩＣのように発熱量の大きいＩＣの場合に
は放熱性が問題になることがわかった。However, since silicone gel is used as the sealing material, it has been found that the release of heat generated from the semiconductor element is not very good. It has been found that heat dissipation becomes a problem when an IC that generates a small amount of heat, such as an 0MO8 IC, is sealed, but not so much when an IC that generates a large amount of heat, such as a high-speed bipolar IC.
本発明は半導体素子で発生する熱を効率よくパッケージ
の外部に逃がし、パッケージの熱抵抗を低減した半導体
装置を提供することを目的としたものである。SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device in which heat generated in a semiconductor element is efficiently released to the outside of a package, and the thermal resistance of the package is reduced.
本発明の前記ならびにそのほかの目的と新規な特徴は、
本明細書の記述および添付図面からあきらかになるであ
ろう。The above and other objects and novel features of the present invention include:
It will become clear from the description of this specification and the accompanying drawings.
本願において開示される発明のうち代表的なものの概要
を簡単に説明すれば、下記のとおりである。A brief overview of typical inventions disclosed in this application is as follows.
すなわち、半導体素子から発生した熱の伝導経路として
半導体素子の発熱が効率よくパッケージの外部に伝わる
ように、ダムとキャップのそれぞれの材質を熱伝導率の
大きいセラミック材料又は金属材料としたことにある。In other words, the dam and the cap are each made of a ceramic material or a metal material with high thermal conductivity so that the heat generated by the semiconductor element can be efficiently transmitted to the outside of the package as a conduction path for the heat generated from the semiconductor element. .
本発明の半導体装置の構造を、第１図に示す。 The structure of the semiconductor device of the present invention is shown in FIG.
実装基板１上に接合材料２により半導体素子３を搭載（
固着）し、該半導体素子３と実装基板１上に形成された
基板配線４とをコネクタワイヤ５により結線し、基板配
線４を実装基板１に多数立設されたビン６に接続し、実
装基板１上に接合部材７によりダム８を固着し、少なく
とも半導体素子３と、コネクタワイヤ６による結線部上
をシリコーンゲル９で封止し、ダム８上にキャップ１０
を接合材料１１により取付して成る。本発明に従えばダ
ム８およびキャップ１１はセラミック材料または金属材
料よりなる。A semiconductor element 3 is mounted on a mounting board 1 using a bonding material 2 (
The semiconductor element 3 and the board wiring 4 formed on the mounting board 1 are connected by a connector wire 5, and the board wiring 4 is connected to a number of pins 6 erected on the mounting board 1. A dam 8 is fixed onto the dam 8 by a bonding member 7, at least the semiconductor element 3 and the connecting portion formed by the connector wire 6 are sealed with a silicone gel 9, and a cap 10 is attached onto the dam 8.
are attached by bonding material 11. According to the invention, the dam 8 and the cap 11 are made of ceramic or metal material.
上記シリコーンゲル９の形成は、例えば、ゾル状態のシ
リコーン系のシーリング剤を半導体素子３土にボッティ
ングし、当該シーリング剤を熱硬化して、ゲル化するこ
とにより形成される。ダム８はかかるゾルの流れ止めに
使用され、第１図に示すように、実装基板１とダム８と
で区画される空間内にシリコーンゲル９が形成され、半
導体素子３はこのゲルにより封止される。当該シーリン
グ剤としては、例えば信越化学工業（株）社製ＫＪＲ９
０１０（商品名）が使用される。このシリコーンゲルは
前述のように耐湿性に優れ、半導体素子との接合性が良
いので、良好な封止性を達成するのであるが、このゲル
は膨潤に似た状態にあるので、半導体素子３やコネクタ
ワイヤ５を外的環境から機械的に保護するためにダム８
上にキャンプ１０を取付けて（・る。この半導体装置は
、多数のピン６が立設されており、当該ピン６を介して
プリント配線基板などに容易に実装することができる。The silicone gel 9 is formed, for example, by bottling a silicone sealing agent in a sol state onto the semiconductor element 3 soil, heat-curing the sealing agent, and turning it into a gel. The dam 8 is used to stop the flow of the sol, and as shown in FIG. 1, a silicone gel 9 is formed in the space defined by the mounting board 1 and the dam 8, and the semiconductor element 3 is sealed with this gel. be done. As the sealant, for example, KJR9 manufactured by Shin-Etsu Chemical Co., Ltd.
010 (product name) is used. As mentioned above, this silicone gel has excellent moisture resistance and good bonding properties with the semiconductor element, so it achieves good sealing performance.However, since this gel is in a state similar to swelling, the semiconductor element A dam 8 is used to mechanically protect the wires and connector wires 5 from the external environment.
A camp 10 is attached on top of the semiconductor device. This semiconductor device has a large number of pins 6 erected, and can be easily mounted on a printed wiring board or the like via the pins 6.
ところで、本発明者がこのよ５な半導体装置について、
実装基板１をガラス材料とエポキシ樹脂より爬せられた
ガラスエポキシ基板とし、ダム８およびキャップ１０を
同様の材料で構成したところ、かかるガラスエポキシは
熱伝導率が非常に小さい為、半導体素子３で発生した熱
がパンケージの外部に伝導しにくいという欠点があるこ
とが判った。By the way, regarding these five semiconductor devices, the inventor has
When the mounting board 1 is a glass epoxy board made of glass material and epoxy resin, and the dam 8 and cap 10 are made of the same material, the glass epoxy has very low thermal conductivity. It has been found that the disadvantage is that the heat generated is difficult to conduct to the outside of the pan cage.
第２図は半導体チップで発生した熱の伝導経路を示した
ものであるが、半導体チップ３から発生した熱の一部は
、封止剤（シリコーンゲル）９゜ダム８．キャップ１０
を経由してハノケージ外部に逃げ、一部、コネクタワイ
ヤ例えばＡｌワイヤ５、基板配線４．ダム８．キャップ
１０を経由してパッケージ外部に逃げるが、この熱の伝
導経路を考えるときには、ダム８とキャップ１０が放熱
に重要な役割を果たしていることが判る。FIG. 2 shows the conduction path of heat generated in the semiconductor chip. A part of the heat generated from the semiconductor chip 3 is transferred to the sealing agent (silicone gel) 9° dam 8. cap 10
Some of the connector wires, such as Al wires 5, board wiring 4. Dam 8. The heat escapes to the outside of the package via the cap 10, but when considering the conduction path of this heat, it can be seen that the dam 8 and the cap 10 play an important role in heat radiation.
ダム８およびキャップ１１を構成するセラミック材料と
しては、例えば、一般に、気密封止型の半導体装置のキ
ャップを構成するアルミナを焼結して成るアルミナセラ
ミックが使用され、金属材料としては、例えばアルミニ
ウムが使用される。As the ceramic material constituting the dam 8 and the cap 11, for example, an alumina ceramic made by sintering alumina that constitutes the cap of a hermetically sealed semiconductor device is generally used, and as the metal material, for example, aluminum is used. used.
第１表にガラスエポキシとアルミナセラミックとアルミ
ニウムとの熱伝導率の比較データを、また、第２表にこ
れら材料による第１図に示すような７２ビン数を有する
グリッドアレイタイプのパッケージの熱抵抗の比較デー
タを示した。Table 1 shows comparative data on the thermal conductivity of glass epoxy, alumina ceramic, and aluminum, and Table 2 shows the thermal resistance of a grid array type package with 72 bins as shown in Figure 1 using these materials. Comparative data was shown.
第１表
第２表
第１表および第２表の結果からダム、キャップをアルミ
ナセラミック、アルミニウムとすることにより低熱抵抗
のパッケージが得られることが判る。From the results in Tables 1 and 2, it can be seen that a package with low thermal resistance can be obtained by using alumina ceramic or aluminum for the dam and cap.
第１図における、半導体素子３は、例えばシリコーン単
結晶基板から成り、周知の技術によって、この半導体素
子（チップ）内には多数の回路素子が形成され、１つの
回路機能を与えている。回路素子は、例えば０ＭＯ８か
ら成り、これらの回路素子によって、例えば論理回路お
よびメモリ回路機能が形成されている。The semiconductor element 3 in FIG. 1 is made of, for example, a silicon single crystal substrate, and a large number of circuit elements are formed within this semiconductor element (chip) by a well-known technique to provide one circuit function. The circuit elements are made of, for example, 0MO8, and these circuit elements form, for example, a logic circuit and a memory circuit function.
半導体素子３を実装基板１上にマウントする際に使用さ
れる接合材料２やダム８を固着する接合材料７やキャッ
プ１０を取付する接合材料１１には、例えばエポキシ系
樹脂系接着剤■またはシリコーン系樹脂接着剤が使用さ
れる。The bonding material 2 used when mounting the semiconductor element 3 on the mounting board 1, the bonding material 7 for fixing the dam 8, and the bonding material 11 for attaching the cap 10 include, for example, an epoxy resin adhesive or silicone. A resin adhesive is used.
基板配線４は、例えば、アルミニウムにより構成され、
例えば周知のプリント配線技術により形成すればよい。The board wiring 4 is made of aluminum, for example,
For example, it may be formed using a well-known printed wiring technique.
ビン６は第２図に示すように、半導体基板３に９設され
たスルーホールを介して上記基板配線４と接続しており
、このビン７６は半田１２により実装基板１に立設され
る。As shown in FIG. 2, the vial 6 is connected to the substrate wiring 4 through nine through holes provided in the semiconductor substrate 3, and the vial 76 is erected on the mounting substrate 1 with solder 12.
し効果］
本発明によれば、ダムおよびキャップを熱伝導率の良い
セラミック材料または金属材料としたので、半導体素子
から発生した熱が熱伝導の良いダム、キャップを経由し
てパッケージ外部に容易に逃がすことができる。したが
って、パッケージの熱抵抗を大幅に低減することができ
た。According to the present invention, since the dam and the cap are made of a ceramic material or a metal material with good thermal conductivity, the heat generated from the semiconductor element is easily transferred to the outside of the package via the dam and the cap with good thermal conductivity. You can escape. Therefore, the thermal resistance of the package could be significantly reduced.
以上本発明者によってなされた発明を実施例にもとつき
具体的に説明したが、本発明は上記実施例に限定される
ものではなく、その要旨を逸脱しない範囲で種々変更可
能であることはいうまでもない。Although the invention made by the present inventor has been specifically explained above based on examples, the present invention is not limited to the above examples, and it is understood that various changes can be made without departing from the gist of the invention. Needless to say.
例えば、前記実施例では実装基板の平面に半導体素子を
搭載する例を示したが実装基板に半導体素子を搭載する
ための溝部を設け、該溝部に半導体素子を搭載してもよ
い。また、前記実施例ではシリコーンゲル封止剤の上部
とキャンプの裏面との間に空隙を設けた例を示したが、
該封止剤上部をキャップ裏面に密着させ、放熱性をより
一層高めてもよい。For example, in the above embodiment, the semiconductor element is mounted on the plane of the mounting board, but the mounting board may be provided with a groove for mounting the semiconductor element, and the semiconductor element may be mounted in the groove. Further, in the above example, an example was shown in which a gap was provided between the top of the silicone gel sealant and the back surface of the camp.
The upper part of the sealant may be brought into close contact with the back surface of the cap to further enhance heat dissipation.
〔利用分野］
本発明はシリコーンゲルを封止剤とし、ダムおよびキャ
ップを備えている限り、他の６謹半導体装置に適用する
ことが可能であり、実装基板としてガラスエポキシ基板
を使用する場合だけでなく、他の基板例えば有機材料プ
リント配線基板を使用する場合やパッケージのタイプと
してもビングリッドアレイタイプだけでなくチップキャ
リア、７ラツトバツクパツケージ、デュアルインライン
（Ｄ Ｉ Ｌ’）など各種パッケージに適用できる。ま
た、熱抵抗の低減が必要な大規模なマルチチップパッケ
ージにも有用である。[Field of Application] The present invention can be applied to other types of semiconductor devices as long as they use silicone gel as a sealant and are equipped with a dam and a cap, and are applicable only when a glass epoxy substrate is used as the mounting substrate. In addition, it can be applied to other substrates such as organic material printed wiring boards, and to various types of packages such as bin grid array types, chip carriers, 7-lat back packages, dual in-line (DIL'), etc. can. It is also useful for large-scale multi-chip packages that require reduced thermal resistance.
第１図は本発明の実施例を示す断面図、第２図は半導体
素子から発生した熱の伝導経路を説明する本発明実施例
要部断面図である。
１・・・実装基板、２・・・接合材料、３・・・半導体
素子、４・・・基板配線、訃・・コネクタワイヤ、６・
・・ビン、７・・・接合材料、８・・・ダム、９・・・
シリコーンゲル（封止剤）、１０・・・キャップ、１１
・・・接合材料、第 １ 図
第 ２ 図
／θFIG. 1 is a sectional view showing an embodiment of the present invention, and FIG. 2 is a sectional view of a main part of the embodiment of the present invention, illustrating a conduction path of heat generated from a semiconductor element. DESCRIPTION OF SYMBOLS 1... Mounting board, 2... Bonding material, 3... Semiconductor element, 4... Board wiring, End... Connector wire, 6...
...Bin, 7...Joining material, 8...Dam, 9...
Silicone gel (sealant), 10... Cap, 11
...Joining material, Fig. 1 Fig. 2/θ
Claims (1)
素子を、シリコーンゲルで封止して成り、かつ、前記実
装基板上にダムを介してキャップを取付けて成る半導体
装置であって、前記ダムおよびキャップをセラミック材
料または金属材料により構成したことを特徴とする半導
体装置。 ２、実装基板がガラスエポキシ基板である、特許請求の
範囲第１項記載の半導体装置。[Claims] 1. A semiconductor device comprising a semiconductor element mounted on a mounting board, at least the element sealed with silicone gel, and a cap attached to the mounting board via a dam. A semiconductor device, wherein the dam and the cap are made of a ceramic material or a metal material. 2. The semiconductor device according to claim 1, wherein the mounting board is a glass epoxy board.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59149486A JPH0658939B2 (en) | 1984-07-20 | 1984-07-20 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59149486A JPH0658939B2 (en) | 1984-07-20 | 1984-07-20 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6129158A true JPS6129158A (en) | 1986-02-10 |
| JPH0658939B2 JPH0658939B2 (en) | 1994-08-03 |
Family
ID=15476203
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59149486A Expired - Lifetime JPH0658939B2 (en) | 1984-07-20 | 1984-07-20 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0658939B2 (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4916522A (en) * | 1988-04-21 | 1990-04-10 | American Telephone And Telegraph Company , At & T Bell Laboratories | Integrated circuit package using plastic encapsulant |
| JPH02254745A (en) * | 1989-03-28 | 1990-10-15 | Nec Corp | Chip carrier |
| WO2000013233A1 (en) * | 1998-08-28 | 2000-03-09 | Amkor Technology, Inc. | Electromagnetic interference shield device and method |
| US6448635B1 (en) | 1999-08-30 | 2002-09-10 | Amkor Technology, Inc. | Surface acoustical wave flip chip |
| US6614102B1 (en) | 2001-05-04 | 2003-09-02 | Amkor Technology, Inc. | Shielded semiconductor leadframe package |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5856445A (en) * | 1981-09-30 | 1983-04-04 | Nec Corp | Multilayer ceramic package |
-
1984
- 1984-07-20 JP JP59149486A patent/JPH0658939B2/en not_active Expired - Lifetime
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5856445A (en) * | 1981-09-30 | 1983-04-04 | Nec Corp | Multilayer ceramic package |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4916522A (en) * | 1988-04-21 | 1990-04-10 | American Telephone And Telegraph Company , At & T Bell Laboratories | Integrated circuit package using plastic encapsulant |
| JPH02254745A (en) * | 1989-03-28 | 1990-10-15 | Nec Corp | Chip carrier |
| WO2000013233A1 (en) * | 1998-08-28 | 2000-03-09 | Amkor Technology, Inc. | Electromagnetic interference shield device and method |
| US6092281A (en) * | 1998-08-28 | 2000-07-25 | Amkor Technology, Inc. | Electromagnetic interference shield driver and method |
| US6472598B1 (en) | 1998-08-28 | 2002-10-29 | Amkor Technology, Inc. | Electromagnetic interference shield device with conductive encapsulant and dam |
| US6601293B1 (en) | 1998-08-28 | 2003-08-05 | Amkor Technology, Inc. | Method of making an electromagnetic interference shield device |
| US6448635B1 (en) | 1999-08-30 | 2002-09-10 | Amkor Technology, Inc. | Surface acoustical wave flip chip |
| US6614102B1 (en) | 2001-05-04 | 2003-09-02 | Amkor Technology, Inc. | Shielded semiconductor leadframe package |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0658939B2 (en) | 1994-08-03 |
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