JPS63261767A - Manufacture of superconducting transistor - Google Patents

Abstract

PURPOSE:To secure source and drain electrodes at a distance within a suitable extent and to make thin the thickness of a gate insulating film to contrive the improvement of uniformity and reproducibility of the characteristics of a device and the improvement of a circuit yield, by a method wherein the process for forming the gate insulating film and a control electrode is executed earlier than the process for forming the source and drain electrodes consisting of superconductor. CONSTITUTION:For example, the surface of an Si semiconductor substrate 1 is thermally oxidized in an oxygen-containing atmosphere to form an insulating film 2. A superconductor 3 which is used as a control electrode is formed and a resist 4 for an electron beam is coated thereon. Then, a resist pattern is formed, an Al metal thin film 5 is deposited on this pattern, a lift-off is performed to form a metal mask, a plasma etching is performed using this metal mask as a mask to remove the substrate 1 and a processing is performed in the form of a protrusion of a prescribed width to form a gate insulating film 7 and the control electrode 8. P ions are introduced in the substrate 1 using the film 5 as a mask to form a high-concentration impurity introduced layer 9 and an activating treatment is executed. A superconductive thin film is formed by an electron beam deposition method and a top layer is etched away from the film 5 to form source and drain electrodes 10 and 11.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a superconducting transistor that operates at extremely low temperatures and a method for manufacturing the same, and particularly to a superconducting transistor that operates at extremely low temperatures and a method for manufacturing the same. , relates to a superconducting transistor suitable for increasing circuit gain and a method for manufacturing the same.

[Conventional technology]

A superconducting transistor whose operating principle is to control the value of superconducting current flowing between two superconducting electrodes provided in contact with a semiconductor by changing the superconducting near-field effect by applying a voltage to a control electrode. For more information, see Journal of Applied Physics, Vol. 51, p. 2736 (1980) (Journal of Appl.
ied Physics vo Q, 51 (19
80)).

[Problem that the invention seeks to solve]

The above conventional technology aims at realizing a field effect type superconducting element. That is, by applying an electric field to the control electrode through the gate insulating film, the carrier concentration in the semiconductor channel is changed, and the superconducting proximity effect is modulated, thereby increasing the source
The idea is to control the superconducting current that flows between the drain electrodes when the voltage is zero. In order to generate the superconducting proximity effect, the distance between the two superconductors that form the source and drain electrodes must be approximately 10 times the electron pair coherence length of the superconductors, that is, 0.2 μm or less. . If it is smaller than this range, the coupling between the superconducting electrodes will be too strong, making it difficult to control the control electrode, leading to problems such as a decrease in the gain of the superconducting transistor, for example. On the other hand, if it is larger than this range, superconducting weak bonds will not be formed;
Superconducting current does not flow. It was difficult to secure this distance, form a gate insulating film here, and place a gate electrode thereon.

An object of the present invention is to provide a method for manufacturing a superconducting transistor that is suitable for high integration and improves uniformity and reproducibility of device characteristics as well as circuit gain.

[Means for solving problems]

The above purpose is to perform the gate insulating film and control electrode manufacturing process before the source/drain electrode formation process made of superconductor, thereby ensuring a suitable distance between the source and drain electrodes and gate insulation. This is achieved by reducing the thickness of the film and forming the impurities in the semiconductor in a suitable distribution.

[Effect]

By forming the gate insulating film and control electrode in advance and processing them all at once to the required dimensions, the thickness of the gate insulating film can be minimized, improving single circuit gain, and furthermore, the gate insulating film can be heated to temperatures of 1000°C or higher. If this process is used when forming superconducting electrodes by high-temperature thermal oxidation, deterioration of the characteristics of the superconducting electrode can be prevented. Further, since impurities can be introduced using the control electrode as a mask, it becomes easy to introduce impurities with a suitable distribution. Furthermore, by maintaining the insulation between the source/train electrode and the control electrode, the distance between the source and drain can be made approximately 10 times the coherence length, which improves reliability and enables higher gain and higher speed. Become.

〔Example〕

Hereinafter, the present invention will be explained in detail with reference to Examples.

A first embodiment of the present invention will be described using FIG. 1st
Figures (a) to (h) show the manufacturing steps in order, and (h) shows the structure of the completed superconducting transistor.

As shown in FIG. 1(a), the surface of a Si semiconductor substrate 1 containing impurities of 1×1014a11-δ or less is
Thermal oxidation is performed in an oxygen atmosphere at a temperature of 0.degree. C. to form an insulating film 2 with a J width of approximately 80 nm. Next, a superconductor 3 made of Nb to be a control electrode with a thickness of about 1100 nm is formed by DC magnetron sputtering (Fig. 1(b)), and then P is deposited on top of it.
An electron beam resist 4 such as MMA was applied to a thickness of about 500 nm. Next, a resist pattern with a gap of 0.2 μm in width is formed using an electron beam lithography method. Next, a metal thin film 5 made of AQ with a thickness of 30 nm is deposited on this resist pattern using a resistance heating method (see Fig. 1). d)) Soaked in an acetone solution and lifted off to a width of 0.2μ as shown in Figure 1(e).
A metal mask with a diameter of less than m was formed. Next, using this as a mask, plasma etching using CFc gas was performed.
The Si substrate 1 was removed by etching 200 nm, and the width was 0.2 nm.
Gate insulating film 7. Processed into a protrusion shape of μm or less. A control electrode 8 is formed. Immediately thereafter, P ions are introduced into the semiconductor substrate 1 by an ion implantation method using the metal thin film 5 as a mask to form a high concentration impurity introduction layer 9 having an impurity concentration of 1×10 18 G −8 or more, and an activation process is performed. In this case, since the high-concentration impurity-introduced layer 9 is formed in a self-aligned manner, this end reaches the semiconductor directly below the control electrode 8, and this portion effectively affects the gain of the device. In addition,
In the center of the semiconductor protrusion, there is an impurity concentration of 1×1018■
−3 or less channels 6 are formed (Fig. 1(f)
).

Next, a superconducting thin film made of Nb with a thickness of 200 nm is formed by electron beam evaporation, and then the upper layer of the metal thin film 5 is etched and removed to form the source electrode 10. A drain electrode 11 was formed, and a superconducting transistor having the structure shown in FIG. 1(h) could be obtained.

In the superconducting transistor manufactured by the method described above, by forming the gate insulating film and the gate electrode first, it is possible to maintain the insulation between the source/drain electrode and the control electrode while forming the channel width with high precision. The thickness of the gate insulating film can be minimized, and after installing the superconducting electrode,
No high-temperature process steps are involved. Therefore, reproducibility,
Uniformity.

Improved reliability. Device characteristics such as circuit gain and operating speed have also been improved.

Next, a second embodiment of the present invention will be described using FIG.

2(a) to 2(g) sequentially show the manufacturing steps, and FIG. 2(g) shows the structure of the completed superconducting transistor.

As shown in FIG. 2(a), the surface of a Si semiconductor substrate 1 containing less than lXl0"m"'8'8 is thermally oxidized in an oxygen atmosphere at 1200°C, and an insulating film 2 with a thickness of about 80 nm is formed. form. Next, a Nb superconductor 3 to be a control electrode with a thickness of about 200 nm is formed by DC magnetron sputtering, and an electron beam resist 4 such as PMMA is applied on top of the Nb superconductor 3 with a thickness of about 5 nm.
A thickness of 00 nm was applied. (FIG. 2(b)) Next, a resist pattern with a width of 0.2 μm was formed using an electron beam lithography method, and plasma etching was performed using this as a mask to form the gate electrode 8. Next, using this as a mask, P ions are introduced into the semiconductor substrate 1 by an ion implantation method to form a high concentration impurity introduction layer 9 having an impurity concentration of 1×10 180 −8 or more, and an activation process is performed. In this case, since the high-concentration impurity-introduced layer 9 is formed in a self-aligned manner, its end reaches the semiconductor directly below the control electrode 8, which effectively works to improve the gain of the device. Note that a channel 6 having an impurity concentration of 1X1018<-3> or less is formed directly below the center of the control electrode 8. Next, the side wall of the control electrode 8 is oxidized in oxygen plasma to form an interlayer insulating film 12, and then, in order to remove the insulating film other than the lower part of the control electrode 8, plasma etching is performed with CF4 gas using the resist 4 as a mask. (Fig. 2(e)). Then, after depositing a superconducting thin film of Nb with a thickness of 200 nm by electron beam evaporation,
Lift-off was performed by immersing it in acetone to form a source electrode 10 and a drain electrode w1.8, and a superconducting transistor having the structure shown in FIG. 2(g) could be obtained.

In the superconducting transistor manufactured by the method described above, the width of the channel can be formed with high accuracy, and the source/drain electrodes and the control electrode can be electrically separated. Therefore, reproducibility,
It has high uniformity and reliability, and has improved device characteristics such as circuit gain and operating speed.

In this example, Nb was used as the material of the superconducting electrode, but Nb N, N bas i , N baG e
Nb compounds such as Pb, Pb-Au,
Pb-In.

Similar effects can be obtained even when pb gold alloys such as Pb-In-Au and Pb-B1 are used.

In addition to the Si semiconductor, the semiconductor substrate also contains G e.

Ga As, In As, In P
, I n S b, etc. may be used. Although AQ was used as the metal thin film serving as a mask, similar effects can be obtained by using silicides such as Au, tungsten silicide, and molybdenum silicide.

〔Effect of the invention〕

As described above, according to the present invention, superconducting transistors can be manufactured with high reproducibility, uniformity, and high precision. Furthermore, the thickness of the gate oxide film can be minimized, and it becomes easier to control the channel portion to a suitable size and the impurity distribution of the semiconductor, thereby improving circuit gain and operating speed. Therefore, it is possible to easily provide a highly integrated superconducting logic circuit.

[Brief explanation of the drawing]

FIG. 1 and FIG. 2 are cross-sectional views for explaining the manufacturing process of a superconducting transistor showing an embodiment of the present invention. DESCRIPTION OF SYMBOLS 1... Semiconductor substrate, 2... Insulating film, 3... Superconductor, 4... Resist, 5... Metal thin film, 6... Channel, 7... Gate isolation ana, 8 ...control electrode,
9... High concentration impurity introduced layer, 10... Source electrode,
11...Drain electrode, 12...Interlayer insulating film.

Claims (1)

[Claims] 1. At least two superconducting electrodes formed facing each other in contact with the semiconductor, and 2.
sandwiched between one high concentration impurity layer and the high concentration impurity layer,
A step of forming at least the control electrode in a superconducting element having a channel portion into which an impurity at a lower concentration is introduced, and a control potential provided over the upper portion of the channel of the semiconductor in the opposing portion of the superconducting electrode; A method for manufacturing a superconducting transistor, comprising sequentially forming the high concentration impurity layer and forming the two superconducting electrodes.