JPS62131588A - Manufacture of superconductive transistor - Google Patents

Manufacture of superconductive transistor

Info

Publication number
JPS62131588A
JPS62131588A JP60271462A JP27146285A JPS62131588A JP S62131588 A JPS62131588 A JP S62131588A JP 60271462 A JP60271462 A JP 60271462A JP 27146285 A JP27146285 A JP 27146285A JP S62131588 A JPS62131588 A JP S62131588A
Authority
JP
Japan
Prior art keywords
superconducting
mask
substrate
impurities
film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP60271462A
Other languages
Japanese (ja)
Inventor
Mutsuko Hatano
睦子 波多野
Osamu Okura
理 大倉
Juichi Nishino
西野 壽一
Ushio Kawabe
川辺 潮
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP60271462A priority Critical patent/JPS62131588A/en
Publication of JPS62131588A publication Critical patent/JPS62131588A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10NELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N60/00Superconducting devices
    • H10N60/10Junction-based devices
    • H10N60/128Junction-based devices having three or more electrodes, e.g. transistor-like structures

Abstract

PURPOSE:To improve the gain of a circuit and to implement high integration density, by providing a diffused layer, which has impurity concentration higher than that of a substrate, by an ion implantation, with an insulating film provided on a semiconductor layer as a mask, and a part, in which impurities are not diffused, between superconductive electrodes. CONSTITUTION:An SiO2 film 10 is formed on the surface of an Si substrate 1 with impurities. Then a resist pattern is formed on the surface. With the pattern as a mask, a protruded SiO2 part 10 is formed by plasma etching. Then with the SiO2 part as a mask, impurities are introduced from the surface by ion implantation, and a diffused layer 5 is formed. The surface of the Si substrate is etched, and a protruded part 9 is formed. After an insulating film 6 is formed, the insulating film 10 is removed. Then an Nb film is deposited. With this film as a mask, machining is performed by plasma etching and superconductive electrodes 2 and 3 are obtained. Thereafter, SiO2 insulating films 7 and 8 are formed. Then a control electrode 4 is formed. Thus, an element having a large circuit element can be obtained, dispersion in characteristics is reduced and the yield rate is improved.

Description

【発明の詳細な説明】 〔発明の利用分野〕 本発明は極低温で動作するスイッチングデバイスに係り
、特に回路の利得を大きくし特性のばらつきが小さい高
集積化に適した超伝導トランジスタの製造方法に関する
[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to switching devices that operate at extremely low temperatures, and in particular to a method for manufacturing a superconducting transistor that increases circuit gain and reduces variation in characteristics and is suitable for high integration. Regarding.

〔発明の背景〕[Background of the invention]

半導体を使用し素子の特性を制御するための電極を有す
る超伝導素子としては、ティー・ディー・クラーク(T
 、 D 、 C1ark)によって提案されたJOF
ET (ハイブリッド・ジョセフソン・フィールド・イ
フエクト・トランジスタ: Hybrid Josep
hsonField Effect Transist
ons)がジャープル・オブ・アプライド・フィジック
ス(J、^pp1.phys、) 2736ページ、第
51巻(1980)に報告されており公知である。JO
FETにおいては不純物を高濃度に導入した半導体基板
上に超電導体よりなる電極を形成する。この場合、素子
の制御は、制御電極に電圧を印加し、反転層を制御電極
側から半導体側へ拡げることによって行っている。
As a superconducting device that uses semiconductors and has electrodes for controlling the characteristics of the device, T.D. Clark (T.D.
, D, C1ark) proposed by JOF
ET (Hybrid Josephson Field Effect Transistor)
hsonField Effect Transist
ons) is reported in Journal of Applied Physics (J, ^pp1.phys, ), page 2736, volume 51 (1980), and is well known. J.O.
In an FET, an electrode made of a superconductor is formed on a semiconductor substrate into which impurities are introduced at a high concentration. In this case, the device is controlled by applying a voltage to the control electrode and expanding the inversion layer from the control electrode side to the semiconductor side.

このため、制御電極直下の半導体層の不純物濃度が高い
ために、制御電極に印加すべき電圧は数百ミリボルト以
上になる。−力出力としてリース・ドレイン電極間に得
られる電圧は数百ミリボルト以下と小さい。つまり回路
の利得は1以下となつてしまい、高利得化が期待できな
い。したがって従来の半導体技術において使用されてい
る回路と同様のものを使用することはできなかった。
Therefore, since the impurity concentration of the semiconductor layer directly under the control electrode is high, the voltage to be applied to the control electrode is several hundred millivolts or more. -The voltage obtained between the lease and drain electrodes as a force output is small, less than a few hundred millivolts. In other words, the gain of the circuit is less than 1, and high gain cannot be expected. Therefore, it was not possible to use circuits similar to those used in conventional semiconductor technology.

〔発明の目的〕[Purpose of the invention]

本発明の目的は、その特性が電圧で制御できるスイッチ
ングデバイスで、回路の利得を向上させ、高集積化が可
能でしかも作製工程E制御性がよく特性のばらつきが小
さい超伝導トランジスタを提供することにある。
An object of the present invention is to provide a superconducting transistor, which is a switching device whose characteristics can be controlled by voltage, which improves the gain of the circuit, enables high integration, has good controllability in the manufacturing process, and has small variations in characteristics. It is in.

〔発明の概要〕[Summary of the invention]

上記目的の中の回路の高利得化を達成するために、半導
体層の超伝導電極と接している部分にはショットキ障壁
を低減するため、基板より高い不純物濃度を導入し、そ
の間には低不純物濃度の部分を設ける。すなわち、半導
体層中に含まれる不純物の濃度分布に変化を持たせるこ
とによって前記目的を達成するものである。不純物を高
濃度にかつ均一に含有している場合に比べて、電荷の蓄
積あるいは反転の状態が異なり、制御電極に印加する電
圧は小さくなる。ここで超伝導電極間の距離は弱結合状
態に保つためにはコヒーレント長さの約10倍以下にす
る必要がある。その値は半導体や超伝導体の材料によっ
て異るがふつう数百nm程度である。従ってこの数百n
mの長さの半導体中の濃度分布に変化をもたせるのは難
かしい。
In order to achieve the high gain of the circuit in the above purpose, a higher impurity concentration than the substrate is introduced into the part of the semiconductor layer in contact with the superconducting electrode in order to reduce the Schottky barrier, and a low impurity Provide a concentration section. That is, the above object is achieved by varying the concentration distribution of impurities contained in the semiconductor layer. Compared to the case where impurities are uniformly contained at a high concentration, the state of charge accumulation or inversion is different, and the voltage applied to the control electrode becomes smaller. Here, the distance between the superconducting electrodes needs to be about 10 times or less the coherent length in order to maintain a weak coupling state. The value varies depending on the material of the semiconductor or superconductor, but it is usually on the order of several hundred nanometers. Therefore, this several hundred n
It is difficult to bring about a change in the concentration distribution in a semiconductor with a length of m.

そこで、不純物をイオン打込みした場合の横方向への拡
散層を利用し、半導体と超伝導電極が接している部分は
高濃度に、中央部は低濃度に形成したことに特徴がある
Therefore, by utilizing the lateral diffusion layer when impurity ions are implanted, the part where the semiconductor and superconducting electrode are in contact is formed with a high concentration, and the central part is formed with a low concentration.

〔発明の実施例〕[Embodiments of the invention]

以下、本発明の第1の実施例を第1.第2図により説明
する。
Hereinafter, the first embodiment of the present invention will be explained as follows. This will be explained with reference to FIG.

第1図は超伝導トランジスタの断面の一部を示す、Si
からなる半導体基板1の突起部9の両側にそれぞれ11
00nの不純物拡散層5が形成され、中央部は基板濃度
に保たれている。この突起部上部には厚さ50nmのS
 j、 Ozからなる絶縁膜7と厚さ1100nの5i
C)zからなる層間絶縁膜8を介して制御電極4が設置
されている。一方、突起部の両側には、厚さ1100n
のS i Ozからなる絶縁膜を介して厚さが突起部と
同程度でNbからなる超伝導電極2,3が形成されてい
る。
Figure 1 shows a part of the cross section of a superconducting transistor.
11 on both sides of the protrusion 9 of the semiconductor substrate 1 consisting of
00n impurity diffusion layer 5 is formed, and the central portion is kept at the substrate concentration. At the top of this protrusion, a 50 nm thick S
Insulating film 7 made of J, Oz and 5i with a thickness of 1100n
C) A control electrode 4 is installed via an interlayer insulating film 8 made of z. On the other hand, on both sides of the protrusion, the thickness is 1100n.
Superconducting electrodes 2 and 3 made of Nb and having the same thickness as the protrusion are formed through an insulating film made of SiOz.

次に第1図に示した超伝導トランジスタの製造工程と第
2図を用いて説明する。
Next, the manufacturing process of the superconducting transistor shown in FIG. 1 will be explained using FIG. 2.

不純物濃度I X 10 ”cm−”以下のホウ素を不
純物として含んだSi基板1の表面に、CVD法により
厚さ300nmの5iOz膜10を形成する(第2図(
a))−その後、表面に電子線描画装置を用いてレジス
トパターンを形成し、これをマスクとしてCF4ガスを
用いたプラズマエツチングによって幅300nmの突起
状の33. Ozを形成する(第2図(b))。続いて
この突起状の絶縁膜10をマスクとしてイオン打込みに
よって不純物濃度1×1019CIl−6のホウ素を表
面から導入する(第2図(c))、この場合打込まれた
深さは、400nm、マスク下への拡散の範囲5は11
00nであることが望ましい。次に、再び絶縁膜10を
マスクとしてCF4ガスを用いたプラズマエツチングに
よって、Si基板の表面をエツチングし、高さ400n
m、幅300nmの突起部9を形成した(第2図(d)
)。続いて、1200℃で水蒸気を含んだ酸素により1
2時間酸化して5iOzからなる厚さ1100nの絶縁
膜6を形成した後、マスクとして用いた絶縁膜10をC
F4ガスによるプラズマエツチングで除去する。(第2
図(C))。
A 5iOz film 10 with a thickness of 300 nm is formed by CVD on the surface of a Si substrate 1 containing boron as an impurity with an impurity concentration of I x 10 "cm-" or less (see Fig. 2).
a)) - Thereafter, a resist pattern is formed on the surface using an electron beam lithography system, and using this as a mask, plasma etching is performed using CF4 gas to form protruding 33. Oz is formed (Fig. 2(b)). Next, using this protruding insulating film 10 as a mask, boron with an impurity concentration of 1×10 19 CIl-6 is introduced from the surface by ion implantation (FIG. 2(c)). In this case, the implanted depth is 400 nm. The range of diffusion under the mask 5 is 11
It is desirable that it is 00n. Next, using the insulating film 10 as a mask, the surface of the Si substrate was etched by plasma etching using CF4 gas to a height of 400 nm.
m, and a protrusion 9 with a width of 300 nm was formed (Fig. 2(d)
). Subsequently, 1
After oxidizing for 2 hours to form an insulating film 6 made of 5iOz and having a thickness of 1100 nm, the insulating film 10 used as a mask was oxidized with carbon.
It is removed by plasma etching using F4 gas. (Second
Figure (C)).

次にNbをIX 10−’pa以下の高真空中で電子ビ
ーム加熱によって蒸着し、厚さ300nmのN t)膜
を堆積させ、このNb膜をホトレジストノ(ターンをマ
スクとしてCF4ガスによるプラズマエツチングによっ
て加工し超伝導電極2,3を得る(第21問(f))。
Next, Nb was evaporated by electron beam heating in a high vacuum of less than I to obtain superconducting electrodes 2 and 3 (Question 21 (f)).

突起部9と超伝導m極5,6はほぼ同一の高さに存在し
平坦化が実現できる。次に気相成長法によって厚さ50
nmの5iOzの絶縁膜7,8を形成した後、制御電極
4をNbのマグネトロンスパッタ法による製膜とプラズ
マエツチングによる加工によって形成し、本発明の超伝
導トランジスタは完成した(第2図(g)、(h))。
The protrusion 9 and the superconducting m-poles 5 and 6 are present at almost the same height, and flattening can be achieved. Next, a thickness of 50 mm was obtained using the vapor phase growth method.
After forming the insulating films 7 and 8 of 5iOz nm, the control electrode 4 was formed by forming a Nb film by magnetron sputtering and processing by plasma etching, and the superconducting transistor of the present invention was completed (see Fig. 2 (g). ), (h)).

この超伝導トランジスタを液体ヘリウム温度(4,2K
)に冷却して動作させたところ、超伝導電子の半導体中
のしみ出しが容易となり、制御電極に数mVの電圧を印
加することによって超伝導電極間と流れる超伝導電流を
大きく変化する利得の大きい素子を得ることができた。
This superconducting transistor is heated at liquid helium temperature (4.2K).
), superconducting electrons easily seep into the semiconductor, and by applying a voltage of several mV to the control electrode, the gain can be changed significantly between the superconducting electrodes and the superconducting current flowing. We were able to obtain a large element.

また不純物濃度の空間的な分布を精度よく実現できたの
で、特性のばらつきが小さく、歩留りが高い回路が得ら
れる効果がある。
Furthermore, since the spatial distribution of the impurity concentration can be realized with high accuracy, it is possible to obtain a circuit with small variations in characteristics and a high yield.

次に、本発明の第2の実施例を第3図により説明する。Next, a second embodiment of the present invention will be described with reference to FIG.

Siの半導体基板上に、絶縁物すを介して超伝導電極2
,3を300nmの距離をおいて並べて設置し、その間
にSiの半導体層5を形成し、その上部に厚さ50nm
の530zからなる絶縁物7を介して制御電極4を設置
した構造である。
A superconducting electrode 2 is placed on a Si semiconductor substrate via an insulator.
.
In this structure, the control electrode 4 is installed via an insulator 7 made of 530z.

半導体層5の幅1100nにわたる中央部分は不純物濃
度I X 10 ”am−’であり、その両側は不純物
濃度I X 10”cm−8で高濃度である。このよう
な不純物分布をもたせる製法は、第1の実施例に記載し
た方法により実現できる。つまり幅300nmの5iO
z膜を、マスクとしてホウ素をイオン打込みすればマス
ク下の横方向の拡散層を1100nに制御できた。この
ようにして距離300nm以下の超伝導電極2,3の間
の不純物分布を制御できる。
The central portion of the semiconductor layer 5 having a width of 1100n has an impurity concentration of I.times.10"am-", and both sides thereof have a high impurity concentration of I.times.10"cm-8. A manufacturing method that provides such an impurity distribution can be realized by the method described in the first embodiment. In other words, 5iO with a width of 300 nm
By implanting boron ions into the Z film as a mask, the lateral diffusion layer under the mask could be controlled to 1100 nm. In this way, the impurity distribution between the superconducting electrodes 2 and 3 with a distance of 300 nm or less can be controlled.

この超伝導トランジスタを液体ヘリウム温度(4,2K
)に冷却して動作させたところ回路利得の大きい素子を
得ることができた。
This superconducting transistor is heated at liquid helium temperature (4.2K).
), we were able to obtain a device with a large circuit gain.

さらにこれを用いて集積回路を構成したところ、不純物
濃度分布を精度よく制御できたので特性のばらつきが小
さく歩留りが高い回路が実現できた。
Furthermore, when an integrated circuit was constructed using this, the impurity concentration distribution could be controlled with high accuracy, resulting in a circuit with small variations in characteristics and high yield.

次に、本発明筒3の実施例を第4図により説明する。超
伝導電極2,3と層間絶縁膜6を交互に積層し、その端
部に半導体5と絶縁物7を介して制御電極4が設置され
ている。半導体中の不純物濃度は、超伝導電極2,3の
間の1100nにわたっては低く (L X 10 ”
cm”’δ)、半導体と超伝導体が接する部分は高い(
I X 1019cm−’)。
Next, an embodiment of the tube 3 of the present invention will be described with reference to FIG. Superconducting electrodes 2 and 3 and interlayer insulating films 6 are alternately stacked, and a control electrode 4 is installed at the end of the superconducting electrodes 2 and 3 with a semiconductor 5 and an insulator 7 interposed therebetween. The impurity concentration in the semiconductor is low over 1100n between the superconducting electrodes 2 and 3 (L x 10 ”
cm”'δ), the area where the semiconductor and superconductor are in contact is high (
I x 1019 cm-').

このような濃度分布をもたせる製法は、第1の実施例に
記載した方法により実現できる。つまり幅300nmの
S i Ox、膜をマスクとしてホウ素を斜の方向にイ
オン打込みすれば幅1100n程度の低濃度領域を残す
ことができる。
A manufacturing method that provides such a concentration distribution can be realized by the method described in the first example. In other words, by implanting boron ions in an oblique direction using a SiOx film with a width of 300 nm as a mask, a low concentration region with a width of about 1100 nm can be left.

この超伝導トランジスタを液体ヘリウム温度(4,2K
)に冷却して動作させたところ、回路利得の大きい素子
を得ることができた。
This superconducting transistor is heated at liquid helium temperature (4.2K).
), we were able to obtain a device with large circuit gain.

さらに集積回路を構成したところ、不純物濃度の分布を
精度よく制御できたので特性のばらつきが小さく歩留り
が高い回路が実現できた。
Furthermore, when we constructed an integrated circuit, we were able to control the distribution of impurity concentrations with high precision, making it possible to create a circuit with small variations in characteristics and high yield.

本実施例では半導体材料にSiを用いたが、これに代え
てGaAs、InP、InSb、InAs等の材料を用
いてもよい、超伝導材料としてはNbを用いたが、これ
に代えてpb、pb金合金NbN。
In this example, Si was used as the semiconductor material, but materials such as GaAs, InP, InSb, and InAs may be used instead. Nb was used as the superconducting material, but instead of this, pb, pb gold alloy NbN.

MoN、NbaSj等を用いてもよい。また不純物とし
てホウ素に代えてリンヒ素、アンチモン等を用いてもよ
い。
MoN, NbaSj, etc. may also be used. Moreover, phosphorus arsenic, antimony, etc. may be used instead of boron as an impurity.

〔発明の効果〕〔Effect of the invention〕

本発明によれば超伝導電極に接する半導体層中の不純物
濃度分布を微小部分を空間的に精度よく作成でき再現性
よく制御できる。このため印加電圧で超電導電極間の結
合状態を制御する際の利得を大きくすることができる構
造を実現でき、特性のばらつきが小さく高い歩留りにな
るという効果がある。
According to the present invention, the impurity concentration distribution in the semiconductor layer in contact with the superconducting electrode can be created in minute portions with spatial precision and controlled with good reproducibility. Therefore, it is possible to realize a structure that can increase the gain when controlling the coupling state between the superconducting electrodes using an applied voltage, and has the effect of reducing variation in characteristics and achieving a high yield.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の第1の実施例による超伝導トランジス
タの一部を示す断面図、第2図は本発明の第1の実施例
による超伝導トランジスタの製造工程を示す断面図、第
3図は本発明筒2の実施例による超伝導トランジスタの
一部を示す断面図、第4図は本発明筒3の実施例による
超伝導トランジスタの一部を示す断面図である。
FIG. 1 is a sectional view showing a part of a superconducting transistor according to a first embodiment of the present invention, FIG. 2 is a sectional view showing a manufacturing process of a superconducting transistor according to a first embodiment of the present invention, and FIG. The figure is a sectional view showing a part of a superconducting transistor according to an embodiment of the tube 2 of the present invention, and FIG. 4 is a sectional view showing a part of a superconducting transistor according to an embodiment of the tube 3 of the present invention.

Claims (1)

【特許請求の範囲】 1、一対の超伝導電極と少くとも両超伝導電極に接続し
て延在する半導体層と制御電極とを少くとも有する超伝
導トランジスタにおいて、該半導体層は該半導体層上に
設けた絶縁膜をマスクとしたイオン打込法によつて基板
より高い不純物濃度を有する拡散層と、前記超伝導電極
間に不純物を拡散しない部分を設けたことを特徴とする
超伝導トランジスタの製法。 2、特許請求の範囲第1項記載の不純物を拡散しない部
分の長さは、300nm以下であることを特徴とする超
伝導トランジスタの製法。
[Claims] 1. In a superconducting transistor having at least a pair of superconducting electrodes, a semiconductor layer connected to and extending to both superconducting electrodes, and a control electrode, the semiconductor layer is formed on the semiconductor layer. A superconducting transistor characterized in that a region in which impurities are not diffused is provided between a diffusion layer having a higher impurity concentration than the substrate and the superconducting electrode by ion implantation using an insulating film provided on the substrate as a mask. Manufacturing method. 2. A method for manufacturing a superconducting transistor, characterized in that the length of the portion in which impurities are not diffused as set forth in claim 1 is 300 nm or less.
JP60271462A 1985-12-04 1985-12-04 Manufacture of superconductive transistor Pending JPS62131588A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60271462A JPS62131588A (en) 1985-12-04 1985-12-04 Manufacture of superconductive transistor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60271462A JPS62131588A (en) 1985-12-04 1985-12-04 Manufacture of superconductive transistor

Publications (1)

Publication Number Publication Date
JPS62131588A true JPS62131588A (en) 1987-06-13

Family

ID=17500370

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60271462A Pending JPS62131588A (en) 1985-12-04 1985-12-04 Manufacture of superconductive transistor

Country Status (1)

Country Link
JP (1) JPS62131588A (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03296284A (en) * 1990-04-16 1991-12-26 Nec Corp Superconductive element and manufacture thereof
EP0487922A2 (en) * 1990-11-30 1992-06-03 Sony Corporation High speed switching electron device
US5317168A (en) * 1988-02-05 1994-05-31 Hitachi, Ltd. Superconducting field effect transistor
US5388068A (en) * 1990-05-02 1995-02-07 Microelectronics & Computer Technology Corp. Superconductor-semiconductor hybrid memory circuits with superconducting three-terminal switching devices
JP2005294782A (en) * 2004-03-31 2005-10-20 Takeshi Awaji Semiconductor superconductivity element
CN111969102A (en) * 2020-09-11 2020-11-20 中国科学院紫金山天文台 Preparation method for improving superconducting titanium-niobium film contact electrode

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5317168A (en) * 1988-02-05 1994-05-31 Hitachi, Ltd. Superconducting field effect transistor
JPH03296284A (en) * 1990-04-16 1991-12-26 Nec Corp Superconductive element and manufacture thereof
JP2616130B2 (en) * 1990-04-16 1997-06-04 日本電気株式会社 Superconducting element manufacturing method
US5388068A (en) * 1990-05-02 1995-02-07 Microelectronics & Computer Technology Corp. Superconductor-semiconductor hybrid memory circuits with superconducting three-terminal switching devices
EP0487922A2 (en) * 1990-11-30 1992-06-03 Sony Corporation High speed switching electron device
JP2005294782A (en) * 2004-03-31 2005-10-20 Takeshi Awaji Semiconductor superconductivity element
CN111969102A (en) * 2020-09-11 2020-11-20 中国科学院紫金山天文台 Preparation method for improving superconducting titanium-niobium film contact electrode
CN111969102B (en) * 2020-09-11 2023-10-27 中国科学院紫金山天文台 Preparation method for improving superconducting titanium-niobium film contact electrode

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