JPS6257260A - Superconducting transistor - Google Patents
Superconducting transistorInfo
- Publication number
- JPS6257260A JPS6257260A JP60195822A JP19582285A JPS6257260A JP S6257260 A JPS6257260 A JP S6257260A JP 60195822 A JP60195822 A JP 60195822A JP 19582285 A JP19582285 A JP 19582285A JP S6257260 A JPS6257260 A JP S6257260A
- Authority
- JP
- Japan
- Prior art keywords
- superconducting
- semiconductor
- control electrode
- thick
- transistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N60/00—Superconducting devices
- H10N60/10—Junction-based devices
- H10N60/128—Junction-based devices having three or more electrodes, e.g. transistor-like structures
Landscapes
- Superconductor Devices And Manufacturing Methods Thereof (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の利用分野〕
本発明は極低温で動作する超電導デバイスに係り、特に
半導体中をトンネルする超電導電子の数を制御電圧に印
加する電圧によって制御する超電導デバイスに関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a superconducting device that operates at extremely low temperatures, and particularly to a superconducting device in which the number of superconducting electrons tunneling through a semiconductor is controlled by a voltage applied to a control voltage.
従来の超電導体と半導体を組合わせた超電導デバイスは
特開57−016186号に記載のように第1図に示す
構造となっていた。A conventional superconducting device combining a superconductor and a semiconductor has a structure shown in FIG. 1, as described in Japanese Patent Laid-Open No. 57-016186.
これは一対の超電導電極1,2を対向させた間に制御電
極4を設けたtIII造である。This is a tIII structure in which a control electrode 4 is provided between a pair of superconducting electrodes 1 and 2 facing each other.
極低温においてこのディスの2つの超電導体が半導体を
介した超電導弱結合状態撃つくるには、2つの超電導体
間の距離を超電導体の電子対のコヒーレント長さの10
倍程度、すなわち0.2μm以下に接近させる必要があ
る。この従来技術においては、はじめに2つの超電導電
極を一体化して形成しておき、ホトリソグラフィとエツ
チングにより2つの超電導電極1,2に分離する。続い
てその分離した部分を熱酸化して復縁膜5を形成し、蒸
着により制御電極4を設置する工程である。この方法に
よると超電導電極1,2の間隔は0.2μm以下と狭い
ためこの部分に絶縁物5及び制御電極4を形成すること
は困難である。また形成できたとしても加工の寸法精度
を高くすることはできないという欠点があった。In order for the two superconductors of this disk to achieve a superconducting weak coupling state through the semiconductor at extremely low temperatures, the distance between the two superconductors must be 10 times the coherence length of the electron pairs in the superconductors.
It is necessary to approach the distance by about twice as much, that is, by 0.2 μm or less. In this prior art, two superconducting electrodes are first formed integrally and then separated into two superconducting electrodes 1 and 2 by photolithography and etching. Subsequently, the separated portion is thermally oxidized to form a reinforcing film 5, and the control electrode 4 is installed by vapor deposition. According to this method, since the distance between the superconducting electrodes 1 and 2 is as narrow as 0.2 μm or less, it is difficult to form the insulator 5 and the control electrode 4 in this area. Further, even if it could be formed, there was a drawback that the dimensional accuracy of processing could not be improved.
本発明の目的は、半導体と超電導体とを組合わせた極低
温で動作する超電導トランジスタにおいて、加工精度を
高め、これによってデバイスの特性の均一性、再現性な
らびに利得を向−1−させることのできる超電導トラン
ジスタの構造と製造法を提供することにある。The purpose of the present invention is to improve the processing accuracy of a superconducting transistor that combines a semiconductor and a superconductor and operates at extremely low temperatures, thereby improving the uniformity, reproducibility, and gain of device characteristics. The purpose of this invention is to provide a structure and manufacturing method for a superconducting transistor that can be manufactured.
本発明はこの目的を達成するために、半導体の上下に設
置した第1及び第2の超電導電極と、該半導体と絶縁膜
によって隔てられた第3のゲート電極を有し、第1及び
第2の電極の超電導弱結合状態を第3の電極に印加する
電圧で制御することを特徴とする。超電導体と半導体が
接した部分では、超電導体側のオーダパラメータが半導
体側に染みだしており、その空間的な距離は、半導体中
の電子対のコヒーレント長さξ。によって表わされる。In order to achieve this object, the present invention has first and second superconducting electrodes installed above and below a semiconductor, and a third gate electrode separated from the semiconductor by an insulating film. The superconducting weak coupling state of the electrodes is controlled by the voltage applied to the third electrode. At the point where the superconductor and semiconductor are in contact, the order parameters of the superconductor leak into the semiconductor, and the spatial distance is the coherence length ξ of the electron pairs in the semiconductor. is expressed by
第1及び第2の超電導電極の空間的な距離りがコヒーレ
ント長さの10倍以下の場合、超電導弱結合態となり得
る。■、の距離は、本発明の超電導トランジスタの場合
には超電導体間にある半導体の厚さによって決まる。一
方ξ、の値は温度T及び半導体中のキャリア濃度N、半
導体と超電導体の種類によって変化し、Nが大きいほど
ξ。も大きくなる。よってξ、と■、の比0.7丁、の
値が大きい程、超電導体間の結合は強くなる。したがっ
て制御電極に印加することによって電荷を半導体中に蓄
積して制御することができる。When the spatial distance between the first and second superconducting electrodes is 10 times or less the coherent length, a weakly coupled superconducting state can be achieved. In the case of the superconducting transistor of the present invention, the distance (2) is determined by the thickness of the semiconductor between the superconductors. On the other hand, the value of ξ changes depending on the temperature T, the carrier concentration N in the semiconductor, and the type of semiconductor and superconductor, and the larger N is, the larger ξ is. also becomes larger. Therefore, the larger the value of the ratio of ξ and ■, which is 0.7, the stronger the coupling between the superconductors. Therefore, by applying an electric charge to the control electrode, electric charge can be accumulated and controlled in the semiconductor.
ここでI、の値はトランジスタがONの時に■、/ξ、
の比が10以下になっているように設計されている必要
がある。チャネルにSj半導体を用いた場合■、の値は
0.1〜0.2μmの範囲に選ばれろことが望ましい。Here, the value of I, when the transistor is ON, is ■, /ξ,
The design must be such that the ratio is 10 or less. When an Sj semiconductor is used for the channel, it is desirable that the value of (1) be selected in the range of 0.1 to 0.2 μm.
本発明の超電導トランジスタは丁、の値は半導体の厚さ
によって決まるので、均一性に制御することけ容易であ
って製造の際のトランジスタ特性の再現性、均一性が極
めて優れている。またこの構造による超電導トランジス
タを用いると複数個直列接続して出力振幅を大きくする
複合デバイスを構成できる。In the superconducting transistor of the present invention, since the value of D is determined by the thickness of the semiconductor, it is easy to control uniformity, and the reproducibility and uniformity of transistor characteristics during manufacture are extremely excellent. Further, by using superconducting transistors with this structure, a composite device can be constructed by connecting a plurality of transistors in series to increase the output amplitude.
以下、実施例を用いて本発明の詳細な説明する。 Hereinafter, the present invention will be explained in detail using Examples.
第2図は本発明の第1の実施例による超電導トランジス
タの断面図である。半導体3の上と下に第1と第2の超
電導電極1..2を積層しその側壁部に絶縁膜5によっ
て隔てられた第3の制御電極4が設置されている。FIG. 2 is a sectional view of a superconducting transistor according to a first embodiment of the present invention. First and second superconducting electrodes 1. above and below the semiconductor 3. .. A third control electrode 4 is provided on the side wall of the control electrode 2, which is separated by an insulating film 5.
第1、第2の電極の超電導弱結合状態を第3の電極に印
加する電圧で制御する電界効果トランジスタを構成して
いる。超電導弱結合状態が制御できれば流れる超電導電
流を変化されることができる。A field effect transistor is configured in which a superconducting weak coupling state between the first and second electrodes is controlled by a voltage applied to the third electrode. If the superconducting weak coupling state can be controlled, the flowing superconducting current can be changed.
次に、この超電導1−ランジスタの製造方法を説明する
(第3図)。基板8の上に厚さ300’n mのNb薄
膜2をDCマグネトロンスパッタ法によって堆積させた
表面−ににただちに気相成長法あるいは分子線成長法に
よって厚さ200nmのSiよりなるチャネル層3を形
成し、さらにイオン打込み法により不純物Bを1025
(2)−3導入した。再び厚さ300nmのNb@膜1
を堆積して積層構造を形成する。これをホト1ノジスト
をマスクとしたイオンエツチング法によって所望形状に
加工しく5)
た後に側壁部の表面を1000℃酸素雰囲気中で10分
熱酸化し、約20nmの絶縁物5を得た。最後にNbを
DCマグネトロンスパッタ法により約800nm堆積さ
せた。この後CF4ガスによる反応性イオンエツチング
によってこれを加工して熱酸化膜より右側幅2μmのN
bを残すことにより第3の電極4を得る。以上によって
第2図に示した本実施例の超電導トランジスタを作製す
ることができた。Next, a method of manufacturing this superconducting transistor will be explained (FIG. 3). Immediately on the surface of the Nb thin film 2 with a thickness of 300'nm deposited on the substrate 8 by the DC magnetron sputtering method, a channel layer 3 made of Si with a thickness of 200nm is formed by vapor phase epitaxy or molecular beam epitaxy. Then, impurity B is added to 1025 by ion implantation method.
(2)-3 was introduced. Again 300 nm thick Nb@film 1
is deposited to form a laminated structure. This was processed into a desired shape by an ion etching method using photonodist as a mask (5), and then the surface of the side wall portion was thermally oxidized for 10 minutes in an oxygen atmosphere at 1000° C. to obtain an insulator 5 with a thickness of about 20 nm. Finally, Nb was deposited to a thickness of about 800 nm by DC magnetron sputtering. After that, this was processed by reactive ion etching using CF4 gas to form a 2 μm wide N film on the right side of the thermal oxide film.
The third electrode 4 is obtained by leaving b. Through the above steps, the superconducting transistor of this example shown in FIG. 2 could be manufactured.
本実施例によれば超電導電極間の距離を決るために半導
体の厚さを用いているので精度よく制御することができ
、トランジスタ特性のばらつきを抑えることができ、製
造時の歩留りを向上させることができる。また層間絶縁
膜が必要とならないので作製工程が容易になるなどの効
果もある。According to this embodiment, since the thickness of the semiconductor is used to determine the distance between the superconducting electrodes, it can be controlled accurately, suppressing variations in transistor characteristics, and improving yield during manufacturing. I can do it. Further, since an interlayer insulating film is not required, the manufacturing process becomes easier.
第4図は本発明筒2の実施例による超電導トランジスタ
の断面図である。超電導電極2を共通として2つのトラ
ンジスタが、1つの制御電極4に対して直列に接続され
た構造をしている。第6図には、このデバイスの作製]
;程を示す。FIG. 4 is a sectional view of a superconducting transistor according to an embodiment of the tube 2 of the present invention. It has a structure in which two transistors are connected in series to one control electrode 4 using a superconducting electrode 2 in common. Figure 6 shows the fabrication of this device]
; indicates the degree.
第1の実施例で示したごと(Nb薄膜2.Si半導体3
とNb薄膜1を積層する(第6図(a))。As shown in the first embodiment (Nb thin film 2. Si semiconductor 3
and Nb thin film 1 are laminated (FIG. 6(a)).
その後ホトレジストをマスクとしたイオンエツチング法
によって、Nb薄膜1.半導体3を2つに分離する。そ
の後この溝の表面を熱酸化して絶縁物5を形成しく第6
図(b))、その上にNbよりなる500nmの厚さの
Nbを堆積させ制御電極4を設置した(第6図(C))
。Thereafter, the Nb thin film 1. Separate the semiconductor 3 into two. After that, the surface of this groove is thermally oxidized to form an insulator 5.
(Fig. 6(b)), on which Nb with a thickness of 500 nm was deposited and the control electrode 4 was installed (Fig. 6(C)).
.
以」―によって第4図に示した本実施例の超電導トラン
ジスタを作製することができた。本実施例によれば容易
に2つの超電導トランジスタを直列に接続できるため、
一定の製御電圧に対する出力振幅を2倍にすることがで
き、回路利得を高めることができる。また電極の端子を
同一面側からとり出すことができる。一方、作製の工程
数は2倍にならず一度に超電導電極、チャネル層を形成
できるので高集積化が容易であるなどの効果がある。The superconducting transistor of this example shown in FIG. 4 could be manufactured by the following steps. According to this embodiment, two superconducting transistors can be easily connected in series, so
The output amplitude for a constant control voltage can be doubled, and the circuit gain can be increased. Further, the terminals of the electrodes can be taken out from the same side. On the other hand, since the superconducting electrode and channel layer can be formed at once without doubling the number of manufacturing steps, there are advantages such as ease of high integration.
第5図は本発明の第3の実施例による超電導トランジス
タの断面図である。第2の実施例による超電導トランジ
スタをさらに複数個接続し、素子間をKOH液で液で化
学エツチングして穴を開け、その部分に蒸着によりSi
Oを埋め込み分離層6を形成した。本実施例によれば、
制御電極4に印加する一定の入力に対する出力振幅を大
きくでき、回路利得を高めることができる。また作製、
高朶積化が容易であるなどの効果がある。FIG. 5 is a sectional view of a superconducting transistor according to a third embodiment of the present invention. A plurality of superconducting transistors according to the second embodiment are further connected, holes are formed between the elements by chemical etching with a KOH solution, and Si is deposited on the holes by vapor deposition.
A separation layer 6 was formed by burying O. According to this embodiment,
The output amplitude for a constant input applied to the control electrode 4 can be increased, and the circuit gain can be increased. Also made,
It has the advantage of being easy to increase the volume.
以−L示した3つの実施例においては第1.第2゜第3
の電極材料にはNbを用いたが、NbN。In the three embodiments shown below, the first. 2nd゜3rd
Nb was used as the electrode material, but NbN.
Nb3Ge、Nb3Sn、NbaAI2 等のNb化合
物、あるいはPb−Au、Pb−In−An。Nb compounds such as Nb3Ge, Nb3Sn, NbaAI2, or Pb-Au, Pb-In-An.
Pb−B1等のpb金合金用いた場合でも同様の効果を
得ることができる。また第3の電極の材料には、AQ、
不純物を高濃度に含んだ多結晶Si、単結晶Siを用い
ても本発明の目的を達成することができた。Similar effects can be obtained even when a pb gold alloy such as Pb-B1 is used. In addition, the material of the third electrode includes AQ,
The object of the present invention could be achieved even by using polycrystalline Si or single crystalline Si containing impurities at a high concentration.
また半導体にはS i、 tit結晶の他に多結晶Sj
。In addition to Si and tit crystals, polycrystalline Sj
.
アモルファスS i、 Ge、 GaAsのInAs
、 I n P 。Amorphous Si, Ge, InAs of GaAs
, I n P .
TnSb等を用いてもよい。TnSb or the like may also be used.
また絶縁膜5の材料としてはS i O,S i、N4
を使用しても同様の効果を得ることができた。なお、半
導体の不純物濃度は極低温中で動作させるために10”
m−’以−りであることが望ましい。In addition, the materials of the insulating film 5 include SiO, Si, N4
A similar effect could be obtained using . Note that the impurity concentration of the semiconductor is 10" in order to operate at extremely low temperatures.
It is desirable that the value is m-' or more.
不純物としては、P、R,AS、Sb等の中から選ばれ
る。The impurity is selected from P, R, AS, Sb, etc.
〔発明の効果〕
本発明によれば、電圧によって制御できる超電導トラン
ジスタを実現し、再現性、均一性よく製造することがで
きる。また本発明の超電導トランジスタは容易に直列接
続でき、微小な寸法を制御することができるため、高速
かつ高集積の超電導集積回路が実現できる効果がある。[Effects of the Invention] According to the present invention, a superconducting transistor that can be controlled by voltage can be realized and manufactured with good reproducibility and uniformity. Furthermore, since the superconducting transistor of the present invention can be easily connected in series and its minute dimensions can be controlled, it has the effect of realizing a high-speed, highly integrated superconducting integrated circuit.
第1図は従来の超電導トランジスタを示す断面図、第2
図、第3図は、本発明筒1の実施例による超電導トラン
ジスタの断面図、第4図は第2の実施例による超電導ト
ランジスタの断面図、第5図は第3の実施例による超電
導トランジスタの断面図、第6図(a)〜(c)は第2
の実施例による超電導トランジスタの製造工程を示す断
面図である。
1.2・・・超電導電極、3・・・半導体、4・・・制
御電極、5・・・絶縁膜、6,7・・・絶縁層、8・・
・基板。Figure 1 is a sectional view showing a conventional superconducting transistor, Figure 2 is a cross-sectional view showing a conventional superconducting transistor.
3 is a sectional view of a superconducting transistor according to an embodiment of the tube 1 of the present invention, FIG. 4 is a sectional view of a superconducting transistor according to a second embodiment, and FIG. 5 is a sectional view of a superconducting transistor according to a third embodiment. Cross-sectional views, Figures 6 (a) to (c) are the second
FIG. 3 is a cross-sectional view showing the manufacturing process of a superconducting transistor according to an embodiment of the present invention. 1.2... Superconducting electrode, 3... Semiconductor, 4... Control electrode, 5... Insulating film, 6, 7... Insulating layer, 8...
·substrate.
Claims (1)
超電導体よりなる電極を積層して、その端部に絶縁膜と
制御電極を設けた構造を有することを特徴とする超電導
トランジスタ。 2、特許請求範囲第1項に記載の超電導トランジタにお
いて、半導体の厚さは0.1〜0.2μm範囲に選ばれ
たことを特徴とする超電導トランジスタ。[Claims] 1. It has a structure in which an electrode made of a first superconductor, an electrode made of a semiconductor, and a second superconductor are stacked, and an insulating film and a control electrode are provided at the ends thereof. superconducting transistor. 2. A superconducting transistor according to claim 1, wherein the thickness of the semiconductor is selected to be in the range of 0.1 to 0.2 μm.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP60195822A JPS6257260A (en) | 1985-09-06 | 1985-09-06 | Superconducting transistor |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP60195822A JPS6257260A (en) | 1985-09-06 | 1985-09-06 | Superconducting transistor |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6257260A true JPS6257260A (en) | 1987-03-12 |
Family
ID=16347574
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP60195822A Pending JPS6257260A (en) | 1985-09-06 | 1985-09-06 | Superconducting transistor |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6257260A (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0487922A2 (en) * | 1990-11-30 | 1992-06-03 | Sony Corporation | High speed switching electron device |
US5126315A (en) * | 1987-02-27 | 1992-06-30 | Hitachi, Ltd. | High tc superconducting device with weak link between two superconducting electrodes |
US5179426A (en) * | 1987-08-04 | 1993-01-12 | Seiko Epson Corporation | Josephson device |
-
1985
- 1985-09-06 JP JP60195822A patent/JPS6257260A/en active Pending
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5126315A (en) * | 1987-02-27 | 1992-06-30 | Hitachi, Ltd. | High tc superconducting device with weak link between two superconducting electrodes |
US5552375A (en) * | 1987-02-27 | 1996-09-03 | Hitachi, Ltd. | Method for forming high Tc superconducting devices |
US5179426A (en) * | 1987-08-04 | 1993-01-12 | Seiko Epson Corporation | Josephson device |
EP0487922A2 (en) * | 1990-11-30 | 1992-06-03 | Sony Corporation | High speed switching electron device |
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