JPS61206277A - Superconductive transistor - Google Patents
Superconductive transistorInfo
- Publication number
- JPS61206277A JPS61206277A JP60046539A JP4653985A JPS61206277A JP S61206277 A JPS61206277 A JP S61206277A JP 60046539 A JP60046539 A JP 60046539A JP 4653985 A JP4653985 A JP 4653985A JP S61206277 A JPS61206277 A JP S61206277A
- Authority
- JP
- Japan
- Prior art keywords
- control electrode
- superconducting
- substrate
- projecting section
- electrodes
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N60/00—Superconducting devices
- H10N60/10—Junction-based devices
- H10N60/128—Junction-based devices having three or more electrodes, e.g. transistor-like structures
Abstract
Description
【発明の詳細な説明】
〔発明の利用分野〕
本発明は、極低温で動作する超電導デバイスに係り、特
に半導体と、超電導体とを組み合わせ。DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a superconducting device that operates at extremely low temperatures, and particularly to a combination of a semiconductor and a superconductor.
制御電極を有する電界効果型の超電導トランジスタに関
する。The present invention relates to a field-effect superconducting transistor having a control electrode.
半導体と2つの超電導体を組合わせた超電導デバイスは
、半導体に縮退したSi単結晶を用いた例 、 、
“、
あるいは半導体に
p型のGaAsを使用した例 4が知
ら
れている。これらの例では超電導体にはpbが用いられ
ており、その加工には、ホトレジストをマスクにしたエ
ツチング法が使用されている。極低温においてこのデバ
イスの2つの超電導体が半導体を介した超電導弱結合を
形成するためには、2つの超電導電極間の距離を超電導
体の電子対のコヒーレント長さの10倍程度、すなわち
約0.5μm以下に接近させる必要がある。第1図に特
開昭57−106186号に開示されている従来の超電
導トランジスタの構造を示す。この構造においては、ま
ず2つの超電導電極2,3を一体化して形成しておき、
次いでホトレジストあるいは電子線レジストをマスクに
したエツチングによって加工し、接近した2つの超電導
電極2と3を形成している。A superconducting device that combines a semiconductor and two superconductors is an example of using a degenerate Si single crystal as a semiconductor.
“,
Alternatively, Example 4 is known in which p-type GaAs is used as the semiconductor. In these examples, PB is used as the superconductor, and an etching method using a photoresist as a mask is used for processing. In order for the two superconductors of this device to form a superconducting weak coupling via the semiconductor at extremely low temperatures, the distance between the two superconducting electrodes must be approximately 10 times the coherent length of the electron pairs in the superconductor, or approximately 0. It is necessary to bring the distance closer to .5 μm or less. FIG. 1 shows the structure of a conventional superconducting transistor disclosed in Japanese Patent Application Laid-Open No. 57-106186. In this structure, first, two superconducting electrodes 2 and 3 are formed integrally,
Next, etching is performed using photoresist or electron beam resist as a mask to form two superconducting electrodes 2 and 3 that are close to each other.
続いて熱酸化膜6を約80nm・形成した後、該超電導
電極2,3の間に、制御電極5を形成している。しかし
、第1図に示した才従来の構造においては、0.5 μ
m以下のせまいところに、制御電極を形成することは容
易では無く、このため、加工の寸法精度が高くならず、
信頼性、均一性を得るのが困難であった。Subsequently, a thermal oxide film 6 of about 80 nm is formed, and then a control electrode 5 is formed between the superconducting electrodes 2 and 3. However, in the conventional structure shown in Figure 1, 0.5 μ
It is not easy to form a control electrode in a narrow space of less than m, and for this reason, the dimensional accuracy of processing is not high.
It was difficult to obtain reliability and uniformity.
本発明の目的は、半導体と超電導体を組み合わせた極低
温で動作するトランジスタ型の素子において、超電導体
の加工精度を高め、素子特性の信頼性、均一性を向上さ
せた超電導トランジスタを提供することにある。An object of the present invention is to provide a superconducting transistor in which the processing accuracy of the superconductor is improved and the reliability and uniformity of the device characteristics are improved in a transistor-type element that combines a semiconductor and a superconductor and operates at extremely low temperatures. It is in.
本発明は、上記目的を達成するために、従来のエツチン
グによる超電導電極に代えて、半導体の基板側にエツチ
ングによって突起部を形成し、この突起部に、絶縁物層
を介して制御電極を設けた点に特徴がある。この構造に
よれば、半導体の基板の加工精度によって、2つの超電
導体相互の空間的な距離が決まる。したがって、デバイ
スの特性の均一性を高くし、製造時の歩留まりを高くす
ることが可能になる。また、制御電極の側面を絶縁する
ことにより、制御電極と超電導電極の間は完全に絶縁さ
れ、よりデバイス特性の均一性、信頼性を向上すること
が可能となる。In order to achieve the above object, the present invention forms protrusions by etching on the semiconductor substrate side, in place of conventional etched superconducting electrodes, and provides control electrodes on these protrusions via an insulating layer. It is characterized by the fact that According to this structure, the spatial distance between the two superconductors is determined by the processing precision of the semiconductor substrate. Therefore, it is possible to improve the uniformity of device characteristics and increase the yield during manufacturing. Furthermore, by insulating the side surfaces of the control electrode, the control electrode and the superconducting electrode are completely insulated, making it possible to further improve the uniformity and reliability of device characteristics.
以下、本発明の一実施例を第2図、第3図を用いて説明
する。An embodiment of the present invention will be described below with reference to FIGS. 2 and 3.
第2図は、本発明の超電導トランジスタ構造の断面図で
ある。半導体の基板1の一部に突起部4があり、この突
起部の両側に対向する一対の超電導電極2,3を形成し
ている。突起部4の上には、側面が絶縁された制御電極
5を絶縁物層6を介して設けている。FIG. 2 is a cross-sectional view of the superconducting transistor structure of the present invention. A portion of a semiconductor substrate 1 has a protrusion 4, and a pair of superconducting electrodes 2 and 3 facing each other are formed on both sides of the protrusion. A control electrode 5 whose side surfaces are insulated is provided on the protrusion 4 with an insulator layer 6 interposed therebetween.
このデバイスの作製工程を第3図により説明する。Si
単結晶基板1を、1200℃で水蒸気を含んだ酸素によ
り1時間酸化することにより基板表面に厚さ80nmの
Sin、よりなる絶縁物層6を形成する。次いで、多結
晶Siよりなる厚さ0.3μmの制御電極5を高真空容
器中にて電子ビーム蒸着によって形成した後電子ビーム
レジストをマスクとして、CF4ガスによるプラズマエ
ツチングによって基板1の一部までエツチングする。続
いて、pbよりなる厚さ300nmの超電導電極2.3
を抵抗加熱蒸着法およびリフトオフ法を用いて形成した
後、制御電極5の側面を熱酸化して絶縁物層5を形成し
た。The manufacturing process of this device will be explained with reference to FIG. Si
A single crystal substrate 1 is oxidized with oxygen containing water vapor at 1200° C. for 1 hour to form an 80 nm thick insulating layer 6 made of Sin on the substrate surface. Next, a control electrode 5 made of polycrystalline Si with a thickness of 0.3 μm is formed by electron beam evaporation in a high vacuum container, and then a part of the substrate 1 is etched by plasma etching with CF4 gas using the electron beam resist as a mask. do. Next, a superconducting electrode 2.3 with a thickness of 300 nm made of pb
was formed using a resistance heating evaporation method and a lift-off method, and then the side surface of the control electrode 5 was thermally oxidized to form an insulating layer 5.
絶縁物層6,7の材料としては、Sin、の他にS i
O,Si、N、、 AM、O,等の中から選んで使用
することができる。半導体材料としては、P、B。In addition to Sin, the material of the insulator layers 6 and 7 is Si
It can be selected from among O, Si, N, AM, O, etc. Semiconductor materials include P and B.
As等の不純物を10”a++−’以上含んだSiまた
はG e 、あるいは10”cm−”以上のSi、Zn
。Si or Ge containing impurities such as As at 10"a++-' or more, or Si, Zn containing 10"cm-" or more
.
Geを不純物として含んだGaAs、 InAs、 I
n P等を用いてもよい、ま゛た制御電極4の材料と
して。GaAs, InAs, I containing Ge as an impurity
nP or the like may also be used as the material for the control electrode 4.
T i 、 W、 Mo、 Po1y−5i+ AQ、
Cu、 P を等を用いてもよい。T i, W, Mo, Po1y-5i+ AQ,
Cu, P, etc. may also be used.
超電導電極2,3の材料として、pb及びpbを主成分
とした合金、Nb、Nb化合物等を用いてもよい。As the material for the superconducting electrodes 2 and 3, pb, an alloy containing pb as a main component, Nb, a Nb compound, etc. may be used.
このようにして作製された超電導トランジスタは、チャ
ネル層となる突起部4を超電導体のコヒーレント長さの
10倍程度である0、5 μm以下に、精度よく容易
に形成できる。In the superconducting transistor manufactured in this way, the protrusion 4 which becomes the channel layer can be easily and accurately formed to a thickness of 0.5 μm or less, which is about 10 times the coherent length of the superconductor.
つまり超電導電極間の空間的な距離が精度よく形成され
ているので特性のばらつきが小さく歩留まりの高い素子
を得ることができた。In other words, since the spatial distance between the superconducting electrodes was formed with high precision, it was possible to obtain a device with small variations in characteristics and high yield.
また、制御電極4に印加された電圧によって2つの超電
導電極2,3の超電導弱結合状態が変化することを動作
原理としているが、絶縁物層7を制御電極4のまわりに
形成して電極間を分離することにより誤動作を防ぐこと
がでiる。Furthermore, although the operating principle is that the superconducting weak coupling state between the two superconducting electrodes 2 and 3 changes depending on the voltage applied to the control electrode 4, an insulator layer 7 is formed around the control electrode 4 to By separating the two, malfunctions can be prevented.
また、超電導電極2と3は、対向しているため、この間
の電流は流れやすくなり、より高速の超電導トランジス
タを得ることができる。Furthermore, since the superconducting electrodes 2 and 3 are facing each other, current flows easily between them, and a higher speed superconducting transistor can be obtained.
さらにセルファライ工程を適用できるため、マスク数工
程数も減り、プロセス的に容易となる。Furthermore, since a self-lay process can be applied, the number of mask steps is also reduced, making the process easier.
第4図に本発明の他の実施例を示す。この実施例では一
つの制御電極に対し、ソースおよびドレンの両電極を複
数個直列に接続した構造となっている。すなわち、基板
1上には先の実施例で説明した方法により形成された三
個の突起部分4が設けられ、これらの突起部分をそれぞ
れ挟むように超電導電極9,10,11.12が設けら
れている。そして、三つの突起部分に絶縁物層6を介し
て一つの制御電極13を設けている。内側の超電だ
導電極10,11は、左端ナトレイン、右端がソースの
2つの役割を兼ねている。この素子によれば、1つの超
電導トランジスタの出力電圧の3倍の出力電圧を得るこ
とができる。つまり、一つの制御電極に対し、直列に接
続する超電導電極の個数を多くすることにより、回路利
得を大きくすることが可能となる。FIG. 4 shows another embodiment of the invention. This embodiment has a structure in which a plurality of source and drain electrodes are connected in series to one control electrode. That is, three protrusions 4 formed by the method described in the previous embodiment are provided on the substrate 1, and superconducting electrodes 9, 10, 11, and 12 are provided to sandwich these protrusions, respectively. ing. One control electrode 13 is provided on the three protruding portions with an insulating layer 6 interposed therebetween. The inner superconducting electrodes 10 and 11 have two roles: the left end serves as a natrain, and the right end serves as a source. According to this element, an output voltage three times the output voltage of one superconducting transistor can be obtained. That is, by increasing the number of superconducting electrodes connected in series to one control electrode, it is possible to increase the circuit gain.
本発明によれば、2つの超電導体が半導体を介して結合
した超電導トランジスタにおいて、超電導体間の距離が
精度よく決定されるので、トランジスタ特性のばらつき
を抑えることができ、従って信頼性の高い高速のスイッ
チング素子を提供できる効果がある。According to the present invention, in a superconducting transistor in which two superconductors are coupled via a semiconductor, the distance between the superconductors is determined with high accuracy, so variations in transistor characteristics can be suppressed, and therefore, reliable high-speed This has the effect of providing a switching element.
第1図は従来の超電導トランジスタの断面図、第2図は
本発明の実施例による超電導トランジスタの断面図、第
3図はその作製工程図、第4図は本発明の他の実施例に
よる超電導トランジスタの断面図である。Fig. 1 is a cross-sectional view of a conventional superconducting transistor, Fig. 2 is a cross-sectional view of a superconducting transistor according to an embodiment of the present invention, Fig. 3 is a diagram of its manufacturing process, and Fig. 4 is a superconducting transistor according to another embodiment of the present invention. FIG. 2 is a cross-sectional view of a transistor.
Claims (1)
に形成され、かつ突起部分の両側に接して設けられた一
対の超電導電極と、前記半導体の突起部分の上部に絶縁
物層を介して設けられた制御電極を有することを特徴と
する超電導トランジスタ。 2、特許請求の範囲第1項において、前記制御電極は側
面が絶縁されていることを特徴とする超電導トランジス
タ。 3、特許請求の範囲第1項または第2項において、前記
制御電極は、ポリシリコンよりなることを特徴とする超
電導トランジスタ。 4、特許請求の範囲第1項または第2項において、前記
制御電極は、常電導金属よりなることを特徴とする超電
導トランジスタ。[Claims] 1. A substrate having a protruding portion made of a semiconductor; a pair of superconducting electrodes formed on the substrate and provided in contact with both sides of the protruding portion; A superconducting transistor characterized by having a control electrode provided through an insulating layer. 2. The superconducting transistor according to claim 1, wherein the control electrode has an insulated side surface. 3. A superconducting transistor according to claim 1 or 2, wherein the control electrode is made of polysilicon. 4. A superconducting transistor according to claim 1 or 2, wherein the control electrode is made of a normal conducting metal.
Priority Applications (8)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP60046539A JPS61206277A (en) | 1985-03-11 | 1985-03-11 | Superconductive transistor |
EP95104470A EP0667645A1 (en) | 1984-11-05 | 1985-11-04 | Superconducting device |
EP85308009A EP0181191B1 (en) | 1984-11-05 | 1985-11-04 | Superconducting device |
DE3588086T DE3588086T2 (en) | 1984-11-05 | 1985-11-04 | Superconductor arrangement |
US07/073,408 US4884111A (en) | 1984-11-05 | 1987-07-13 | Superconducting device |
US07/412,201 US5126801A (en) | 1984-11-05 | 1989-09-25 | Superconducting device |
US07/875,431 US5311036A (en) | 1984-11-05 | 1992-04-29 | Superconducting device |
US08/201,410 US5442196A (en) | 1984-11-05 | 1994-02-24 | Superconducting device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP60046539A JPS61206277A (en) | 1985-03-11 | 1985-03-11 | Superconductive transistor |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS61206277A true JPS61206277A (en) | 1986-09-12 |
Family
ID=12750096
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP60046539A Pending JPS61206277A (en) | 1984-11-05 | 1985-03-11 | Superconductive transistor |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS61206277A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH01200680A (en) * | 1988-02-05 | 1989-08-11 | Hitachi Ltd | Superconducting field-effect transistor |
JPH0214586A (en) * | 1988-07-01 | 1990-01-18 | Hitachi Ltd | Superconductive transistor |
-
1985
- 1985-03-11 JP JP60046539A patent/JPS61206277A/en active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH01200680A (en) * | 1988-02-05 | 1989-08-11 | Hitachi Ltd | Superconducting field-effect transistor |
JPH0214586A (en) * | 1988-07-01 | 1990-01-18 | Hitachi Ltd | Superconductive transistor |
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