JPS61269385A - Superconductive device - Google Patents
Superconductive deviceInfo
- Publication number
- JPS61269385A JPS61269385A JP60110371A JP11037185A JPS61269385A JP S61269385 A JPS61269385 A JP S61269385A JP 60110371 A JP60110371 A JP 60110371A JP 11037185 A JP11037185 A JP 11037185A JP S61269385 A JPS61269385 A JP S61269385A
- Authority
- JP
- Japan
- Prior art keywords
- protrusion
- film
- insulating film
- superconducting
- superconductive
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N60/00—Superconducting devices
- H10N60/10—Junction-based devices
- H10N60/128—Junction-based devices having three or more electrodes, e.g. transistor-like structures
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Superconductor Devices And Manufacturing Methods Thereof (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の利用分野〕
本発明は極低温で動作するスイッチング・デバイスに係
り、特に回路の利得を大きくシ、かつ集積回路を作製す
るために好適な、超伝導デバイスの構造に関する。[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to a switching device that operates at extremely low temperatures, and particularly to a superconducting device that increases circuit gain and is suitable for manufacturing integrated circuits. Regarding structure.
従来の極低温で動作するスイッチング・デバイスとして
はジョセフソン素子が知られている。このジョセフソン
素子のスイッチ速度は高速であり。A Josephson element is known as a conventional switching device that operates at extremely low temperatures. The switching speed of this Josephson element is fast.
また消費電力は数μWと小さい、しかしジョセフソン素
子は基本的には二端子デバイスであり、従って回路の構
成に、従来の半導体トランジスタで蓄積されてきた技術
を使用することができず、また交流の電源を使用しなけ
ればならない、この課題を解決で危る公知の超伝導デバ
イスとしては次の2つがある。第1にはアイトリプルイ
ー・トランザクションオン・マグネティクス(IEEE
τransaction Magnati、cs)
MA G −19巻1983年1293ページに掲載さ
れたる“クイトロン”(Quitaron)と称する準
粒子を利用した超伝導デバイスがある。このデバイスは
準粒子の寿命がスイッチ速度を制限するためにスイッチ
ングの高速化のために素子構造が特殊になる。第2には
ジャーナル・オン・アプライド・フイジイクス51巻1
980年2736ページに掲載されたる“ジョセフソン
・フィールド・エフェクト・トランジスター”(Jos
aphson Field Effect Trons
istor) と題する論文に開示されたる超伝導デ
バイスがある。このデバイスは制御電極がチャネル層か
ら電気的に完全に分離されておらず、従って電流利得を
大きくすることは困難であった6以上、述べたるごと〈
従来技術においては大規模なデジタル集積回路を構成す
るために十分な性能を持った超伝導デバイスが必ずしも
提供されてはいなかった。In addition, the power consumption is small at a few μW, but Josephson elements are basically two-terminal devices, so the technology that has been accumulated with conventional semiconductor transistors cannot be used in the circuit configuration, and There are two known superconducting devices that require the use of a power source and are at risk of solving this problem: The first is iTriple E Transaction on Magnetics (IEEE
τtransaction Magnati, cs)
There is a superconducting device using quasiparticles called "Quitaron" published in MA G-19, 1983, page 1293. In this device, the lifetime of the quasiparticle limits the switching speed, so the element structure has to be special to increase the switching speed. The second is Journal on Applied Physics, Volume 51, Volume 1.
“Josephson Field Effect Transistor” (Josepson Field Effect Transistor) published in 980, page 2736
aphson Field Effect Trons
There is a superconducting device disclosed in a paper titled . In this device, the control electrode was not completely electrically isolated from the channel layer, and therefore it was difficult to increase the current gain6.
In the prior art, superconducting devices with sufficient performance to construct large-scale digital integrated circuits have not always been provided.
本発明の目的は、平坦化された構造を有し、しかも利得
が高いために集積回路への応用に適した超伝導デバイス
の構造を提供することにある。An object of the present invention is to provide a structure of a superconducting device which has a planarized structure and has a high gain and is therefore suitable for application to integrated circuits.
本発明の超伝導デバイスは、デバイスを平坦化して、し
かも利得を向上させるために、半導体基板上にショット
キ障壁低減用の2つの不純物導入部と、その間の低不純
物濃度部分を設け、しかも低不純物濃度部分は、半導体
上に設けた超伝導電極の厚さと同程度かあるいはそれよ
りも薄い凸起中に形成して、デバイスの平坦化を図った
点に特徴がある。In the superconducting device of the present invention, in order to flatten the device and improve gain, two impurity introduction regions for reducing the Schottky barrier and a low impurity concentration region between them are provided on the semiconductor substrate, and a low impurity concentration region is provided on the semiconductor substrate. A feature of the device is that the concentration portion is formed in a protrusion that is about the same thickness or thinner than the superconducting electrode provided on the semiconductor, thereby flattening the device.
以下1本発明を実施例を用いて詳細に説明する。 The present invention will be explained in detail below using examples.
第1図は本発明の一実施例による超伝導デバイスの一部
を示す断面図である。不純物濃度1×IQ14cm−”
以下のホウ素を不純物として含んだSi基板1の表面を
酸化して、厚さ30nmのS i O,より成る酸化膜
2を形成したのち、その上にホトレジストパターンを形
成しこれをマスクとしてCF、ガスを用いたプラズマエ
ツチングあるいはA r @ CF 4等のガスによる
イオンビームエツチングによってSi基板の表面をエツ
チングし、突起部3を形成する。該突起部の高さ、すな
わちSi基板のエツチング量は、後に形成する超伝導電
極の厚さと同じかそれよりも小さいことが望ましい1本
実施例では200nmとした。また突起部の幅は、0.
3〜0.1μmに選ばれることが望ましい、続いて試料
全面に表面濃度1×10”am−”でホウ素の拡散を行
い拡散層4を形成する。拡散層4は拡散法のほがイオン
打込み法を用いても本実施例における目的を達すること
ができる。尚、本実施例では拡散層の厚さを表面から5
0nm程度に形成した。突起部では該拡散層が両側から
形成され、中央に不純物濃度の低い部分が残る0次にN
bをlXl0−”Pa以下の高真空中で電子ビーム加熱
によって蒸着し、厚さ約200nmのNbgを堆積させ
る。Nb[(7)堆積には、電子ビーム蒸着のほかにス
パッタリング法を用いること−もできる。このNb膜を
ホトレジストパターンをマスクとしてCF4ガスによる
プラズマエツチングによって加工し、超電導電極5,6
を得る。突起部3と超伝導電極5,6は、はぼ同一の高
さに存在し、従ってデバイスの平坦化が実現できる0次
に気相成長法により厚さ50nmのSin。FIG. 1 is a sectional view showing a part of a superconducting device according to an embodiment of the present invention. Impurity concentration 1×IQ14cm-”
After oxidizing the surface of a Si substrate 1 containing the following boron as an impurity to form an oxide film 2 made of SiO with a thickness of 30 nm, a photoresist pattern was formed on it, and using this as a mask, CF, The surface of the Si substrate is etched by plasma etching using a gas or ion beam etching using a gas such as Ar @ CF 4 to form protrusions 3 . The height of the protrusion, that is, the amount of etching of the Si substrate is preferably 200 nm in this embodiment, which is the same as or smaller than the thickness of the superconducting electrode to be formed later. Further, the width of the protrusion is 0.
The thickness is preferably selected to be 3 to 0.1 .mu.m. Subsequently, boron is diffused over the entire surface of the sample at a surface concentration of 1.times.10 "am-" to form a diffusion layer 4. The purpose of this embodiment can be achieved by using the ion implantation method rather than the diffusion method for forming the diffusion layer 4. In this example, the thickness of the diffusion layer is 5 mm from the surface.
It was formed to have a thickness of about 0 nm. In the protrusion, the diffusion layer is formed from both sides, leaving a part with low impurity concentration in the center.
Nbg is deposited to a thickness of about 200 nm by electron beam heating in a high vacuum of less than lXl0-''Pa. This Nb film is processed by plasma etching using CF4 gas using the photoresist pattern as a mask, and superconducting electrodes 5 and 6 are formed.
get. The protrusion 3 and the superconducting electrodes 5 and 6 are formed at a thickness of 50 nm using zero-order vapor phase epitaxy, which allows the device to be planarized.
膜を形成し、同じくプラズマエツチングによって加工し
て絶縁膜7を形成したのち、制御電極8をNbの真空蒸
着による製膜とプラズマエツチングによる加工によって
形成し、本発明の超伝導デバイスは完成した。SiO,
膜は気相成長法にかえて、スパッタリング法によって形
成することも可能である。After a film was formed and processed by plasma etching to form an insulating film 7, a control electrode 8 was formed by vacuum evaporation of Nb and processing by plasma etching, completing the superconducting device of the present invention. SiO,
The film can also be formed by sputtering instead of vapor phase growth.
この超伝導デバイスを用いて集積回路を作製し液体ヘリ
ウム温度(4,2K) に冷却して動作させたところ
1本超伝導デバイスは、チャネルに相当する部分の不純
物濃度がI X 1. O”cn−”程度と低いうえに
、超伝導体と半導体の接蝕部には半導体側に拡散層が存
在するため、超伝導電子の半導体中への染み出しが容易
になり、また数mVの電圧を制御電極に印加することに
よって、半導体中のコヒーレンス長さが変化し2つの超
伝導電極間に流れる超伝導電流の大きさを10〜100
倍程度変化させることができた。さらに前述のごとくに
デバイスが平坦化されているために、制御電極に延在す
る配線とこれを結ぶための他の配線層とを多層にして立
体的に形成することが可能となり、高い集積度を実現し
、なおかつ高い製造歩留りを得ることができた。また1
本実施例では酸化膜2をあらかじめ形成してゲート絶縁
膜を構成しているので、界面準位を低減できデバイスの
動作を安定化することができる。なお、本実施例では、
半導体材料にSiを用いたが、これに代えて、GaAs
、InAs、InP、InSb等の材料を用いても良い
ことは言うまでもない、また超電導材料にNbを用いた
が、これに代えてpb金合金あるいはNbN、Nb、S
i、Nb、AI2.Nb、Sn等のNbの化合物、M
o N等のMo化合物を使用しても同様の効果を得るこ
とができた。また不純物の種類はホウ素にかえて、リン
、ヒ素、アンチモン等を用いても良い。When an integrated circuit was fabricated using this superconducting device and operated after being cooled to liquid helium temperature (4.2 K), the impurity concentration in the portion corresponding to the channel of the single superconducting device was found to be I x 1. In addition to being as low as O"cn-", there is a diffusion layer on the semiconductor side in the corrosion area between the superconductor and the semiconductor, so superconducting electrons easily seep into the semiconductor, and By applying a voltage of
I was able to double the amount. Furthermore, since the device is flattened as mentioned above, it is possible to form a three-dimensional structure with multiple layers of wiring extending to the control electrode and other wiring layers to connect them, resulting in a high level of integration. We were able to achieve this and achieve a high manufacturing yield. Also 1
In this embodiment, since the oxide film 2 is formed in advance to constitute the gate insulating film, the interface state can be reduced and the operation of the device can be stabilized. In addition, in this example,
Although Si was used as the semiconductor material, GaAs was used instead.
It goes without saying that materials such as , InAs, InP, and InSb may be used.Also, although Nb was used as the superconducting material, a pb gold alloy, NbN, Nb, Sb, etc. may be used instead.
i, Nb, AI2. Nb, Nb compounds such as Sn, M
Similar effects could be obtained using Mo compounds such as oN. Moreover, the type of impurity may be replaced with boron, such as phosphorus, arsenic, antimony, etc.
また、不純物は基板と同導電型のものを用いることが好
ましいが異なる導電型の不純物を用いても本発明の効果
を得ることができる。Further, although it is preferable to use impurities of the same conductivity type as the substrate, the effects of the present invention can be obtained even if impurities of different conductivity types are used.
以上述べたように、本発明によれば、デバイスにおける
超伝導電流の大きさを100倍程度まで変化させること
ができるので、デバイスとしての利得を向上させること
ができる利点がある。またデバイスが平坦化されている
ので、上部に立体的に配線層を形成することが容易であ
り、従って回路の集積度を高くしたとき、没差部での配
線の断線を防ぐことができ、従って高い製造歩留りを得
ることのできる利点がある。As described above, according to the present invention, the magnitude of the superconducting current in the device can be changed up to about 100 times, so there is an advantage that the gain of the device can be improved. In addition, since the device is flattened, it is easy to form a three-dimensional wiring layer on the top, and therefore, when the degree of circuit integration is increased, disconnection of wiring at the recessed part can be prevented. Therefore, there is an advantage that a high manufacturing yield can be obtained.
第1図は本発明の一実施例による超伝導デバイスの一部
を示す断面図。FIG. 1 is a sectional view showing a part of a superconducting device according to an embodiment of the present invention.
Claims (1)
上部に設けられた第1の絶縁膜と、該突起部の高さと同
じかあるいはそれよりも大きな厚さを有し、かつ突起部
側面に形成された2つ又はそれ以上の超伝導電極と、前
記第1の絶縁膜上に形成された第2の絶縁膜と、該第2
の絶縁膜に設けた制御電極とを、少なくとも有し、前記
突起部はその側面が基板よりも高い不純物濃度を有する
よう形成されたことを特徴とする超伝導デバイス。1. A semiconductor protrusion provided on a semiconductor substrate, a first insulating film provided on the top of the protrusion, and a protrusion having a thickness equal to or greater than the height of the protrusion; two or more superconducting electrodes formed on a side surface of the part, a second insulating film formed on the first insulating film, and a second insulating film formed on the first insulating film;
a control electrode provided on an insulating film, and the protrusion is formed so that its side surface has a higher impurity concentration than that of the substrate.
Priority Applications (8)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP60110371A JPS61269385A (en) | 1985-05-24 | 1985-05-24 | Superconductive device |
DE3588086T DE3588086T2 (en) | 1984-11-05 | 1985-11-04 | Superconductor arrangement |
EP85308009A EP0181191B1 (en) | 1984-11-05 | 1985-11-04 | Superconducting device |
EP95104470A EP0667645A1 (en) | 1984-11-05 | 1985-11-04 | Superconducting device |
US07/073,408 US4884111A (en) | 1984-11-05 | 1987-07-13 | Superconducting device |
US07/412,201 US5126801A (en) | 1984-11-05 | 1989-09-25 | Superconducting device |
US07/875,431 US5311036A (en) | 1984-11-05 | 1992-04-29 | Superconducting device |
US08/201,410 US5442196A (en) | 1984-11-05 | 1994-02-24 | Superconducting device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP60110371A JPS61269385A (en) | 1985-05-24 | 1985-05-24 | Superconductive device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS61269385A true JPS61269385A (en) | 1986-11-28 |
Family
ID=14534100
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP60110371A Pending JPS61269385A (en) | 1984-11-05 | 1985-05-24 | Superconductive device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS61269385A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS62232978A (en) * | 1986-04-03 | 1987-10-13 | Nippon Telegr & Teleph Corp <Ntt> | Semicomductor element |
-
1985
- 1985-05-24 JP JP60110371A patent/JPS61269385A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS62232978A (en) * | 1986-04-03 | 1987-10-13 | Nippon Telegr & Teleph Corp <Ntt> | Semicomductor element |
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