JP2594934B2 - Weakly coupled Josephson device - Google Patents

Weakly coupled Josephson device

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Publication number
JP2594934B2
JP2594934B2 JP62077414A JP7741487A JP2594934B2 JP 2594934 B2 JP2594934 B2 JP 2594934B2 JP 62077414 A JP62077414 A JP 62077414A JP 7741487 A JP7741487 A JP 7741487A JP 2594934 B2 JP2594934 B2 JP 2594934B2
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JP
Japan
Prior art keywords
film
superconductor
electrode
normal conductor
thickness
Prior art date
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Expired - Lifetime
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JP62077414A
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Japanese (ja)
Other versions
JPS63245972A (en
Inventor
信雄 宮本
壽一 西野
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Hitachi Ltd
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Hitachi Ltd
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    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10NELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N60/00Superconducting devices
    • H10N60/10Junction-based devices
    • H10N60/12Josephson-effect devices

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  • Superconductor Devices And Manufacturing Methods Thereof (AREA)

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は液体ヘリウム温度近傍で動作させる弱結合型
ジヨセフソン素子に係り、特に高速のスイツチング動作
に好適な弱結合型ジヨセフソン素子に関する。
Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a weak-coupled Josephson device operated near liquid helium temperature, and more particularly to a weak-coupled Josephson device suitable for high-speed switching operation.

〔従来の技術〕[Conventional technology]

従来の弱結合型ジヨセフソン素子については、アイ・
イー・イー・イー,トランザクシヨンズ オン エレク
トロン デバイセス,イーデー −28巻,第11号(198
1)第1394頁から第1397頁(IEEE,TRANSACTIONS ON ELEC
TRON DEVICES,VOL.ED−28,No.11(1981)pp.1394−139
7)において論じられている。また、基板の段差部を用
いて弱結合を形成することは、特願昭54−122376号、特
願昭55−16923号に記載されている。しかし、上記従来
例に記載の弱結合部は超電導体からなり、2つの超電導
膜を弱く結びつけているくびれ部分からなっている。
For the conventional weakly-coupled Josephson device,
EEE, Transactions on Electron Devices, Eday -28, Issue 11 (198
1) Pages 1394 to 1397 (IEEE, TRANSACTIONS ON ELEC
TRON DEVICES, VOL.ED-28, No.11 (1981) pp.1394-139
7). The formation of a weak bond using a step portion of a substrate is described in Japanese Patent Application Nos. 54-122376 and 55-16923. However, the weak coupling portion described in the above-mentioned conventional example is made of a superconductor, and is made of a constricted portion that weakly connects the two superconducting films.

〔発明が解決しようとする問題点〕 この素子は第6図に示すように、Siから成る常導電体
64上でPbとInの合金薄膜から成る超電導体電極65及び66
を対向させた平面形構造になつている。一般にこのよう
な構造の弱結合型ジヨセフソン素子の超電導体電極間を
流れるジヨセフソン電流Iは、 I∝(T2)・exp(−L/ξ) …(式1) で与えられる。ここでTは素子の動作温度で、超電導電
極の超電導転移温度より低く、一般に液体ヘリウム温度
(4.2゜K)である。ξは常電導体中の電子対コヒーレ
ンス長で、常電導性の性質によつて定まる。Lは2つの
超電導体電極の対向間隔で、結合長と称する。この素子
で実用に足りる数μA以上のジセフソン接合電流を得る
ためには、結合長Lを電子対コヒーレンス長ξの10倍
程度以下、すなわち約0.5μm以下にする必要があり、
かつジヨセフソン接合電流のそろつた多数個の素子を作
製するためには、各結合長の寸法精度を高める必要があ
る。従来技術においては、まずSi基板上にPb−In合金か
ら成る超電導体薄膜を形成し、次いでフオトレジストあ
るいは電子線レジストをマスクとしたエツチングによつ
て素子パターン及び結合長部分を加工し、接近した2つ
の超電導体電極を形成していた。このように平面形構造
の素子では、結合長部分を、0.5μm以下という極めて
微細なパターン寸法で精度良く、また再現性良く加工す
る工程を必要としているが、この加工は必ずしも容易で
はなかつた。このため、従来法では作製した素子は、結
合長に依存するジヨセフソン接合電流が基板内で約±10
%以上の分布をもち、また基板間で約±30%の分布をも
ち、電流の均一性と再現性に乏しいという問題があつ
た。
[Problems to be solved by the invention] As shown in FIG. 6, this element is a normal conductor made of Si.
Superconducting electrodes 65 and 66 consisting of Pb and In alloy thin films on 64
Are opposed to each other in a planar structure. Generally Jiyosefuson current I flowing between the superconductor electrodes of weak coupling type Jiyosefuson element having such a structure is given by the Iα (T 2 / ξ n) · exp (-L / ξ n) ... ( Equation 1). Here, T is the operating temperature of the element, which is lower than the superconducting transition temperature of the superconducting electrode, and is generally a liquid helium temperature (4.2 K). ξ n in the electron pair coherence length in the normal conductor, by connexion determined the nature of the normally conducting. L is the distance between the two superconductor electrodes facing each other and is referred to as the coupling length. To obtain the number μA or more Jisefuson junction current sufficient to practical use in this device, the coupling length L less than 10 times the electron pair coherence length xi] n, i.e. should be about 0.5μm or less,
In addition, in order to fabricate a large number of devices having the same Josephson junction current, it is necessary to increase the dimensional accuracy of each coupling length. In the prior art, first, a superconductor thin film made of a Pb-In alloy is formed on a Si substrate, and then the device pattern and the coupling length are processed by etching using a photoresist or an electron beam resist as a mask. Two superconductor electrodes were formed. As described above, in the element having the planar structure, a process of processing the coupling length portion with an extremely fine pattern dimension of 0.5 μm or less with high accuracy and high reproducibility is required, but this processing is not always easy. For this reason, the device manufactured by the conventional method has a Josephson junction current depending on the coupling length of about ± 10
% Or more, and a distribution of about ± 30% between substrates, resulting in poor current uniformity and poor reproducibility.

本発明の目的は、常電導体を介して2つの超電導体を
接続して構成する弱結合型ジヨセフソン素子において、
2つの超電導体の微細な結合の形成を容易にし、かつそ
の寸法精度を高め、これによつて素子特性の均一性と再
現性を向上できる新しい素子構造を提供することにあ
る。
An object of the present invention is to provide a weak-coupling-type Josephson element configured by connecting two superconductors via a normal conductor,
It is an object of the present invention to provide a new device structure which facilitates formation of a fine coupling between two superconductors and enhances its dimensional accuracy, thereby improving uniformity and reproducibility of device characteristics.

〔問題点を解決するための手段〕[Means for solving the problem]

上記目的を達成するため、本発明では結合長部分をパ
ターン加工して形成する従来の平面形素子構造に代え
て、常電導体あるいは絶縁体で形成した段差部分で2つ
の超電導体を分離し、かつこの段差部における段差の大
きさを基準として結合長を決める第1の素子構造とし
た。
In order to achieve the above object, in the present invention, instead of the conventional planar element structure in which the coupling length portion is formed by pattern processing, two superconductors are separated by a step portion formed of a normal conductor or an insulator, In addition, a first element structure in which the coupling length is determined based on the size of the step in the step portion is adopted.

また、本発明では常電導体を2つの超電導体で挾んだ
三層構造として、該常電導体の膜厚を結合長とし、かつ
弱結合部を除く常電導体に形成した絶縁体層で、2つの
超電導体を電気的に分離する第2の素子構造とした。
In the present invention, the normal conductor has a three-layer structure in which the normal conductor is sandwiched between two superconductors. And a second element structure for electrically separating the two superconductors.

〔作用〕[Action]

この第1の素子構造によれば、段差を真空蒸着等の薄
膜堆積法、あるいは常電導体をエツチングする方法によ
り形成することが可能である。この薄膜堆積法及びエツ
チング法は、数nmの単位で寸法制御を再現性良く行なう
ことが可能であり、段差の大きさすなわち結合長の寸法
精度とその再現性を格段に高めることができる。従つて
素子特性の均一性と再現性を向上できる。
According to the first element structure, the steps can be formed by a thin film deposition method such as vacuum deposition or a method of etching a normal conductor. In the thin film deposition method and the etching method, dimensional control can be performed with good reproducibility in a unit of several nm, and the size of the step, that is, the dimensional accuracy of the coupling length and the reproducibility can be remarkably improved. Therefore, the uniformity and reproducibility of the device characteristics can be improved.

この第2の素子構造によれば、弱結合材料となる常電
導体の膜厚を制御することにより、任意の結合長を有す
る素子を作製することができる。この常電導体は真空蒸
着法あるいはスパツタリング法等の薄膜堆積法により形
成することが可能であり、これらの薄膜堆積法は数nmの
精度で膜厚、すなわち結合長を再現性良く制御できる。
従つて結合長に依存する素子特性の均一性と再現性を向
上できる。
According to the second element structure, an element having an arbitrary coupling length can be manufactured by controlling the thickness of the normal conductor serving as a weak coupling material. The normal conductor can be formed by a thin film deposition method such as a vacuum evaporation method or a sputtering method, and these thin film deposition methods can control the film thickness, that is, the bond length with a reproducibility of several nm.
Therefore, the uniformity and reproducibility of device characteristics depending on the coupling length can be improved.

〔実施例〕〔Example〕

以下、実施例1〜5を用いて本発明の第1の素子構造
について詳細に説明する。
Hereinafter, the first element structure of the present invention will be described in detail using Examples 1 to 5.

(実施例1) (1)まず第1図(a)に示すように、フオトレジスト
13(ヘキスト(Hoechst)社製、商品名:AZ−1350J)の
パターンを形成した直径2インチのSi基板11上に、段差
材12として厚さ0.5μmのSiを真空蒸着法により形成し
た。このSiは、本発明の弱結合型ジヨセフソン接合が動
作する、極低温において、アクセプタ、あるいはドナー
がフリーズ・アウトする程度にすなわち1×1024m-3
下に少なくしてある。
(Example 1) (1) First, as shown in FIG.
Si (0.5 μm thick) was formed as a step member 12 on a 2-inch diameter Si substrate 11 on which a pattern 13 (manufactured by Hoechst, trade name: AZ-1350J) was formed by vacuum evaporation. This Si is reduced to such an extent that the acceptor or the donor freezes out at an extremely low temperature at which the weak-bond type Josephson junction of the present invention operates, that is, 1 × 10 24 m −3 or less.

(2)そして、該フオトレジスト13をアセトンで溶解除
去することにより、第1図(b)に示すようにSi段差材
12で高さの0.5μmの段差部を形成した。
(2) Then, by dissolving and removing the photoresist 13 with acetone, as shown in FIG.
At 12, a step having a height of 0.5 μm was formed.

(3)次いで、第1図(c)に示すように常電導体14と
して厚さ1μmのCu膜を真空蒸着法により形成したの
ち、同一真空槽内で超電導体電極15及び16として、厚さ
0.3μmのNb膜を真空蒸着法により該Cu膜上に形成し
た。この際、Nbは段差面が見通せない方向から蒸着し、
段差面にNbが蒸着されないようにした。これにより、Nb
超電導体電極15と同電極16は、段差部で0.2μmの間
隙、すなわち結合長17で分離された。
(3) Next, as shown in FIG. 1 (c), a Cu film having a thickness of 1 μm is formed as a normal conductor 14 by a vacuum evaporation method, and then the superconductor electrodes 15 and 16 are formed in the same vacuum chamber.
A 0.3 μm Nb film was formed on the Cu film by a vacuum evaporation method. At this time, Nb is deposited from a direction where the step surface cannot be seen,
Nb was not deposited on the step surface. This gives Nb
The superconductor electrode 15 and the superconductor electrode 16 were separated by a gap of 0.2 μm, that is, a coupling length 17 at the step.

ここでNb超電導体電極膜をスパツタリング法によつて
形成した場合、段差面にもNbが飛着し、該電極15と16は
短絡した。しかし、この後CF4ガスを用いた反応性プラ
ズマエツチング法でNb膜を厚さ10〜20nmのエツチングに
よつて除去することにより、段差面に付着したNbを除去
でき、該電極15と16を段差部で分離することができた。
Here, when the Nb superconductor electrode film was formed by the sputtering method, Nb jumped onto the step surface, and the electrodes 15 and 16 were short-circuited. However, by by connexion removed etching thickness 10~20nm the Nb film by reactive plasma Etsu quenching method using this after CF 4 gas, can be removed Nb adhering to the stepped surface, the electrodes 15 and 16 Separation was possible at the step.

(4)最後に、フオトレジストをマスク材とし、CF4
スを用いたプラズマエツチング法によりNb超電導体電極
膜15及び16をエツチングして、第1図(d)に示すよう
な弱結合型ジヨセフソン素子を完成した。
(4) Finally, the Nb superconductor electrode films 15 and 16 are etched using a photoresist as a mask material by a plasma etching method using CF 4 gas to form a weakly-coupled Josephson as shown in FIG. The device was completed.

本実施例において結合長17は、段差材12の高さ(膜
厚)あるいは超電導体電極15の膜厚を変えることによつ
て、任意の長さにすることができる。そこでSi段差材12
の高さを0.5μmに固定し、Nb超電導体電極15の膜厚を
前述した0.3μmに加えて、0.2μm,0.25μm,0.35μm,0.
4μmとした結果、結合長が0.1μm,0.15μm,0.2μm,0.2
5μm,0.3μmの接合を作製することができた。これらの
接合長の寸法精度は、Si段差材とNb超電導電極を真空蒸
着するときの膜厚制御性と膜厚の場所的な分布によつて
定まる。本実施例の場合は、この寸法精度は設定値の±
1%以下で、この再現性は±2%以下で極めて良好であ
つた。この結果、従来法で基板内で約±10%以上分布し
ていた接合電流を±5%以下に、また、従来試作ロツト
間で約±30%ばらついていた接合電流を±10%以下に低
減でき、接合電流の均一性と再現性を向上することがで
きた。
In this embodiment, the coupling length 17 can be set to an arbitrary length by changing the height (film thickness) of the step member 12 or the film thickness of the superconductor electrode 15. Therefore, the Si step material 12
Is fixed at 0.5 μm, and the film thickness of the Nb superconductor electrode 15 is added to the aforementioned 0.3 μm, and 0.2 μm, 0.25 μm, 0.35 μm, 0.
As a result of 4 μm, the bond length is 0.1 μm, 0.15 μm, 0.2 μm, 0.2
5 μm and 0.3 μm junctions could be produced. The dimensional accuracy of these bonding lengths is determined by the film thickness controllability and the spatial distribution of the film thickness when vacuum depositing the Si step material and the Nb superconducting electrode. In the case of the present embodiment, this dimensional accuracy is ±
At 1% or less, the reproducibility was very good at ± 2% or less. As a result, the junction current, which was distributed about ± 10% or more in the substrate by the conventional method, is reduced to ± 5% or less, and the junction current, which was about ± 30% scattered between prototype lots, is reduced to ± 10% or less. As a result, the uniformity and reproducibility of the junction current were improved.

(実施例2) (1)まず第2図(a)に示すように、Si基板21全面に
常電導体24として厚さ1μmのCu膜を真空蒸着法により
形成したのち、フオトレジスト23のパターンを形成し
た。
(Example 2) (1) First, as shown in FIG. 2 (a), a Cu film having a thickness of 1 μm is formed as a normal conductor 24 on the entire surface of a Si substrate 21 by a vacuum deposition method, and then a pattern of a photoresist 23 is formed. Was formed.

(2)次いで該フオトレジストをマスク材として、Arガ
スを用いたイオンミリング法により該Cu膜を0.5μmの
深さまでエツチングした。そして該フオトレジストをア
セトンで溶解除去して、第2図(b)に示すようにCu膜
に0.5μmの段差を形成した。
(2) Next, using the photoresist as a mask material, the Cu film was etched to a depth of 0.5 μm by an ion milling method using Ar gas. The photoresist was dissolved and removed with acetone to form a step of 0.5 μm on the Cu film as shown in FIG. 2 (b).

(3)次に前記試料の表面を1.33PaのArガス雰囲気中で
高周波スパツタエツチングして、試料の表面の不純物及
び酸化物を除去したのち、超電導体電極25及び26として
厚さ0.3μmのNb膜を真空蒸着法により第2図(c)に
示すように形成した。
(3) Next, the surface of the sample is subjected to high frequency sputtering in an Ar gas atmosphere of 1.33 Pa to remove impurities and oxides on the surface of the sample. An Nb film was formed by a vacuum evaporation method as shown in FIG.

(4)そしてフオトレジスト(前記AZ−1350J)をマス
ク材とし、CF4ガスを用いたプラズマエツチング法によ
り該Nb膜をエツチングして第2図(d)に示すような弱
結合型ジヨセフソン素子を完成した。そして実施例1と
同様に、ジヨセフソン接合電流の均一性と再現性を向上
できた。
(4) Then, using the photoresist (AZ-1350J) as a mask material and etching the Nb film by a plasma etching method using CF 4 gas, a weak coupling type Josephson device as shown in FIG. completed. As in Example 1, the uniformity and reproducibility of the Josephson junction current could be improved.

なお、本実施例では、Si基板上に形成した常電導体の
Cu膜をエツチングして段差を設けたが、Si基板に代えて
Cu基板を用い、これをエツチングして段差を形成するこ
とも可能である。
In this embodiment, the normal conductor formed on the Si substrate
Steps were provided by etching the Cu film, but instead of the Si substrate
It is also possible to use a Cu substrate and etch it to form a step.

(実施例3) (1)第3図(a)に示すようにSi基板31上にフオトレ
ジスト33(前記AZ−1350J)のパターンを形成したの
ち、段差材32として厚さ0.5μmのSiOを真空蒸着法によ
り形成した。
Example 3 (1) After forming a pattern of a photoresist 33 (AZ-1350J) on a Si substrate 31 as shown in FIG. 3 (a), 0.5 μm thick SiO was used as a step member 32. It was formed by a vacuum evaporation method.

(2)そして、該フオトレジストをアセトンで溶解除去
することにより、第3図(b)に示すようにSiO段差材3
2で高さ0.5μmの段差を形成した。
(2) Then, by dissolving and removing the photoresist with acetone, as shown in FIG.
2, a step having a height of 0.5 μm was formed.

(3)次いで第3図(c)に示すように、超電導体電極
35及び36として、厚さ0.4μmのNb膜を真空蒸着法によ
り形成し、引き続いて同一真空中で常電導体34として厚
さ0.8μmのCuを該Nb膜上に蒸着した。これにより2つ
のNb超電導体電極35と36は、SiO段差材32で形成した段
差部において、0.1μmの結合長でCu常電導体34を介し
て結合された。
(3) Next, as shown in FIG.
As 35 and 36, an Nb film having a thickness of 0.4 μm was formed by a vacuum evaporation method, and subsequently, 0.8 μm thick Cu was deposited as a normal conductor 34 on the Nb film in the same vacuum. As a result, the two Nb superconductor electrodes 35 and 36 were connected to each other at the step formed by the SiO step member 32 via the Cu normal conductor 34 with a bond length of 0.1 μm.

(4)そしてフオトレジストをマスク材として、Arガス
を用いたイオンミリング法により該Cu常電導体34て該Nb
超電導体電極35及び36をエツチングして、第3図(d)
に示すように素子パターンを形成した。
(4) Then, using the photoresist as a mask material, the Cu normal conductor 34 and the Nb were formed by ion milling using Ar gas.
After etching the superconductor electrodes 35 and 36, FIG. 3 (d)
An element pattern was formed as shown in FIG.

(5)さらにフオトレジスト(前記AZ−1350J)をマス
ク材として、Arガスを用いたイオンミリング法により段
差部以外の該Cu常電導体34をエツチングして、第3図
(e)及び(f)に示すような弱結合型ジヨセフソン素
子を完成した。
(5) Using the photoresist (AZ-1350J) as a mask material, the Cu normal conductor 34 other than the stepped portion was etched by an ion milling method using Ar gas, and FIG. 3 (e) and (f). ), A weakly-coupled Josephson device was completed.

本実施例のように、超電導体電極の上に常電導体で弱
結合部を形成しても、実施例1と同様の特性が得られ、
ジヨセフソン接合電流の均一性と再現性を向上すること
ができた。
As in the present embodiment, even when the weak coupling portion is formed with a normal conductor on the superconductor electrode, the same characteristics as those of the first embodiment can be obtained.
The uniformity and reproducibility of the Josephson junction current were improved.

なお本実施例の段差材32を、SiOから常電導体のCuに
替え、超電導体電極の上下を常電導体で挾んで弱結合部
を構成することも可能である。
It should be noted that the step member 32 of the present embodiment may be replaced with Cu as a normal conductor from SiO, and a weak coupling portion may be formed by sandwiching the superconductor electrode above and below with a normal conductor.

(実施例4) 次に本発明の弱結合型ジヨセフソン素子の段差部に制
御電極を設け、ここに電圧を印加して2つの超電導体電
極間にある常電導体に電界を加え、この超電導結合状態
を変化させて、ジヨセフソン接合電流を制御する超電導
トランジスタを作製した一実施例について、第4図を用
いて説明する。
(Example 4) Next, a control electrode is provided at a step portion of the weakly-coupled Josephson device of the present invention, and a voltage is applied to the control electrode to apply an electric field to the normal conductor between the two superconductor electrodes. An embodiment in which the state is changed to produce a superconducting transistor for controlling the Josephson junction current will be described with reference to FIG.

(1)Si基板41上に制御電極48として厚さ0.5μmのNb
を真空蒸着法により形成したのち、フオトレジストをマ
スク材として、CF4ガスを用いたプラズマエツチング法
によりエツチングし、第4図(a)に示すようにNb膜で
高さ0.5μmの段差を形成した。
(1) Nb having a thickness of 0.5 μm as a control electrode 48 on a Si substrate 41
Is formed by a vacuum deposition method and then etched by a plasma etching method using CF 4 gas using a photoresist as a mask material to form a step of 0.5 μm in height with an Nb film as shown in FIG. 4 (a). did.

(2)次に第4図(b)に示すように、フオトレジスト
43でNb制御電極48の配線パツド部を被覆して、陽極酸化
法により該Nbの表面に厚さ約30nmの酸化Nb絶縁膜49を形
成した。
(2) Next, as shown in FIG.
The wiring pad portion of the Nb control electrode 48 was covered with 43, and an Nb oxide insulating film 49 having a thickness of about 30 nm was formed on the surface of the Nb by anodization.

(3)そして該フオトレジスト43をアセトンで溶解除去
したのち、試料を真空装置に設置し、5×10-4Pa以下の
真空中で約200℃の温度で30分間の加熱処理を行なつた
後、試料の表面を1.33PaのO2ガス雰囲気中で高周波スパ
ツタエツチングし、試料表面の不純物を除去した。そし
て常電導体44として、真空蒸着法により段差面を見通す
斜め方向から、厚さ約0.1μmの多結晶Si膜を形成し、
続いて超電導体電極45及び46として、真空蒸着法により
断差面が見通せない方向から、厚さ0.4μmのNb膜を形
成した。これにより第4図(c)に示すように超電導体
電極45と46を段差部において0.1μmの結合長で分離す
ることができた。
(3) Then, after dissolving and removing the photoresist 43 with acetone, the sample was set in a vacuum device and subjected to a heat treatment at a temperature of about 200 ° C. for 30 minutes in a vacuum of 5 × 10 −4 Pa or less. Thereafter, the surface of the sample was subjected to high frequency sputtering in a 1.33 Pa O 2 gas atmosphere to remove impurities on the sample surface. Then, as a normal conductor 44, a polycrystalline Si film having a thickness of about 0.1 μm is formed from an oblique direction through the step surface by a vacuum evaporation method,
Subsequently, an Nb film having a thickness of 0.4 μm was formed as the superconductor electrodes 45 and 46 from a direction in which the cross section could not be seen by a vacuum evaporation method. Thereby, as shown in FIG. 4 (c), the superconductor electrodes 45 and 46 could be separated at the step portion with a coupling length of 0.1 μm.

(4)最後にフオトレジストをマスク材とし、Arガスを
用いたイオンミリング法により、Nb超電導体電極45及び
46とSi常電導体44をエツチングして、第4図(d)に示
すような超電導トランジスタを完成した。
(4) Finally, using the photoresist as a mask material and ion milling using Ar gas, the Nb superconductor electrode 45 and
The superconducting transistor as shown in FIG. 4 (d) was completed by etching the 46 and the Si normal conductor 44.

本実施例においても実施例1と同様にジヨセフソン接
合電流の均一性,再現性を向上することができ、かつ制
御電極に200〜200mVの電圧を印加することにより、ジヨ
セフソン接合電流を0〜80μAの範囲で制御することが
できた。
In this embodiment, the uniformity and reproducibility of the Josephson junction current can be improved as in the first embodiment, and by applying a voltage of 200 to 200 mV to the control electrode, the Josephson junction current can be reduced to 0 to 80 μA. The range could be controlled.

以上本実施例は、実施例1で説明した本発明による素
子の段差材に制御電極機能を付加した新しい構造の超電
導トランジスタを提供するものである。
As described above, the present embodiment provides a superconducting transistor having a new structure in which a control electrode function is added to the step member of the device according to the present invention described in the first embodiment.

(実施例5) 前記実施例4では、制御電極をジヨセフソン素子の下
に設けた例を説明したが、この制御電極をジヨセフソン
素子の上に形成することも可能である。そこで実施例1
で説明した素子(第1図(d)に示す)上に絶縁膜を介
して制御電極を設けたが、制御電圧が大きくなるという
欠点があつた。この場合、常導電体−超電導体電極−絶
縁膜−制御電極の順に素子を構成したため、電界が導電
導体に印加されにくかつたためと考えられる。そこで、
超電導体電極−常電導体−絶縁膜−制御電極の順に素子
を構成した実施例について、第5図を用いて以下に説明
する。
Fifth Embodiment In the fourth embodiment, the example in which the control electrode is provided below the Josephson element has been described. However, the control electrode may be formed on the Josephson element. Therefore, Embodiment 1
Although the control electrode is provided on the element (shown in FIG. 1 (d)) described above with an insulating film interposed therebetween, there is a disadvantage that the control voltage is increased. In this case, it is considered that the element was configured in the order of the normal conductor, the superconductor electrode, the insulating film, and the control electrode, so that it was difficult for the electric field to be applied to the conductive conductor. Therefore,
An embodiment in which elements are formed in the order of superconductor electrode-normal conductor-insulating film-control electrode will be described below with reference to FIG.

(1)まず第5図(a)に示すようにSi基板51上に、段
差材52として厚さ0.5μmのSiO膜を形成した。
(1) First, as shown in FIG. 5 (a), a 0.5 μm thick SiO film was formed as a step member 52 on a Si substrate 51.

(2)そして、超電導体電極55及び56として、真空蒸着
法により段差面が見通せない方向から厚さ0.4μmのNb
膜を形成し、引き続いて常電導体54として、厚さ0.15μ
mの多結晶Siを段差面を見通す方向から真空蒸着法によ
り形成し、その表面を乾燥したO2ガス雰囲気中で、100
℃20分間の加熱処理により酸化し、厚さ約25nmは酸化Si
絶縁膜59を形成し、第5図(b)に示すような構造にし
た。
(2) Nb having a thickness of 0.4 μm was used as the superconductor electrodes 55 and 56 in a direction in which the step surface could not be seen by vacuum evaporation.
After forming a film, subsequently as a normal conductor 54, a thickness of 0.15μ
m of polycrystalline Si is formed by a vacuum deposition method from the direction looking through the step surface, and the surface is dried in an O 2 gas atmosphere at 100
Oxidized by heat treatment at ℃ 20 minutes, about 25 nm thick silicon oxide
An insulating film 59 was formed to have a structure as shown in FIG.

(3)次いで、フオトレジストをマスク材とし、Arガス
を用いたイオンミリング法により、該酸化Si絶縁膜59、
Si常電導体54、Nb超電導電極55及び56をエツチングして
素子パターンを形成したのち、同じくイオンミリング法
により、断差部以外の該酸化Si絶縁膜59とSi常電導体54
のみをエツチングして、第5図(c)に示すような構造
にした。
(3) Next, using the photoresist as a mask material, the silicon oxide insulating film 59 is formed by ion milling using Ar gas.
After etching the Si normal conductor 54 and the Nb superconducting electrodes 55 and 56 to form an element pattern, the ion-milling method also uses the Si oxide insulating film 59 and the Si normal conductor 54 except for the cut portion.
Only this was etched to obtain a structure as shown in FIG. 5 (c).

(4)そして第5図(d)に示すように、真空蒸着法に
より厚さ0.7μmのSiO層間絶縁膜60を形成し、さらに該
酸化Si絶縁膜59上に制御電極58として、厚さ1.0μmのP
b−In蒸着膜を形成して、超電導トランジスタを完成し
た。
(4) Then, as shown in FIG. 5 (d), an SiO interlayer insulating film 60 having a thickness of 0.7 μm is formed by a vacuum evaporation method, and a control electrode 58 is formed on the Si oxide insulating film 59 as a control electrode 58 having a thickness of 1.0 μm. μm P
A superconducting transistor was completed by forming a b-In deposited film.

本実施例においても実施例4と同様に、制御電極に電
圧を印加することによりジヨセフソン接合電流を制御す
ることができた。
In this embodiment, similarly to the fourth embodiment, the Josephson junction current could be controlled by applying a voltage to the control electrode.

以上の実施例1〜5においては、超電導電極にNbを用
いたが、このほかにNbN,Nb3Al,Nb3Ge等のNb化合物、Pb
−In,Pb−Bi,Pb−Au−In等のPb合金、あるいはMoNなど
を用いることができることは言うまでもない。常電導体
材料については、Cu,Siの例で説明したが、Al,Ge,GaAs,
InP,InAs,InSb,GaSb,GaPなどを用いた場合でも同様の効
果を得ることができた。
In Examples 1 to 5 above, was used with Nb superconducting electrodes, NbN Besides this, Nb 3 Al, Nb compound such as Nb 3 Ge, Pb
Needless to say, a Pb alloy such as -In, Pb-Bi, Pb-Au-In, or MoN can be used. As for the normal conductor material, the example of Cu, Si has been described, but Al, Ge, GaAs,
Similar effects were obtained when InP, InAs, InSb, GaSb, GaP, etc. were used.

以下、実施例6〜7を用いて本発明を詳細に説明す
る。
Hereinafter, the present invention will be described in detail using Examples 6 and 7.

(実施例6) (1)まず直径2インチのSi基板111上に、厚さ200nmの
Nb膜を直流マグネトロンスパツタ法により形成し、この
上にフオトレジスト(ヘキスト(Hoechst)社製,商品
名:AZ−1350J)で第1の超電導体電極パターンを光露光
法により形成した。そしてこのフオトレジストをマスク
材とし、CF4とO2の混合ガスを用いた反応性プラズマエ
ツチング法により、該Nb膜をエツチングして第7図
(a)に示すような第1のNb超電導体電極112を形成し
た。
(Example 6) (1) First, a 200-nm-thick Si substrate 111 having a thickness of 2
An Nb film was formed by a DC magnetron sputter method, and a first superconductor electrode pattern was formed on the Nb film by a light exposure method using a photoresist (trade name: AZ-1350J, manufactured by Hoechst). The photoresist is used as a mask material, and the Nb film is etched by a reactive plasma etching method using a mixed gas of CF 4 and O 2 to form a first Nb superconductor as shown in FIG. An electrode 112 was formed.

(2)次にArガスを用いた高周波スパツタクリーニング
法により、該Nb超電導体電極112の表面を清浄化処理し
たのち、真空蒸着法により常電導体113として厚さ50nm
のSi膜を形成した(第7図(b))。このSiは本発明の
弱結合型ジヨセフソン素子が動作する極低温において、
アクセプタあるいはドナーがフリーズ・アウトする程
度、すなわち1×1024m-3以下の不純物濃度にした。な
おこの蒸着では水晶振動子式膜厚計を用いて蒸着膜厚を
制御した。
(2) Next, after cleaning the surface of the Nb superconductor electrode 112 by a high-frequency sputter cleaning method using Ar gas, the thickness of the normal conductor 113 is reduced to 50 nm by a vacuum deposition method.
(FIG. 7 (b)). At this cryogenic temperature at which the weakly-coupled Josephson device of the present invention operates,
The impurity concentration was set so as to freeze out the acceptor or the donor, that is, 1 × 10 24 m −3 or less. In this deposition, the thickness of the deposited film was controlled by using a quartz crystal film thickness meter.

(3)そしてフオトレジスト(該AZ−1350J)114を用い
て該Si膜の弱結合部を被覆したのち、O2ガスを用いた高
周波プラズマ酸化法により、露出した該Si膜表面を酸化
して、厚さが約5nm以上のSiOx絶縁体層115を形成し(第
7図(c))、該フオトレジストをアセトンで溶解除去
した。
(3) After coating the weakly bonded portion of the Si film with a photoresist (the AZ-1350J) 114, the exposed surface of the Si film is oxidized by a high-frequency plasma oxidation method using O 2 gas. Then, a SiOx insulator layer 115 having a thickness of about 5 nm or more was formed (FIG. 7C), and the photoresist was dissolved and removed with acetone.

(4)次にArガスを用いた高周波スパツタクリーニング
法により、該Si常電導体113の弱結合部およびSiOx絶縁
体層115の表面を清浄化処理したのち、厚さ200nmのNb膜
を直流マグネトロンスパツタ法により形成した(第7図
(d))。そして該フオトレジストを用いて第2の超電
導体電極パターンを形成し、CF4を用いた反応性プラズ
マエツチング法により、該Nb膜をエツチングして第2の
Nb超電導体電極116を形成し、第7図(e)に示すよう
な弱結合型ジヨセフソン素子を完成した。
(4) Next, after the weak coupling portion of the Si normal conductor 113 and the surface of the SiOx insulator layer 115 are cleaned by a high frequency sputter cleaning method using Ar gas, the Nb film having a thickness of 200 nm is subjected to direct current. It was formed by a magnetron sputter method (FIG. 7 (d)). Then, a second superconductor electrode pattern is formed using the photoresist, and the Nb film is etched by a reactive plasma etching method using CF 4 to form a second superconductor electrode pattern.
The Nb superconductor electrode 116 was formed to complete a weakly-coupled Josephson device as shown in FIG. 7 (e).

以上のような方法により、常電導体113の厚さ、すな
わち結合長を前述した50nmに加え、100nm,150nm,200nm
とした素子も作製したが、これらの寸法精度は設定値の
±2%以下で、この再現性は±5%以下と極めて良好で
あつた。この結果、従来法で基板内で約±10%以上分布
していた接合電流を±5%以下に、また試作ロツト間で
約±30%ばらついていた接合電流を±10%以下に低減で
き、素子特性の均一性と再現性を向上することができ
た。
By the method as described above, the thickness of the normal conductor 113, that is, the coupling length in addition to the aforementioned 50 nm, 100 nm, 150 nm, 200 nm
The dimensional accuracy was ± 2% or less of the set value, and the reproducibility was extremely good at ± 5% or less. As a result, it is possible to reduce the junction current, which was distributed about ± 10% or more in the substrate by the conventional method, to ± 5% or less, and to reduce the junction current, which was distributed about ± 30% between prototype lots, to ± 10% or less. The uniformity and reproducibility of the device characteristics could be improved.

(実施例7) 前述の実施例6では、一層毎に電極パターンを形成す
るため、弱結合部に残るフオトレジスト等の不純物を高
周波スパツタクリーニング法で除去し、表面を清浄化す
る工程が必要であつた。また第1の超電導体電極の段差
によつて2つの超電導体電極が短絡しないよう、第1の
超電導体電極112の断面形状を第7図に示すように台形
にする必要があり、素子間隔を狭められず、素子の高密
度化が困難であつた。そこで本発明において上記の清浄
化工程を不要とし、かつ素子を平坦化して高密度を容易
にした実施例について、第8図を用いて以下に説明す
る。
(Embodiment 7) In Embodiment 6 described above, since an electrode pattern is formed for each layer, a step of removing impurities such as photoresist remaining in the weakly bonded portion by a high frequency sputter cleaning method and cleaning the surface is necessary. It was. In order to prevent the two superconductor electrodes from being short-circuited by the step of the first superconductor electrode, the cross section of the first superconductor electrode 112 must be trapezoidal as shown in FIG. It was difficult to increase the density of the device without being narrowed. Therefore, an embodiment in which the above-described cleaning step is unnecessary in the present invention and the element is flattened to facilitate high density will be described below with reference to FIG.

(1)まず第8図(a)に示すように、Si基板121上に
第1の超電導体電極122として厚さ200nmのNbN膜を、続
いて常電導体123として厚さ100nmのSi膜、第2の超電導
体電極126として厚さ100nmのNbN膜を連続して形成し
た。ここでNbN膜は直流マグネトロンスパツタ法によ
り、Si膜は真空蒸着法により形成し、水晶振動子式膜厚
計を用いて膜厚を制御した。このように予め三層膜を連
続形成することにより、実施例6で述べた膜表面の清浄
化工程は不要となつた。
(1) First, as shown in FIG. 8A, an NbN film having a thickness of 200 nm is formed as a first superconductor electrode 122 on a Si substrate 121, and then a Si film having a thickness of 100 nm is formed as a normal conductor 123. An NbN film having a thickness of 100 nm was continuously formed as the second superconductor electrode 126. Here, the NbN film was formed by a DC magnetron sputter method, and the Si film was formed by a vacuum deposition method, and the film thickness was controlled using a quartz crystal film thickness meter. By continuously forming the three-layer film in advance in this way, the step of cleaning the film surface described in Example 6 is not required.

(2)次に該基板表面にフオトレジスト(前記AZ−1350
J)で第1の超電導体電極パターンを光露光法により形
成した。そしてこのフオトレジスト124をマスク材とし
て、CF4ガスを用いた反応性プラズマエツチング法によ
り、第8図(b)に示すように2つのNbN超電導体電極1
22,126とSiで常電導体123をエツチングした。
(2) Next, a photoresist (the AZ-1350)
In J), a first superconductor electrode pattern was formed by a light exposure method. Then, using this photoresist 124 as a mask material, the two NbN superconductor electrodes 1 were formed by a reactive plasma etching method using CF 4 gas as shown in FIG.
The ordinary conductor 123 was etched with 22,126 and Si.

(3)引き続いて該基板上に、真空蒸着法によりSiO絶
縁膜127を300nmの厚さまで形成し、該レジスト124をア
セトンで溶解し、この上に蒸着されてSiO膜を除去する
ことにより、第8図(c)に示すように常電導体123の
表面までSiO絶縁体127で埋め戻した。
(3) Subsequently, an SiO insulating film 127 is formed to a thickness of 300 nm on the substrate by a vacuum evaporation method, the resist 124 is dissolved with acetone, and the SiO film is deposited thereon to remove the SiO film. 8 As shown in FIG. 8C, the surface of the normal conductor 123 was back-filled with the SiO insulator 127.

(4)さらに該基板表面に、フオトレジスト(前記AZ−
1350J)で弱結合部のパターンを光露光法により形成し
た。そしてこのフオトレジスト128をマスク材として、C
F4ガスを用いた反応性プラズマエツチング法により、第
2のNbN超電導体電極126をエツチングしたのち、O2ガス
を用いた高周波プラズマ酸化法により、露出した該Si常
電導体123表面を酸化して、厚さが約5nm以上のSiOx絶縁
体層125を第8図(d)に示すように形成した。
(4) Further, a photoresist (the AZ-
At 1350 J), a pattern of a weakly bonded portion was formed by a light exposure method. Then, using this photoresist 128 as a mask material, C
After etching the second NbN superconductor electrode 126 by reactive plasma etching using F 4 gas, the exposed surface of the Si normal conductor 123 is oxidized by high-frequency plasma oxidation using O 2 gas. Then, an SiOx insulator layer 125 having a thickness of about 5 nm or more was formed as shown in FIG. 8 (d).

(5)次に第8図(e)に示すように、該基板上に厚さ
100nmのSiO絶縁膜129を真空蒸着法により形成した。そ
して該レジスト128をアセトンで溶解し、この上に蒸着
されたSiO膜を除去することにより、第2の超電導体電
極126表面までSiO絶縁体129で埋め、素子を平坦にし
た。
(5) Next, as shown in FIG.
A 100 nm SiO insulating film 129 was formed by a vacuum evaporation method. Then, the resist 128 was dissolved in acetone, and the SiO film deposited thereon was removed, thereby filling the surface of the second superconductor electrode 126 with the SiO insulator 129 to flatten the device.

(6)最後に厚さ150nmのNbN膜を直流マグネトロンスパ
ツタ法により形成したのち、フオトレジストをマスク材
として、CF4ガスを用いた反応性プラズマエツチング法
により該NbN膜をエツチングしてNbN超電導引出電極130
を形成し、第8図(f)に示すように平坦化した弱結合
型ジヨセフソン素子を完成した。そして実施例6と同様
に、ジヨセフソン接合電流の均一性と再現性を向上で
き、さらに実施例6と比して清浄化工程を省略し、かつ
素子構造を平坦化して高密度化を容易にした。
(6) Finally, an NbN film having a thickness of 150 nm is formed by a DC magnetron sputter method, and then the NbN film is etched by a reactive plasma etching method using CF 4 gas using a photoresist as a mask material to form an NbN superconductor. Extraction electrode 130
Was formed, and a flattened weak coupling type Josephson device was completed as shown in FIG. 8 (f). As in the case of the sixth embodiment, the uniformity and reproducibility of the Josephson junction current can be improved. Further, compared with the sixth embodiment, the cleaning step is omitted, and the element structure is flattened to facilitate the high density. .

以上実施例6〜7においては、超電導電極NbNを用い
たが、この他にNb,Nb3Ge,MoNあるいはPb−In,Pb−Bi等
のPb合金などを用いることができることは言うまでもな
い。また常電導体材料についてはSiの例で説明したが、
Al,Ge,Cuを用いても同様の効果が得られた。
Above in Examples 6-7, it was used superconducting electrodes NbN, this addition to Nb, Nb 3 Ge, MoN or Pb-an In, can of course be used, such as Pb alloy such as Pb-Bi. In addition, the normal conductor material has been described using the example of Si,
Similar effects were obtained by using Al, Ge, and Cu.

〔発明の効果〕〔The invention's effect〕

以上説明したごとく本発明による第1の素子構造の素
子、すなわち段差部で2つの超電導体電極を分離し、か
つこの段差部に配した常電導体で2つの超電導体電極を
結合した弱結合型ジヨセフソン素子では、結合長となる
段差の制御を、寸法の制御性,再現性共に優れた、真空
蒸着法等の薄膜堆積法あるいはエツチング法により行な
うことができる。従つて結合長の寸法精度を設定値の±
1%以下に、再現性を±2%以下にでき、従来の素子で
±10%以上分布していたジヨセフソン接合電流を±5%
以下に、試作ロツト間の接合電流のばらつきを従来の約
±30%から±10%以下にすることができ、素子特性の均
一性と再現性を向上できる。
As described above, an element having the first element structure according to the present invention, that is, a weakly-coupled element in which two superconductor electrodes are separated at a step and the two superconductor electrodes are connected by a normal conductor disposed at the step. In the case of the Josephson device, the step which becomes the bond length can be controlled by a thin film deposition method such as a vacuum evaporation method or an etching method which is excellent in both dimensional controllability and reproducibility. Therefore, set the dimensional accuracy of the bond length to ±
The reproducibility can be reduced to 1% or less, the reproducibility can be reduced to ± 2% or less, and the Josephson junction current distributed by ± 10% or more in the conventional device can be reduced to ± 5%.
In the following, the variation of the junction current between the prototype lots can be reduced from about ± 30% to ± 10% or less of the prior art, and the uniformity and reproducibility of the device characteristics can be improved.

本発明の第2の素子構造によれば、弱結合形ジヨセフ
ソン素子の結合長となる常電導体の膜厚の制御を、寸法
の制御性,再現性共に優れた真空蒸着法等の薄膜堆積法
により行なうことができる。従つて結合長の寸法精度,
再現性を格段に向上でき、これに依存するジヨセフソン
接合電流を、従来法で基板内で±10%以上分布していた
ものを±5%以上に、また試作ロツト間で約±30%ばら
ついていたものを±10%以下に低減することができ、素
子特性の均一性と再現性を向上できる。
According to the second element structure of the present invention, the control of the film thickness of the normal conductor, which is the coupling length of the weakly-coupled Josephson element, is performed by a thin film deposition method such as a vacuum evaporation method which is excellent in both dimensional control and reproducibility. Can be performed. Therefore, the dimensional accuracy of the bond length,
The reproducibility can be greatly improved, and the dependent Josephson junction current varies from ± 10% or more on the substrate by the conventional method to ± 5% or more, and also varies by about ± 30% between prototype lots. Can be reduced to ± 10% or less, and the uniformity and reproducibility of element characteristics can be improved.

【図面の簡単な説明】[Brief description of the drawings]

第1図〜第5図は本発明の各実施例における素子作製工
程を示す図、第6図は従来の素子構造を示す図、第7図
及び第8図は、本発明の実施例における素子作製工程を
示す図である。 11,21,21,41,51……Si基板、12,32,52……段差材、13,2
3,33,43……フオトレジスト、14,24,34,44,54,64……常
電導体、15,16,25,26,35,36,45,46,55,56,65,66……超
電導体電極、17,67……結合長、48,58……制御電極、4
9,59……絶縁膜、60……層間絶縁膜、111,121……基
板、112,116,122,126,132,136……超電導体電極、113,1
23,133……常電導体、115,125……絶縁体層、114,124,1
28……フオトレジスト、127,129……絶縁体、130……超
電導引出電極。
1 to 5 are views showing a device fabrication process in each embodiment of the present invention, FIG. 6 is a diagram showing a conventional device structure, and FIGS. 7 and 8 are devices in an embodiment of the present invention. It is a figure showing a manufacturing process. 11,21,21,41,51 …… Si substrate, 12,32,52 …… Step material, 13,2
3,33,43 …… Photoresist, 14,24,34,44,54,64 …… Normal conductor, 15,16,25,26,35,36,45,46,55,56,65,66 …… Superconductor electrode, 17,67 …… Coupling length, 48,58 …… Control electrode, 4
9,59 ... insulating film, 60 ... interlayer insulating film, 111,121 ... substrate, 112,116,122,126,132,136 ... superconductor electrode, 113,1
23,133 …… Normal conductor, 115,125 …… Insulator layer, 114,124,1
28 Photoresist, 127, 129 Insulator, 130 Superconducting extraction electrode.

Claims (1)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】基板と、該基板上の一部に形成された絶縁
膜と、該基板上に該絶縁膜に隣接して形成された第1の
超電導体電極と、該絶縁膜上に形成された第2の超電導
体電極と、該第1の超電導体電極上から該第2の超電導
体電極上にかけて形成された常電導体層と、該常電導体
層上に絶縁膜を介して形成された制御電極とを有し、上
記第1の超電導体電極と上記第2の超電導体電極とは上
記絶縁膜により形成された段差により分離され、上記常
電導体層は該段差部にて弱結合部を形成し、且つ上記制
御電極は該常電導体層の弱結合部に電界を印加するよう
に形成されていることを特徴とする弱結合型ジョセフソ
ン素子。
1. A substrate, an insulating film formed on a part of the substrate, a first superconductor electrode formed on the substrate adjacent to the insulating film, and a first superconducting electrode formed on the insulating film. A second superconductor electrode formed, a normal conductor layer formed from the first superconductor electrode to the second superconductor electrode, and an insulating film formed on the normal conductor layer via an insulating film. And the first superconductor electrode and the second superconductor electrode are separated by a step formed by the insulating film, and the normal conductor layer is weak at the step portion. A weak-coupling type Josephson device, wherein a coupling portion is formed, and the control electrode is formed so as to apply an electric field to a weak-coupling portion of the normal conductor layer.
JP62077414A 1987-04-01 1987-04-01 Weakly coupled Josephson device Expired - Lifetime JP2594934B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62077414A JP2594934B2 (en) 1987-04-01 1987-04-01 Weakly coupled Josephson device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62077414A JP2594934B2 (en) 1987-04-01 1987-04-01 Weakly coupled Josephson device

Publications (2)

Publication Number Publication Date
JPS63245972A JPS63245972A (en) 1988-10-13
JP2594934B2 true JP2594934B2 (en) 1997-03-26

Family

ID=13633278

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62077414A Expired - Lifetime JP2594934B2 (en) 1987-04-01 1987-04-01 Weakly coupled Josephson device

Country Status (1)

Country Link
JP (1) JP2594934B2 (en)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02184087A (en) * 1989-01-11 1990-07-18 Agency Of Ind Science & Technol Superconducting weakly-coupled element
JPH04206785A (en) * 1990-11-30 1992-07-28 Hitachi Ltd Superconductive three-terminal element and its manufacture
JP2989943B2 (en) * 1991-08-28 1999-12-13 株式会社東芝 Superconducting integrated circuit manufacturing method
JP2730368B2 (en) * 1991-12-10 1998-03-25 住友電気工業株式会社 Superconducting field effect element and method for producing the same
DE19608564C2 (en) * 1996-03-07 1999-09-02 Forschungszentrum Juelich Gmbh Superconductor / semiconductor / superconductor step contact

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5469973A (en) * 1977-11-15 1979-06-05 Nippon Telegr & Teleph Corp <Ntt> Weak coupling josephson device

Also Published As

Publication number Publication date
JPS63245972A (en) 1988-10-13

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