JPS63194376A - Josephson junction element - Google Patents
Josephson junction elementInfo
- Publication number
- JPS63194376A JPS63194376A JP62026449A JP2644987A JPS63194376A JP S63194376 A JPS63194376 A JP S63194376A JP 62026449 A JP62026449 A JP 62026449A JP 2644987 A JP2644987 A JP 2644987A JP S63194376 A JPS63194376 A JP S63194376A
- Authority
- JP
- Japan
- Prior art keywords
- film
- layer
- lower electrode
- deposited
- tunnel barrier
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000004888 barrier function Effects 0.000 claims abstract description 19
- 239000000758 substrate Substances 0.000 claims abstract description 19
- 239000002887 superconductor Substances 0.000 claims abstract description 11
- 239000010408 film Substances 0.000 abstract description 52
- 239000010410 layer Substances 0.000 abstract description 43
- 238000000034 method Methods 0.000 abstract description 11
- 239000012535 impurity Substances 0.000 abstract description 9
- 238000010438 heat treatment Methods 0.000 abstract description 6
- 230000000694 effects Effects 0.000 abstract description 5
- 239000011229 interlayer Substances 0.000 abstract description 5
- 239000010409 thin film Substances 0.000 abstract description 5
- 238000001020 plasma etching Methods 0.000 abstract description 4
- 229910020174 Pb-In Inorganic materials 0.000 abstract description 3
- 230000002411 adverse Effects 0.000 abstract description 3
- 229910045601 alloy Inorganic materials 0.000 abstract description 3
- 239000000956 alloy Substances 0.000 abstract description 3
- 239000011248 coating agent Substances 0.000 abstract description 2
- 238000000576 coating method Methods 0.000 abstract description 2
- 239000013078 crystal Substances 0.000 abstract description 2
- 238000009792 diffusion process Methods 0.000 abstract description 2
- 238000001704 evaporation Methods 0.000 abstract 3
- 238000003754 machining Methods 0.000 abstract 3
- 239000000463 material Substances 0.000 description 14
- 238000005530 etching Methods 0.000 description 6
- 238000001755 magnetron sputter deposition Methods 0.000 description 3
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- 238000007740 vapor deposition Methods 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000004140 cleaning Methods 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 230000006866 deterioration Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 239000007789 gas Substances 0.000 description 2
- 229910001020 Au alloy Inorganic materials 0.000 description 1
- 229910000978 Pb alloy Inorganic materials 0.000 description 1
- 229910052681 coesite Inorganic materials 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 229910052906 cristobalite Inorganic materials 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 239000003353 gold alloy Substances 0.000 description 1
- 239000001307 helium Substances 0.000 description 1
- 229910052734 helium Inorganic materials 0.000 description 1
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 229910052682 stishovite Inorganic materials 0.000 description 1
- 229910052905 tridymite Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N60/00—Superconducting devices
- H10N60/10—Junction-based devices
- H10N60/12—Josephson-effect devices
Landscapes
- Superconductor Devices And Manufacturing Methods Thereof (AREA)
Abstract
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明はジョセフソン接合素子に係り、特に。[Detailed description of the invention] [Industrial application field] The present invention relates to Josephson junction devices, and more particularly.
下部電極膜の内部応力を少なくしかつ下部電極膜中の不
純物を少なくするのに好適な構造を有するジョセフソン
接合素子に関する。The present invention relates to a Josephson junction element having a structure suitable for reducing internal stress in a lower electrode film and reducing impurities in the lower electrode film.
従来、下部電極の一部であるＮｂ膜で平坦な絶縁性基板
上に段差を作り、その上に下部電極の一部であるＮｂ膜
とトンネル障壁層と上部電極であるＮｂｉを連続して堆
積しエツチングしてＮｂ膜によって作られた段差の真上
に接合部を形成するジョセフソン接合素子の形成方法に
ついては、ジャパニーズ ジャーナル オブ アプライ
ド フィジイックス ２５ （１９８６年）第Ｌ７０頁
から第Ｌ７２頁（Ｊａｐａｎｅｓｅ Ｊｏｕｒｎａｌ
ｏｆ ＡｐｐｌｉｅｄＰｈｙｓｉｃｓ、 ２５（１９８
６）、 ＰＰ、 Ｌ７０−Ｌ７２）において論じられて
いる。Conventionally, a step is created on a flat insulating substrate using a Nb film, which is part of the lower electrode, and then the Nb film, which is part of the lower electrode, the tunnel barrier layer, and Nbi, which is the upper electrode, are successively deposited on top of the step. A method for forming a Josephson junction element in which a junction is formed directly above a step formed by a Nb film by etching is described in Japanese Journal of Applied Physics 25 (1986), pages L70 to L72. Journal
of Applied Physics, 25 (198
6), PP, L70-L72).
上記従来技術においては、ジョセフソン接合素子の下部
電極たるＮｂｇの形成は２回に分けて行っていた。すな
わち、１回目のＮｂ膜を平坦な絶縁性基板上に堆積し、
ホトレジストを用いたエツチングによって段差を作り、
さらにその上に２回目のＮｂ膜とトンネル障壁層と上部
電極たるＮｂ膜を堆積する。その後にホトレジストを用
いたエツチングを行なって、段差の部分のＮｂ膜とあと
から堆積したＮｂｇの両方からジョセフソン接合素子の
下部電極を形成していた。係る段差をＮｂ膜で形成した
場合１段差の部分の表面がホトレジスト等によって汚染
しまた表面にＮｂの酸化物が形成されるため１段差の上
に再びＮｂ膜を堆積する前にクリーニングをする必要が
ある。しかしながら、クリーニングをしても、それぞれ
Ｎｂからなる２枚の落脱間の超電導コンタクトが確実に
とれるとは限らず、また下部電極膜中に不純物が残り下
部電極膜の劣化の原因になるため、素子の構成上問題が
あった。In the above-mentioned conventional technology, the formation of Nbg, which is the lower electrode of the Josephson junction element, was performed in two steps. That is, the first Nb film is deposited on a flat insulating substrate,
Create a step by etching using photoresist,
Furthermore, a second Nb film, a tunnel barrier layer, and an Nb film serving as an upper electrode are deposited thereon. Thereafter, etching was performed using photoresist to form the lower electrode of the Josephson junction element from both the Nb film at the step portion and the Nbg deposited later. When such a step is formed using a Nb film, the surface of the step is contaminated by photoresist, etc., and Nb oxide is formed on the surface, so cleaning is required before depositing the Nb film again on the step. There is. However, even with cleaning, it is not always possible to ensure superconducting contact between the two pieces of Nb, and impurities remain in the lower electrode film, causing deterioration of the lower electrode film. There was a problem with the structure of the element.
本発明の目的は、下部電極膜の内部応力を少なくし、し
かも下部電極膜中の不純物を少なくすることができる様
なジョセフソン接合素子を提供することにある。SUMMARY OF THE INVENTION An object of the present invention is to provide a Josephson junction element in which internal stress in a lower electrode film can be reduced and impurities in the lower electrode film can be reduced.
上記目的は、段差を有する絶縁性基板を用い。 For the above purpose, an insulating substrate with steps is used.
該絶縁性基板の段差の高い部分の上に形成された第１の
超電導体層と、係る第１の超電導休店上に形成されたト
ンネル障壁層と、係るトンネル障壁層上に形成された第
２の超電導体層からなる構造を用いることにより、達成
される。A first superconductor layer formed on the high step portion of the insulating substrate, a tunnel barrier layer formed on the first superconducting break, and a first superconductor layer formed on the tunnel barrier layer. This is achieved by using a structure consisting of two superconductor layers.
第１の超電導体層をＮｂ１ｌｉとした場合についてに下
部電極形成のためにエツチングを行なうと。When the first superconductor layer is made of Nb1li, etching is performed to form the lower electrode.
Ｎｂ膜の内部応力が開放された結果、トンネル障壁層等
の構造変化が起こりジョセフソン接合としてサブギャッ
プ領域のリーク電流が増加する。As a result of the internal stress in the Nb film being released, structural changes occur in the tunnel barrier layer and the like, resulting in an increase in leakage current in the sub-gap region as a Josephson junction.
また、基板上にＮｂ膜で段差を作り、その段差上にＮｂ
膜とトンネル障壁層と第２の超電導体を連続して堆積し
エツチングして段差の真上に接合部を形成するジョセフ
ソン接合素子の形成方法を用いれば、内部応力の問題は
回避できるが、段差となるＮｂ膜と後に堆積したＮｂ膜
の２層のＮｂ膜から下部電極を構成するため、係る２層
のＮｂ膜の間の超電導コンタクトが確実にとれるとは限
らず、また係る２つの部分の界面の不純物が下部電極中
に拡散して下部電極劣化の原因となる。In addition, we created a step with a Nb film on the substrate, and placed Nb on the step.
The problem of internal stress can be avoided by using a Josephson junction device formation method in which the film, tunnel barrier layer, and second superconductor are sequentially deposited and etched to form a junction directly above the step. Since the lower electrode is composed of two layers of Nb films, the Nb film forming the step and the Nb film deposited later, it is not always possible to ensure superconducting contact between the two layers of Nb films, and the two parts Impurities at the interface diffuse into the lower electrode, causing deterioration of the lower electrode.
本発明では、絶縁性基板自体に段差を設け、その上に下
部電極たるＮｂ膜とトンネル障壁層と上部電極たる側２
の超電導体層を堆積し、その後にエツチングで下部電極
たるＮｂ膜のパターンを形成する。従って絶縁性基板の
段差の上ではＮｂ膜は内部応力の少ない状態で堆積され
、また下部電極膜を一度に成膜するため従来構造におけ
る２つのＮｂ膜間の超電導コンタクトや２つのＮｂ膜膜
面面不純物の問題を解決することができる。In the present invention, a step is provided on the insulating substrate itself, and a Nb film serving as a lower electrode, a tunnel barrier layer, and a side 2 serving as an upper electrode are formed on the insulating substrate itself.
A superconductor layer is deposited, and then a pattern of an Nb film serving as a lower electrode is formed by etching. Therefore, the Nb film is deposited on the step of the insulating substrate with little internal stress, and since the lower electrode film is formed at once, there is no superconducting contact between the two Nb films in the conventional structure, and the film surface of the two Nb films is The problem of surface impurities can be solved.
以下、本発明を実施例を参照して詳細に説明する。第１
図は本発明の一実施例によるジョセフソン接合素子の一
部を示す断面図である。Ｓｉ単結晶でなる基板下部層１
上に抵抗加熱蒸着法によりＳｉＯを４００ｎｍの厚さに
堆積しＣＦ４ガスを用いた反応性イオンエツチング法に
よって部分的に深さ２００ｎｍエツチングして基板上部
層２を形成した。この基板上部層２は段差部を有してお
り、この段差部は、凸状または島状をなしている。Hereinafter, the present invention will be explained in detail with reference to Examples. 1st
The figure is a cross-sectional view showing a portion of a Josephson junction device according to an embodiment of the present invention. Substrate lower layer 1 made of Si single crystal
SiO was deposited thereon to a thickness of 400 nm by resistance heating vapor deposition and partially etched to a depth of 200 nm by reactive ion etching using CF4 gas to form the substrate upper layer 2. This substrate upper layer 2 has a stepped portion, and this stepped portion has a convex shape or an island shape.
次にＲＦマグネトロンスパッタ法によりＳｉｎ。Next, the RF magnetron sputtering method was used to deposit Sin.
を５０ｎｍの厚さに堆積し、被覆用絶縁膜３とした。真
空を破ることなくＤＣマグネトロンスパッタ法によりＮ
ｂ膜を膜厚２００ｎｍ、ＡＩ２膜を膜厚３ｎｍに堆積し
０ 、３ Ｔｏｒｒの０２ガスによってＡＱ膜を酸化し
た後、再びＤＣマグネトロンスパッタ法によりＮｂ膜を
膜厚１１００ｎに堆積し、反応性イオンエツチング法に
よって加工して下部電極４とトンネル障壁層５を形成し
た。この下部電極４とトンネル障壁層５は、基板上部層
２の凸状の段差部上に形成されている。再び反応性イオ
ンエツチング法によって加工して上部電極６を形成した
。次に抵抗加熱蒸着法によりＳｉ膜を厚さ４５０ｎｍに
堆積しりフトオフ法によって加工して層間絶縁膜７を形
成した。最後に抵抗加熱蒸着法によりＰｂ−Ｉｎ合金膜
を膜厚４００ｎｍに堆積しリフトオフ法によって加工し
て超電導！ｉ！線層８とした。以上によって本実施例の
ジョセフソン接合素子を形成した。was deposited to a thickness of 50 nm to form a covering insulating film 3. N by DC magnetron sputtering without breaking the vacuum.
After depositing the B film to a thickness of 200 nm and the AI2 film to a thickness of 3 nm, and oxidizing the AQ film with 02 gas at 0 and 3 Torr, a Nb film was deposited to a thickness of 1100 nm by DC magnetron sputtering again, and reactive ions were deposited to a thickness of 1100 nm. A lower electrode 4 and a tunnel barrier layer 5 were formed by etching. The lower electrode 4 and the tunnel barrier layer 5 are formed on the convex stepped portion of the upper substrate layer 2. The upper electrode 6 was formed by processing again using the reactive ion etching method. Next, a Si film was deposited to a thickness of 450 nm using a resistance heating vapor deposition method and then processed using a lift-off method to form an interlayer insulating film 7. Finally, a Pb-In alloy film was deposited to a thickness of 400 nm using the resistance heating vapor deposition method and processed using the lift-off method to make it superconducting! i! The line layer was 8. Through the above steps, the Josephson junction element of this example was formed.
ジョセフソン接合素子の特性を表わす値として臨界電流
とサブギャップ抵抗の積Ｖｍを考えると、本実施例の素
子を液体ヘリウム温度に冷却して電流−電圧特性を測定
するとＶｍは７０ｍＶであった。これは従来のようにＮ
ｂ膜で段差を作ってその上にＮｂ／Ａｌ２Ｍ化物／Ｎｂ
のジョセフソン接合を作製した場合のＶ ｍ ” ６４
ｍ Ｖと比べても見劣りしない。従って内部応力の悪
影響は従来と同様に避けることができた。Considering the product Vm of critical current and subgap resistance as a value representing the characteristics of a Josephson junction element, when the element of this example was cooled to liquid helium temperature and the current-voltage characteristics were measured, Vm was 70 mV. This is N
Make a step with b film and add Nb/Al2M compound/Nb on top of it.
V m ” 64 when a Josephson junction is fabricated.
It is not inferior to mV. Therefore, the adverse effects of internal stress could be avoided in the same manner as in the past.
また、下部電極が２層のＮｂ膜でつくられる従来の構造
を有する素子を５００個作った場合、下部電極の２枚の
Ｎｂ膜の間の超電導コンタクトがうまくとれずに第２図
のようなＩ−Ｖ特性となったものが５個はどあった。し
かし、本実施例の素子の場合は全くなかった。また、２
５０℃で３０分間熱処理したところ、従来の構造を有す
る素子は下部電極中の不純物の効果によりギャップ電圧
が２．９ｍＶから２．７ｍＶに低下したが１本実施例の
素子では２．９ｍＶのまま一定であった。Furthermore, if 500 devices were manufactured with the conventional structure in which the lower electrode was made of two layers of Nb films, the superconducting contact between the two Nb films of the lower electrode could not be established properly, resulting in a structure as shown in Figure 2. There were 5 items with IV characteristics. However, this was not the case with the device of this example. Also, 2
When heat treated at 50°C for 30 minutes, the gap voltage of the element with the conventional structure decreased from 2.9 mV to 2.7 mV due to the effect of impurities in the lower electrode, but the gap voltage of the element of this example remained at 2.9 mV. It was constant.
本実施例においては基板上部層２の材料にＳｉ○、被覆
用絶縁膜３の材料にＳ ｘ ０２ を下部電極４の材料
にＮ、ｂ、トンネル障壁層５の材料にＡｆｌ酸化物、上
部電極６の材料にＮｂ、層間絶縁膜７の材料にＳｉ、超
電導配線層Ａ層８の材料にＰｂ−Ｉｎ合金を用いたが、
これらに替えて、基板上部Ｎ２の材料にＳｉ、ＳｉＯ□
等、被覆用絶縁膜３の材料にＳｉ、Ｓ’ｉ０等、下部電
極４の材料にＮｂＮ、Ｐｂ合金、ＭｏＮ、Ｎｂ、Ｓｉ。In this example, the material of the upper substrate layer 2 is Si○, the material of the covering insulating film 3 is S x 02, the material of the lower electrode 4 is N, b, the material of the tunnel barrier layer 5 is Afl oxide, and the material of the upper electrode is Nb was used as the material of 6, Si was used as the material of the interlayer insulating film 7, and Pb-In alloy was used as the material of the superconducting wiring layer A layer 8.
Instead of these, Si, SiO□
The material of the covering insulating film 3 is Si, S'i0, etc., and the material of the lower electrode 4 is NbN, Pb alloy, MoN, Nb, Si.
Ｎｂ、ＡＱ等、トンネル障壁層５の材料にＭｇＯ。MgO is used as the material for the tunnel barrier layer 5, such as Nb and AQ.
Ｓｉ、ＳｉＯ２等、上部電極６の材料にＮｂＮ。NbN is used as the material for the upper electrode 6, such as Si or SiO2.
ｐｂ金合金ＭｏＮ、Ｎｂ、Ｓｉ、Ｎｂ、ＡＱ等、層間絶
縁膜７の材料にＳｉ○、Ｓｉｎ、等、超電４配ｍ！！１
８ ノ材料ニＮ ｂ 、 Ｎ ｂ Ｎ、 Ｍ ｏ Ｎ。PB gold alloy MoN, Nb, Si, Nb, AQ, etc., the material of the interlayer insulating film 7 is Si○, Sin, etc., superelectric 4 m! ! 1
8 Materials d N b , N b N, M o N.
Ｎｂ、Ｓｉ、Ｎｂ、ＡＱ等を用いてもよい。Nb, Si, Nb, AQ, etc. may also be used.
本発明によれば、ジョセフソン接合素子の下部電極に用
いる超電導薄膜を内部応力の少ない状態で堆積しトンネ
ル障壁層に悪影響を及ぼさないようにするという利点を
そのまま生かしつつ、従来構造のジョセフソン接合素子
の欠点であった下部電極の２つの超電導薄膜間の超電導
コンタクトの問題や係る２つの超電導薄膜の薄膜界面に
存在する不純物の拡散の問題を解決し、高品質な下部電
極及びトンネル障壁層を有し熱的安定性も大きいジョセ
フソン接合素子を得ることができる。According to the present invention, the superconducting thin film used for the lower electrode of the Josephson junction element is deposited in a state with little internal stress and does not adversely affect the tunnel barrier layer. By solving the problem of superconducting contact between the two superconducting thin films of the lower electrode and the diffusion of impurities existing at the thin film interface of the two superconducting thin films, which were drawbacks of the device, we were able to create a high-quality lower electrode and tunnel barrier layer. It is possible to obtain a Josephson junction element with high thermal stability.
第１図は本発明の一実施例によるジョセフソン接合素子
の構造を示す断面図、第２図は、従来構造のジョセフソ
ン接合素子の電流−電圧特性の一例を示す。
１・・・基板下部層、２・・・基板上部層、３・・・被
覆用絶縁膜、４・・・下部電極、５・・・トンネル障壁
層、６・・・上部電極、７・・・層間絶縁膜、８・・・
超電導配線層。FIG. 1 is a sectional view showing the structure of a Josephson junction device according to an embodiment of the present invention, and FIG. 2 shows an example of current-voltage characteristics of a Josephson junction device having a conventional structure. DESCRIPTION OF SYMBOLS 1... Lower substrate layer, 2... Upper substrate layer, 3... Insulating film for coating, 4... Lower electrode, 5... Tunnel barrier layer, 6... Upper electrode, 7...・Interlayer insulating film, 8...
Superconducting wiring layer.
Claims (1)
に形成された第１の超電導体層と、前記第１の超電導体
層上に形成されたトンネル障壁層と、前記トンネル障壁
層上に形成された第２の超電導体層とを少なくとも有す
ることを特徴とするジョセフソン接合素子。1. An insulating substrate having a convex step, a first superconductor layer formed on the top of the step, a tunnel barrier layer formed on the first superconductor layer, and the tunnel barrier layer. a second superconductor layer formed thereon.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62026449A JPS63194376A (en) | 1987-02-09 | 1987-02-09 | Josephson junction element |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62026449A JPS63194376A (en) | 1987-02-09 | 1987-02-09 | Josephson junction element |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63194376A true JPS63194376A (en) | 1988-08-11 |
Family
ID=12193810
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62026449A Pending JPS63194376A (en) | 1987-02-09 | 1987-02-09 | Josephson junction element |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63194376A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2018017372A1 (en) * | 2016-07-20 | 2018-01-25 | Microsoft Technology Licensing, Llc | Superconducting device with stress reducing dummy elements |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61271877A (en) * | 1985-05-27 | 1986-12-02 | Agency Of Ind Science & Technol | Manufacture of josephson element |
| JPS61272981A (en) * | 1985-05-29 | 1986-12-03 | Fujitsu Ltd | Manufacture of josephson device |
-
1987
- 1987-02-09 JP JP62026449A patent/JPS63194376A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61271877A (en) * | 1985-05-27 | 1986-12-02 | Agency Of Ind Science & Technol | Manufacture of josephson element |
| JPS61272981A (en) * | 1985-05-29 | 1986-12-03 | Fujitsu Ltd | Manufacture of josephson device |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2018017372A1 (en) * | 2016-07-20 | 2018-01-25 | Microsoft Technology Licensing, Llc | Superconducting device with stress reducing dummy elements |
| US10291231B2 (en) | 2016-07-20 | 2019-05-14 | Microsoft Technology Licensing, Llc | Superconducting device with dummy elements |
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