JPS61289670A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS61289670A
JPS61289670A JP13080285A JP13080285A JPS61289670A JP S61289670 A JPS61289670 A JP S61289670A JP 13080285 A JP13080285 A JP 13080285A JP 13080285 A JP13080285 A JP 13080285A JP S61289670 A JPS61289670 A JP S61289670A
Authority
JP
Japan
Prior art keywords
semiconductor substrate
substrate
main surface
oxide film
manufacturing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13080285A
Other languages
Japanese (ja)
Inventor
Norihiko Tsuchiya
憲彦 土屋
Yuichi Mikata
見方 裕一
Toshiro Usami
俊郎 宇佐美
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP13080285A priority Critical patent/JPS61289670A/en
Publication of JPS61289670A publication Critical patent/JPS61289670A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To obtain a stable threshold voltage by a method wherein working upon a semiconductor substrate and transfer of the semiconductor substrate between processes are carried out without exposing the main surface of the semiconductor substrate to the open air containing oxygen. CONSTITUTION:After donors are introduced into the surface layer of a semi- insulating GaAs substrate 1 to form an N-type layer 2, donors are implanted selectively to form an N<+> type source region 3 and an N<+> type drain region 4 by diffusion. The substrate is subjected to heat dissociation in a vacuum apparatus to remove a natural oxide film on the main surface of the substrate and an As beam is applied. Tungsten/aluminum is evaporated on the substrate 1 and a photoresist 11 is applied and Schottky gate electrode 5 is formed. Then, while the vacuum being maintained, the resist 11 is removed and a silicon oxide film is formed as a layer insulation film 6. After contact holes 7 are drilled in the layer insulation film 6, gold/germanium alloy films are evaporated to form a source electrode 8 and a drain electrode 9 which are brought into ohmic contact with the source region 3 and the drain region 4 respectively. With this constitution, a threshold voltage can be controlled at the stable and well reproducible value.

Description

【発明の詳細な説明】 [発明の技術分野] 本発明は、ショットキー障壁電界効果型トランジスタを
具備する半導体装置の製造方法に関し、特に不純物拡散
工程以後の電極等の形成工程を改良し、安定したしきい
値電圧が得られる半導体装置の製造方法に係るものであ
る。
Detailed Description of the Invention [Technical Field of the Invention] The present invention relates to a method for manufacturing a semiconductor device equipped with a Schottky barrier field effect transistor, and in particular improves the process of forming electrodes etc. after the impurity diffusion process to improve stability. The present invention relates to a method of manufacturing a semiconductor device that can obtain a threshold voltage of 100%.

[発明の技術的背it] ショットキー障壁電界効果型トランジスタ(MES  
FETと略記する)が形成された半導体装置とその従来
の製造方法について第2図を参照して説明する。 Cr
等をドープした半絶縁性GaAs基板1にドナーをイオ
ン注入してN型層2を形成する。 更に選択的にイオン
注入して、N+型[13及び4を形成する。 次にこの
表面にショットキー障壁を形成する金属膜を接合し、ホ
[Technical background of the invention] Schottky barrier field effect transistor (MES)
A semiconductor device in which a FET (abbreviated as FET) is formed and a conventional manufacturing method thereof will be described with reference to FIG. Cr
An N-type layer 2 is formed by ion-implanting a donor into a semi-insulating GaAs substrate 1 doped with . Furthermore, selective ion implantation is performed to form N+ type [13 and 4]. Next, a metal film forming a Schottky barrier is bonded to this surface.

トリソグラフィによりゲート電極5を加工する。The gate electrode 5 is processed by lithography.

CVD  S i O,膜を層間絶縁II6として形成
後、コンタクトホール7を開孔し、Au Ge合金膜を
蒸着し、アンニールしてソース電極8及びドレイン電極
9のオーミック接触を形成する。 この上に例えばアル
ミニウム等の配線用金属膜10を形成してMES  F
ETを製造する。 MES  FETでは周知のように
ゲート電極と基板面との間にショットキー障壁が形成さ
れ、この障壁6性質がMES  FETの特性に大きな
影響を持つ。
After forming a CVD SiO film as interlayer insulation II6, a contact hole 7 is opened, an AuGe alloy film is deposited, and annealed to form an ohmic contact between a source electrode 8 and a drain electrode 9. A metal film 10 for wiring such as aluminum is formed on this, and the MES F
Manufacture ET. As is well known in the MES FET, a Schottky barrier is formed between the gate electrode and the substrate surface, and the properties of this barrier 6 have a great influence on the characteristics of the MES FET.

[背景技術の問題点] MES  FETにおいては、上述の如くゲート電極と
半導体基板との界面の状態は特性を左右する大きな要因
である。 従来の製造方法では界面の安定性が悪く、多
くの好ましくない界面単位が存在する。 その結果第1
にショットキー障壁の電位が不安定且つ再現性の悪い値
をとる。 第2にゲート、ソース閤及びゲート、ドレイ
ン間に制w縫囲を越えた空乏層の拡張が起こり十分な電
流が確保できなくなる。 第3にソース電極及びドレイ
ン電極と基板との界面でのオーミック接触による抵抗値
のばらつきが大きくなる。 以上の結果、しきい値電圧
はばらつきの大きな値をとり回路を制御性よく形成する
ことができず、性能及び歩留りの低下を招いている。
[Problems of Background Art] As described above, the state of the interface between the gate electrode and the semiconductor substrate is a major factor that influences the characteristics of MES FETs. In conventional manufacturing methods, the interfacial stability is poor and many undesirable interfacial units are present. As a result, the first
The potential of the Schottky barrier takes values that are unstable and have poor reproducibility. Secondly, the depletion layer between the gate and the source and between the gate and the drain expands beyond the current limit, making it impossible to secure a sufficient current. Thirdly, variations in resistance value due to ohmic contact at the interface between the source electrode and the drain electrode and the substrate become large. As a result of the above, the threshold voltage has a large variation, making it impossible to form a circuit with good controllability, resulting in a decrease in performance and yield.

[発明の目的] 本発明の目的は、MES  FETにおいて前記問題点
を解決し、安定したしきいiI!!圧が得られ、且つソ
ース及びドレイン電極のオーミック接触抵抗値のばらつ
きの少ない半導体装置の製造方法を提供することである
[Object of the Invention] An object of the present invention is to solve the above-mentioned problems in a MES FET and to provide a stable threshold II! ! It is an object of the present invention to provide a method for manufacturing a semiconductor device in which high pressure is obtained and there is little variation in ohmic contact resistance values of source and drain electrodes.

[発明の概要I MES  FETにおける前記問題点発生の主たる原因
の1つは、その製造過程で基板表面に自然酸化膜が形成
され、この酸化膜がゲート電極等と基板との界面に介在
し、不特定の界面単位ができるためという知見が得られ
た。 従って本発明は、基板表面の自然酸化膜を除去し
、それ以模の工程で自然酸化膜の形成防止を計った製造
方法である。
[Summary of the Invention I One of the main causes of the above problems in MES FETs is that a natural oxide film is formed on the substrate surface during the manufacturing process, and this oxide film is interposed at the interface between the gate electrode etc. and the substrate. We found that this is due to the formation of unspecified interfacial units. Therefore, the present invention is a manufacturing method that removes the natural oxide film on the substrate surface and prevents the formation of the natural oxide film in subsequent steps.

なお自然酸化膜とは、製造過程において半導体基板表面
の露出した部分に酸素を含む外気が触れ、意図しないの
に形成される酸化膜である。
Note that the natural oxide film is an oxide film that is unintentionally formed when outside air containing oxygen comes into contact with the exposed portion of the surface of the semiconductor substrate during the manufacturing process.

即ち本発明は、半導体基板の一主面にショットキー障壁
電界効果トランジスタが形成される半導体装置の製造に
おいて、前記半導体基板主面にゲート電極、ソース電極
及びドレイン電極形成前に、前記半導体基板主面の自然
酸化膜の除去を行ない、この自然酸化膜除去工程以後ゲ
ート電極、層間絶縁膜、ソース電極及びドレイン電極に
よって半導体基板主面の全面が被覆されるまでの間にお
いては、前記半導体基板主面を酸素を含む外気にさらす
ことなく、前記半導体基板上の加工(準備作業を含む)
及び前記半導体基板の工程間の転送を行なうことを特徴
とする半導体装置の製造方法である。
That is, in manufacturing a semiconductor device in which a Schottky barrier field effect transistor is formed on one main surface of a semiconductor substrate, the present invention provides a method for manufacturing a semiconductor device in which a Schottky barrier field effect transistor is formed on one main surface of the semiconductor substrate. After removing the natural oxide film on the surface, until the entire main surface of the semiconductor substrate is covered with the gate electrode, interlayer insulating film, source electrode, and drain electrode, the main surface of the semiconductor substrate is removed. Processing (including preparatory work) on the semiconductor substrate without exposing the surface to outside air containing oxygen
and a method for manufacturing a semiconductor device, characterized in that the semiconductor substrate is transferred between processes.

半導体基板がGaAsからなる基板の場合には、本発明
の適用は特に望ましい。 また半導体基板表面の自然酸
化膜を除去する手段は種々あるが、基板を真空中で加熱
するか或いは基板面にガスイオン等の荷電粒子を当てて
除去するのが望ましい実施態様である。
Application of the present invention is particularly desirable when the semiconductor substrate is made of GaAs. Although there are various methods for removing the natural oxide film on the surface of a semiconductor substrate, it is preferable to heat the substrate in vacuum or to remove it by applying charged particles such as gas ions to the substrate surface.

[発明の実施例] 以下本発明の実施例としてGaAs1板を使用したME
S  FETの製造方法について図面に基づき説明する
。 第2図は、半絶縁性のGaAs半導体基板にショッ
トキー障壁電界効果型トランジスタ(MES  FET
)が形成された半導体装置のトランジスタ部分の断面図
である。 このMES  FETの構成は従来のMES
  FETと同様で前述の通りであるが、その製造方法
が異なる。
[Embodiments of the invention] The following is an example of an ME using a GaAs board as an example of the present invention.
A method for manufacturing an S FET will be explained based on the drawings. Figure 2 shows a Schottky barrier field effect transistor (MES FET) on a semi-insulating GaAs semiconductor substrate.
) is a cross-sectional view of a transistor portion of a semiconductor device in which a semiconductor device is formed. The configuration of this MES FET is similar to that of conventional MES
Although it is similar to the FET and as described above, the manufacturing method is different.

第1図(A)ないしくE)は本発明の製造工程を素子断
面図で示したものである。 第1図(A>は、GaAs
半導体基板主面にゲート電極、ソース1!極及びドレイ
ン電極を形成する前の状態を示すものである。 即ちC
「をドープした半絶縁性GaAs基板1の表面層にイオ
ン注入法によりドナーを導入してN型Fm2を形成した
後、更に選択的にドナーを注入してN4型のソース領域
3及びドレイン領域4を拡散形成したものである。 次
に同図(B)に示すようにこの基板を真空装置内にて6
50℃で加熱解離することにより基板主面(表面)の自
然酸化膜を除去する。 このwA基板主面の荒れを防ぐ
ためAsのビームを照射する。
FIGS. 1(A) to 1(E) show the manufacturing process of the present invention in cross-sectional views of the device. Figure 1 (A> is GaAs
Gate electrode and source 1 on the main surface of the semiconductor substrate! This shows the state before forming the pole and drain electrodes. That is, C
Donors are introduced into the surface layer of the semi-insulating GaAs substrate 1 doped with ion implantation to form N-type Fm2, and then donors are further selectively implanted to form N4-type source regions 3 and drain regions 4. Next, as shown in the same figure (B), this substrate was 6
The natural oxide film on the main surface (front surface) of the substrate is removed by thermal dissociation at 50°C. In order to prevent the main surface of the wA substrate from becoming rough, an As beam is irradiated.

同図(C)は前記自然酸化膜除去工程を終えた基板1上
にゲート電極5を形成した状態を示す。
FIG. 1C shows a state in which a gate electrode 5 is formed on the substrate 1 after the natural oxide film removal process.

即ち同図(B)の工程に引続いて真空を保持した状態で
、前記基板1の上にタングステンアルミニウムを蒸着し
、次にホトレジスト11を塗布し周知のホトリソグラフ
ィによりショットキーゲート電極5を加工する。 次に
同図(D)に示すように更に真空を保ったままレジスト
11を除去し、CVD法によるシリコン酸化膜を層間絶
縁106として形成する。 次に同図(E)に示すよう
に層間絶縁膜6にホトリソグラフィでコンタクトホール
7を開孔した後、金・ゲルマニウム合金膜を蒸着してソ
ース電極8及びドレイン電極9を形成し、ソース領域3
及びドレイン領域4のそれぞれとオーミック接触を行な
う。
That is, following the process shown in FIG. 2B, tungsten aluminum is deposited on the substrate 1 while maintaining a vacuum, and then a photoresist 11 is applied and a Schottky gate electrode 5 is processed by well-known photolithography. do. Next, as shown in FIG. 4D, the resist 11 is removed while maintaining the vacuum, and a silicon oxide film is formed as an interlayer insulator 106 by CVD. Next, as shown in FIG. 6(E), a contact hole 7 is formed in the interlayer insulating film 6 by photolithography, and then a gold/germanium alloy film is deposited to form a source electrode 8 and a drain electrode 9, and a source electrode 8 and a drain electrode 9 are formed. 3
and the drain region 4, respectively.

本発明では、第1図(B)に示す自然酸化膜除去工程以
後、同図(E)に示すソース電極及びドレイン電極形成
工程までの間においては半導体基板主面を酸素を含む外
気にさらすことなく基板の加工又は転送を行なわねばな
らない。 従ってこの間に使用する各種製造装置は工程
順に搬送機構を持つ気密なトンネルにより連結され、ま
た前記各種vl造装置のウェハ加工室は外気より遮断さ
れ、ウェハのロード、加工、アンロードの操作は自動化
、ロボット化される。 また前記トンネル及びウェハ加
工室は工程に必要なガスを導入する場合を除き真空に保
持されるか所望により窒素ガス等の不活性ガスで満たさ
れる。
In the present invention, the main surface of the semiconductor substrate is exposed to outside air containing oxygen between the natural oxide film removal step shown in FIG. 1(B) and the source electrode and drain electrode forming step shown in FIG. 1(E). The substrate must be processed or transferred without any problems. Therefore, the various manufacturing equipment used during this time are connected in the order of the process by an airtight tunnel with a transport mechanism, and the wafer processing chambers of the various VL manufacturing equipment are isolated from the outside air, and the loading, processing, and unloading operations of wafers are automated. , robotized. Further, the tunnel and the wafer processing chamber are kept in a vacuum except when introducing gases necessary for the process, or are filled with an inert gas such as nitrogen gas as desired.

最後に第2図に示すようにA1を蒸着しバターニングし
て配線金属層10を形成する。
Finally, as shown in FIG. 2, A1 is deposited and patterned to form a wiring metal layer 10.

なお、上記の実施例ではGaAsのMESFETについ
て述べたが半導体基板がシリコン基板であってもその他
の化合物半導体であっても差支えない。 また基板主面
の自然酸化膜の除去を真空中の加熱による解離を用いた
が、イオン化したアルゴン等の荷電粒子を基板主面に当
てるスパッタリングを用いることも可能である。 また
ショットキー電極としてシリサイド或いは白金等の純金
属を用いても可能である。
In the above embodiment, a GaAs MESFET has been described, but the semiconductor substrate may be a silicon substrate or another compound semiconductor. Further, although dissociation by heating in vacuum was used to remove the natural oxide film on the main surface of the substrate, it is also possible to use sputtering in which charged particles such as ionized argon are applied to the main surface of the substrate. It is also possible to use silicide or pure metal such as platinum as the Schottky electrode.

[発明の効果1 本発明の製造方法によるMES  FETと従来の製造
方法によるMES  FETとをそれぞれ200素子製
作して、そのしきい値電圧の分布を測定した。 ただし
1素子はゲート長1.5μm、幅10μ鴎である。 第
3図は本発明の方法によるMES  FETのしきい値
電圧の分布で、第4図は従来の方法によるMES  F
ETの分布である。
[Effects of the Invention 1 200 MES FETs were manufactured using the manufacturing method of the present invention and 200 MES FETs were manufactured using the conventional manufacturing method, and the threshold voltage distributions thereof were measured. However, one element has a gate length of 1.5 μm and a width of 10 μm. FIG. 3 shows the threshold voltage distribution of the MES FET according to the method of the present invention, and FIG. 4 shows the distribution of the threshold voltage of the MES FET according to the conventional method.
This is the distribution of ET.

従来の方法のMES  FETのしきい値電圧は140
1Vの範囲にわたっているのに対し、本発明のMES 
 FETのしきい値電圧はその1/2程度の80 mV
の範囲内にあり、安定性の増していることが確認される
The threshold voltage of conventional MES FET is 140
1 V, whereas the MES of the present invention
The threshold voltage of FET is about 1/2 of that, 80 mV.
It is confirmed that the stability is within the range of .

以上述べたように本発明の製造方法によれば、半導体基
板主面とゲート、ソース及びドレインのそれぞれの電極
と接合する界面、並びに基板主面のゲートとソース間及
びゲート・とドレイン間の自然酸化膜の形成が抑制され
た結果、しきい値電圧が安定で再現性の良い値に制御可
能となり且つソース電極及びドレイン電極のオーミック
接触抵抗値のばらつきも少なくなり、高性能の半導体装
置を高歩留りで製造できるようになった。
As described above, according to the manufacturing method of the present invention, the interfaces where the main surface of the semiconductor substrate joins with each of the gate, source, and drain electrodes, as well as the natural As a result of suppressing the formation of an oxide film, the threshold voltage can be controlled to a stable and reproducible value, and the variation in ohmic contact resistance of the source and drain electrodes is also reduced, making it possible to improve the performance of high-performance semiconductor devices. It is now possible to manufacture at a high yield.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図(A)ないしくE)は本発明の実施例の製造工程
を示す断面図、第2図は本発明及び従来の製造方法に係
る半導体@欝の断面図、第3図は本発明の製造方法によ
る半導体装置のしきいiim圧分布図、第4図は従来の
製造方法による半導体装置のしきい値電圧分布図である
。 1・・・半導体基板(半絶縁性GaAsI板)、5・・
・ゲート電極、 6・・・層間絶縁膜、 8・・・ソー
ス電極、 9・・・ドレイン電極。 第3図 しきい値電圧(mV)
1(A) to E) are cross-sectional views showing the manufacturing process of an embodiment of the present invention, FIG. 2 is a cross-sectional view of a semiconductor according to the present invention and a conventional manufacturing method, and FIG. 3 is a cross-sectional view of a semiconductor according to the present invention. FIG. 4 is a threshold voltage distribution diagram of a semiconductor device manufactured by the conventional manufacturing method. 1... Semiconductor substrate (semi-insulating GaAsI board), 5...
- Gate electrode, 6... Interlayer insulating film, 8... Source electrode, 9... Drain electrode. Figure 3 Threshold voltage (mV)

Claims (1)

【特許請求の範囲】 1 半導体基板の一主面にショットキー障壁電界効果型
トランジスタが形成される半導体装置の製造において、
前記半導体基板主面にゲート電極、ソース電極及びドレ
イン電極を形成する前に前記半導体基板主面の自然酸化
膜の除去を行ない、かつこの自然酸化膜除去工程よりゲ
ート電極形成工程、層間絶縁膜形成工程並びにソース電
極及びドレイン電極形成工程を終えるまでの間において
は、前記半導体基板主面を酸素を含む外気にさらすこと
なく、前記半導体基板上の加工及び前記半導体基板の前
記工程間の転送を行なうことを特徴とする半導体装置の
製造方法。 2 半導体基板がGaAsからなる特許請求の範囲第1
項記載の半導体装置の製造方法。 3 半導体基板を真空中で加熱して前記基板主面の自然
酸化膜を除去する特許請求の範囲第1項及び第2項記載
の半導体装置の製造方法。 4 半導体基板主面に荷電粒子を衝撃することにより前
記基板主面の自然酸化膜を除去する特許請求の範囲第1
項及び第2項記載の半導体装置の製造方法。
[Claims] 1. In manufacturing a semiconductor device in which a Schottky barrier field effect transistor is formed on one principal surface of a semiconductor substrate,
Before forming a gate electrode, a source electrode, and a drain electrode on the main surface of the semiconductor substrate, a natural oxide film on the main surface of the semiconductor substrate is removed, and from this natural oxide film removal step, a gate electrode formation step and an interlayer insulating film formation step are performed. Processing on the semiconductor substrate and transfer of the semiconductor substrate between the steps are performed without exposing the main surface of the semiconductor substrate to outside air containing oxygen until the process and the step of forming the source electrode and drain electrode are completed. A method for manufacturing a semiconductor device, characterized in that: 2 Claim 1 in which the semiconductor substrate is made of GaAs
A method for manufacturing a semiconductor device according to section 1. 3. The method of manufacturing a semiconductor device according to claims 1 and 2, wherein the semiconductor substrate is heated in a vacuum to remove a natural oxide film on the main surface of the substrate. 4. Claim 1, wherein the natural oxide film on the main surface of the semiconductor substrate is removed by bombarding the main surface of the semiconductor substrate with charged particles.
A method for manufacturing a semiconductor device according to items 1 and 2.
JP13080285A 1985-06-18 1985-06-18 Manufacture of semiconductor device Pending JPS61289670A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13080285A JPS61289670A (en) 1985-06-18 1985-06-18 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13080285A JPS61289670A (en) 1985-06-18 1985-06-18 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS61289670A true JPS61289670A (en) 1986-12-19

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
JP13080285A Pending JPS61289670A (en) 1985-06-18 1985-06-18 Manufacture of semiconductor device

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Country Link
JP (1) JPS61289670A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5229323A (en) * 1987-08-21 1993-07-20 Kabushiki Kaisha Toshiba Method for manufacturing a semiconductor device with Schottky electrodes
JP2008288289A (en) * 2007-05-16 2008-11-27 Oki Electric Ind Co Ltd Field-effect transistor and its manufacturing method

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5229323A (en) * 1987-08-21 1993-07-20 Kabushiki Kaisha Toshiba Method for manufacturing a semiconductor device with Schottky electrodes
JP2008288289A (en) * 2007-05-16 2008-11-27 Oki Electric Ind Co Ltd Field-effect transistor and its manufacturing method

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