JPS63148625A - Formation of electrode - Google Patents

Abstract

PURPOSE:To enhance a yield rate during the manufacture of a device by a method wherein, after at least one of group V elements or its compound consti tuting III-V compound semiconductors or their mixed crystals has been deposited, a heat-treatment process is executed. CONSTITUTION:Not only a combination of a GaAs substrate 11 and a tungsten silicide electrode 31 as III-V compound semiconductors, but also a Schottky electrode 21 composed of various metals for a compound such as InP, GaP or the like or a compound semiconductor multiple mixed crystal material such as GaInP, GaInAs, AlGaAs, GaInAsP or the like are doped with corresponding group V elements. By this method, the stability and uniformity of a barrier characteristic are enhanced. In addition, because an ohmic electrode metal is doped with the group V elements, the stability and reproducibility of the contact resistance are enhanced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for forming electrodes in the production of devices using ■-■ compound semiconductors or their mixed crystals.

[Conventional technology]

In recent years, m-v compound semiconductors, particularly GaAS, have attracted attention as materials for devices constituting ultrahigh-speed integrated circuits. The basic device that makes up a GaAS integrated circuit is a field-effect transistor (with a Schottky-type electrode as the gate).
MESFET), but in order to increase the density, it is necessary to adopt the well-known self-aligned gate structure.

For this purpose, it is necessary to make the Schottky-type gate electrode heat-resistant (for example, applied physics, 53
(Vol., No. 1, 1984, p. 34).

MESFETs with a self-aligned gate structure can provide a highly conductive layer between the gate electrode and the source and drain electrodes by ion implantation, reducing parasitic resistance between each electrode, making it suitable for ultra-high-speed integrated circuits. This structure is effective as a basic device.

As is well known, in the self-aligned gate structure, after placing gate electrode metal locally, high-density impurity implantation is performed using the gate electrode itself as a mask to form a high impurity concentration, low resistance layer right up to the gate. By forming
MESF that can reduce the parasitic series resistance between the gate electrode and the source or drain electrode as much as possible.
This is the electrode structure of ET. However, in order to realize the self-aligned gate structure described above, it is necessary to change the active layer due to heat treatment during the heat treatment process, which is the process of electrically activating the high-density impurity implanted layer using the gate electrode itself as a mask. Instability needs to be overcome.

(Problem to be solved by the invention) The high impurity concentration low resistance layer of MESFET with a self-aligned gate structure is made by ion implantation and then heat treatment activation. The active layer is subjected to heat treatment with gate metal made of high-melting point metal material such as tungsten silicide deposited, at which point the properties of the active layer directly under the tungsten silicide metal change, resulting in characteristic defects. As a result of the uniformity, there is a problem in that the yield of devices is significantly reduced, and a solution to this problem is desperately needed.The cause of the non-uniformity in characteristics is the reaction or mutual diffusion between the gate metal and the semiconductor crystal.

An object of the present invention is to improve the manufacturing yield of devices when a heat treatment step is included after forming an electrode, as typified by a heat-resistant gate electrode of a MESFET.

[Means for solving problems]

The electrode forming method of the present invention includes:
-V compound semiconductor or at least one group (I) element constituting a mixed crystal thereof or a compound thereof is deposited and then heat treated.

〔Example〕

Hereinafter, this invention will be explained in detail based on examples.

Here, one embodiment will be described using a MESFET manufacturing process as an example. First, a semi-insulating GaAs substrate was prepared at a ratio of 3:1:1.
After etching for 60 seconds in a mixed solution of sulfuric acid, hydrogen peroxide, and water (liquid temperature 75°C) mixed in a volume ratio of 5.
Rinse with water for 1 minute, then immerse in hydrochloric acid for 1 minute, and then soak again in hydrochloric acid for 1 minute.
After washing with water for 0 seconds, drying was performed by spraying nitrogen gas onto the surface of the GaAs substrate. After that, as shown in the cross-sectional structure of the wafer in FIG.
Ion implantation is performed to provide an impurity-introduced layer 12. This ion implantation and the subsequent first heat treatment step will be specifically explained. That is, the impurity used for ion implantation is Si, and 1
It was carried out at an accelerating voltage of 00 keV, and the implantation amount was 2×10
It was changed to "ell-". After this, a film 13 of Sin is formed on the surface of the GaAs substrate 11 to protect the impurity-introduced layer from heat treatment.
500 people were deposited and activated by heat treatment at 850° C. for 20 minutes to obtain the n-type active layer 121 shown in FIG.

At this point, as shown in FIG. 2, some of the wafers (sample A) have a GaAs substrate 11 with an Al Schottky electrode 21 of 100 μmφ ion-implanted, except for the 5in2 film 13.
120 μm concentrically with the A1 Schottky electrode 21 using vapor deposition lithography technology.
A window of φ was opened and an Au-Ge (12%) alloy electrode (ohmic electrode) 22 was placed at 350°C.

A heat treatment of about 5 minutes was added. By applying a voltage between the Al Schottky electrode 21 and the Au-Ge (12%) alloy electrode 22, the space charge layer under the key electrode 21 completely depletes the n-type operating layer 121 and becomes semi-insulating. When we investigated the fluctuation value of the voltage required to reach the characteristic GaAs substrate (hereinafter referred to as the characteristic voltage), we obtained ±17 meV over the entire wafer surface, and ±20 meV between wafers, which showed very good uniformity. It was done.

As for the remaining wafers, there are 13 SiO□ films and 3 films.
Except for this, the process of depositing the refractory gate metal is similar to the actual MESFET fabrication process. That is, as shown in FIG. 3, 3,000 tungsten silicide films 31, which are high melting point gate metals, were deposited by sputtering. However, for some wafers (sample B), a target material containing about 5 mol percent arsenic was used for the tungsten silicide sputtered film 31, and for the remaining wafers (sample C), the target material containing about 5 mol percent arsenic was used. An arsenic-free tungsten silicide target was used. After this, as shown in FIG.
Dimensions similar to those of the Schottky electrode 21 (100 μm
In φ), the tungsten silicide film 31 is left as a circular electrode of 100 μmφ using a lithography technique, and the second ion implantation process is started again.

In the second ion implantation step, 120K was used to form the n layer.
At an accelerating voltage of eV, the Si-introduced layer 41 of 2×10-2
was formed.

This second ion implantation process, although a bit extra,
The tungsten silicide 31 itself acts as an ion implantation mask, and the G under the tungsten silicide film 31 is
There is no ion implantation in the aAs-based Fi, 11, and the ion implantation process is called a self-aligned structure because there is no need for alignment. Now, after the second ion implantation for forming the n' layer, a second heat treatment activation step, which is deeply involved in the present invention, begins. In this heat treatment, a 5iOz film 42 was again deposited to protect the ion-implanted layer from heat treatment, and the treatment was carried out at 800° C. for 20 minutes to obtain the n′ layer 411 shown in FIG. After this, tungsten is again deposited using the vapor deposition lithography technique as in the case of the Al Schottky electrode 21.
An Au-Ge (12%) alloy electrode 22 is arranged with a concentric window of 120 μmφ formed with the silicide electrode 31.
A heat treatment was applied at 50° C. for about 5 minutes, and the uniformity of the characteristic voltage was examined.

As a result, for sample B, the variation over the entire wafer was ±22
meV was obtained, and the wafer-to-wafer uniformity was also within this range. This value is based on the AI Schottky electrode 2 evaluated without performing the second ion implantation and heat treatment activation process.
This is equivalent to case 1.

On the other hand, in Sample C, which uses a material that does not contain arsenic as a constituent element of the target material for the conventional tungsten silicide sputtering film, the characteristic voltage fluctuation is ±7 Qm e V over the entire wafer surface and 120 m e V between wafers.
There was a large variation in V. Therefore, although there is no problem with uniformity and reproducibility in the first ion implantation and heat treatment activation process, variations in the dark value occur in the second ion implantation and heat treatment activation process, and furthermore, the tungsten silicide sputtered film It can be seen that by using a target material containing arsenic to which 31 is attached, the variation in the dark value after the second ion implantation and heat treatment activation process is significantly reduced.

Note that there are almost no restrictions on the amount of arsenic, and the effects of the present invention described above can be obtained by including a small amount of arsenic in the electrode metal. Further, even if the arsenic in the target material exceeds 10%, the electrode metal does not contain much arsenic, and there is no excess arsenic.

By using a target material containing arsenic for the tungsten silicide sputtering film and adding arsenic to the gate metal film, the device characteristics represented by the characteristic voltage became uniform. This can be understood as the arsenic added to the gate metal film working effectively to prevent the tungsten silicide layer from reacting with GaAs and mixing arsenic into the tungsten silicide film during the second heat treatment. can.

In addition, in the above, GaAsMES is used as a specific example of the element.
Although this study was conducted assuming an FET, when a MESFET was fabricated, significant improvements in uniformity and reproducibility were observed not only in the characteristic voltage but also in leakage current between the source and drain, mutual conductance, and other characteristics. It was done.

〔Effect of the invention〕

In one embodiment of the present invention, GaAs was used as the semiconductor material and tungsten silicide was used as the electrode metal. In this example, the electrode metal tungsten
The effect of adding As to silicide is that the A constituting GaAs
This can be interpreted as being caused by the fact that s can be prevented from migrating from the GaAs substrate into the electrode metal tungsten silicide.

This means that when applied to a mixed crystal semiconductor consisting of a compound semiconductor or a combination thereof, the ohmic electrode metal or Schottky electrode material in contact with the semiconductor must contain the applicable nI-V compound semiconductor. It is expected that the uniformity and reproducibility of properties will improve by adding group elements. In fact, Ga as a III-V compound semiconductor
Not only the combination of As and tungsten silicide Schottky electrodes, but also InP, GaP and other compounds, Ga InP, Ga InAs, Aj! GaA
The stability and uniformity of the barrier properties can be improved by adding the corresponding group II elements to Schottky electrodes made of various metals for compound semiconductor multi-component mixed crystal materials such as S, Ga InAsP, or ohmic electrode metals. The stability and reproducibility of contact resistance are significantly improved by adding group (2) elements. In addition, when adapting to a mixed crystal containing two or more types of group (I) elements, even one type of group (I) element is effective.

[Brief explanation of the drawing]

FIG. 1 to FIG. 5 are all for explaining the present invention.
It shows the cross-sectional structure of a GaAs wafer at each processing stage. 11...GaAS substrate 12...Ion implantation layer 13 for forming an n-type operating layer...SiO□ film 21 for protection of ion implantation layer heat treatment 21...A1 Schottky electrode 22...Au- Ge ohmic electrode 31...Tungsten silicide electrode 41...n
Ion-implanted layer 42 for layer formation... SiO2 film 121 for protection of ion-implanted layer heat treatment... N-type operating layer 411... n° layer Agent Patent attorney Yoshi Iwasa Base diagram 1 Figure 2 Figure 3 Figure 4 Figure 5

Claims (1)

[Claims] (1) In the process of attaching electrode metal to III-V compound semiconductors or their mixed crystals, after attaching at least one type of Group V element or its compound constituting the III-V compound semiconductors or their mixed crystals. , an electrode forming method characterized by heat treatment.