JPH02262343A - Compound semiconductor device and manufacture thereof - Google Patents
Compound semiconductor device and manufacture thereofInfo
- Publication number
- JPH02262343A JPH02262343A JP8144089A JP8144089A JPH02262343A JP H02262343 A JPH02262343 A JP H02262343A JP 8144089 A JP8144089 A JP 8144089A JP 8144089 A JP8144089 A JP 8144089A JP H02262343 A JPH02262343 A JP H02262343A
- Authority
- JP
- Japan
- Prior art keywords
- compound semiconductor
- semiconductor device
- thin film
- conductive layer
- film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 150000001875 compounds Chemical class 0.000 title claims abstract description 27
- 239000004065 semiconductor Substances 0.000 title claims abstract description 24
- 238000004519 manufacturing process Methods 0.000 title claims description 9
- 239000010408 film Substances 0.000 claims abstract description 22
- 239000000758 substrate Substances 0.000 claims abstract description 14
- 239000010409 thin film Substances 0.000 claims abstract description 13
- 229910052721 tungsten Inorganic materials 0.000 claims abstract description 8
- 239000010937 tungsten Substances 0.000 claims abstract description 8
- PMHQVHHXPFUNSP-UHFFFAOYSA-M copper(1+);methylsulfanylmethane;bromide Chemical compound Br[Cu].CSC PMHQVHHXPFUNSP-UHFFFAOYSA-M 0.000 claims abstract description 7
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims abstract description 5
- 238000000034 method Methods 0.000 claims description 9
- 229910052782 aluminium Inorganic materials 0.000 claims description 6
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 6
- 238000000151 deposition Methods 0.000 claims description 6
- 238000005121 nitriding Methods 0.000 claims description 6
- 238000000059 patterning Methods 0.000 claims 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 abstract description 24
- 230000004888 barrier function Effects 0.000 abstract description 11
- 150000002500 ions Chemical class 0.000 abstract 1
- -1 tungsten nitride Chemical class 0.000 description 4
- 238000000137 annealing Methods 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 229910002601 GaN Inorganic materials 0.000 description 2
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000004891 communication Methods 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- 230000001133 acceleration Effects 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000009832 plasma treatment Methods 0.000 description 1
Landscapes
- Junction Field-Effect Transistors (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の目的〕
（産業上の利用分野）
本発明は、化合物半導体の製造方法、特にＧａＡｓ
電界効果トランジスタ（ＧａＡｓ ＦＥＴ）の構造及び
製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Object of the invention] (Industrial application field) The present invention relates to a method for manufacturing a compound semiconductor, particularly a GaAs
The present invention relates to the structure and manufacturing method of a field effect transistor (GaAs FET).
（従来の技術）
近年、スーパコンビエータや高周波通信用の通信機器に
は、シリコンよりも常温での電子移動度が倍から数倍高
いＧ ａ Ａ ｓ等の化合物半導体を形成母材に採用し
た高速型の電界効果トランジスタ（ＦＥＴ）が多用され
ている。このＧａＡｓＦＩＴ としては、絶縁ゲート
型ＦＥＴ（ＭＩＳ ＦＥＴ）と金属／ＧａＡｓ界面に生
じるショットキ障壁を利用したショットキゲート型ＦＥ
Ｔ（ＭＥＳＦＢＴ） がある。(Conventional technology) In recent years, super combinators and communication equipment for high-frequency communications have adopted compound semiconductors such as GaAs, which have an electron mobility twice to several times higher than silicon at room temperature, as a base material. High-speed field effect transistors (FETs) are often used. This GaAsFIT includes an insulated gate FET (MIS FET) and a Schottky gate FE that utilizes the Schottky barrier that occurs at the metal/GaAs interface.
There is T (MESFBT).
このうちＭＩＳＦＥＴについては、安定で良質な絶縁膜
が形成しにくいことによシその開発は非常に遅れておシ
、現在はＭＥＳＦＢＴが主流を占めている。Among these, the development of MISFETs has been extremely slow due to the difficulty of forming stable and high-quality insulating films, and currently, MESFBTs are the mainstream.
第３図に従来のＭＥＳＦＥＴの構造を示す。ＧａＡｓ基
板２１上にはｎ型導電層２２が形成されている。FIG. 3 shows the structure of a conventional MESFET. An n-type conductive layer 22 is formed on the GaAs substrate 21 .
このｎ型導電層２２上には、ｐ＋型のゲート領域２３が
形成され、更にその上には窒化タングステンからなるゲ
ート電極２４が設けられている。また、ゲート電極２４
に対して自己整合的にソース。A p+ type gate region 23 is formed on this n-type conductive layer 22, and a gate electrode 24 made of tungsten nitride is further provided thereon. In addition, the gate electrode 24
Source self-consistently against.
ドレイン２５．２６のｎ型層が形成され更にソース・ド
レイン領域２５．２６上にＡｕＧｅから成る電極が形成
されている。An n-type layer of the drain 25.26 is formed, and furthermore, an electrode made of AuGe is formed on the source/drain region 25.26.
以上の様な構造のＭＥＳＦＥＴにおいては、ショットキ
障壁の高さはＯ，Ｓ Ｖと低いため、このＭＥＳＦＥＴ
を用いてＧ ａ Ａ ｓディジタル集積回路の高速
論理回路方式として主流をなすＤｉ ｒｅｃｔ−ｃｏｕ
ｐｌｅｄＦＢＴ Ｌｏｇｉｃ （ＤＣＦＬ） を構成
する場合、動作マージンが非常に小さくなり実用上問題
があった。In the MESFET with the above structure, the height of the Schottky barrier is as low as O, SV, so this MESFET
Direct-cou, which is the mainstream high-speed logic circuit method for GaAs digital integrated circuits, uses
When configuring pledFBT Logic (DCFL), the operating margin becomes extremely small, which poses a practical problem.
（発明が解決しようとする課題）
以上の様に、従来のＧａＡｓ ＭＥＳ ＦＥＴを用いて
ＤＣＦＬ＠路を構成すると充分に大きな動作マージンが
得られず実用上問題があった。(Problems to be Solved by the Invention) As described above, when a DCFL circuit is constructed using conventional GaAs MES FETs, a sufficiently large operating margin cannot be obtained, which poses a practical problem.
本発明はこの様な課題を解決する高いシｍツキー障壁を
有するＧａＡｓ ＭＥＳＦＥＴの構造及びその製造方法
を提供することを目的とする。An object of the present invention is to provide a structure of a GaAs MESFET having a high Schittsky barrier and a method for manufacturing the same, which solves the above-mentioned problems.
（課題を解決するための手段）
本発明は、上記事情に鑑みて為されたもので、第１の発
明は、化合物半導体基板表面に形成された第１導電型の
導電層と、この第１導電型の導電層上に形成された窒化
アルミニウム薄膜と、この窒化アルミニウム薄膜上に形
成されたタングステンまたはその化合物からなる電極と
を具備したことを特徴とする化合物半導体装置を提供す
る。(Means for Solving the Problems) The present invention has been made in view of the above circumstances, and the first invention includes a conductive layer of a first conductivity type formed on the surface of a compound semiconductor substrate, Provided is a compound semiconductor device comprising an aluminum nitride thin film formed on a conductive layer of a conductive type, and an electrode made of tungsten or a compound thereof formed on the aluminum nitride thin film.
また、第２の発明は、化合物半導体上にアルミニウム薄
膜を堆積する工程と、このアルミニウムして電極を形成
する工程とを具備したことを特徴とする化合物半導体装
置の製造方法を提供する。Further, a second invention provides a method for manufacturing a compound semiconductor device, comprising the steps of depositing an aluminum thin film on a compound semiconductor, and forming an electrode using the aluminum.
（作用）
クショットキ障壁を高くすることが可能となシ、これを
用いて形成された化合物半導体装置をＤＣＦＬ回路に適
用した場合、従来と比べ大きな動作マージンが得られ集
積回路の歩留シを向上することが可能となる。(Function) It is possible to increase the Kuschottky barrier, and when a compound semiconductor device formed using this is applied to a DCFL circuit, a larger operating margin can be obtained compared to conventional ones, improving the yield of integrated circuits. It becomes possible to do so.
（実施例）
以下、本発明の実施例について図面を参照して説明する
。(Example) Hereinafter, an example of the present invention will be described with reference to the drawings.
第１図は本発明のＧａＡｓ ＭＥＳ ＦＥＴの断面図で
ある。Ｇ ａ Ａ ｓ基板１上には、５００Ａの厚さを
有するｎ型導電層２が形成されている。このｎ型溝れ、
更にその上にはＷＮｘ膜（窒化タングステン膜）よ構成
るゲート電極４が形成されている。また、このゲート電
極４をマスクにしてイオン注入を行なうことによシソー
ス・ドレイン領域５，６が形成されている。このソース
・ドレイン領域５，６上にＡ ｕ Ｇ ｅからなる電極
７，８が形成されている。FIG. 1 is a cross-sectional view of a GaAs MES FET of the present invention. On the GaAs substrate 1, an n-type conductive layer 2 having a thickness of 500A is formed. This n-type groove,
Furthermore, a gate electrode 4 made of a WNx film (tungsten nitride film) is formed thereon. Furthermore, source and drain regions 5 and 6 are formed by performing ion implantation using this gate electrode 4 as a mask. Electrodes 7 and 8 made of AuGe are formed on the source/drain regions 5 and 6.
以上の様な構造のＭＥＳＦＥＴにおいては、ショットキ
障壁はｌｅＶ以上の値が得られる。即ち、タングステン
またはその化合物の堆積によシ擬似的なＭＩＳ構造とな
シ、障壁高さとして見かけ上１ｅＶ以上の値となる。従
って、上記構造のＭＥＳＦＥＴを用いてＤＣＦＬ回路を
構成することによシ、従来の金属／ Ｇ ａ Ａ ｓ接
合を有するＦＥＴに比較して、大きな動作マージンが得
られ、集積回路の歩留シを向上することが可能となる。In the MESFET having the above structure, a Schottky barrier value of leV or more can be obtained. That is, a pseudo MIS structure is created by depositing tungsten or its compound, and the barrier height has an apparent value of 1 eV or more. Therefore, by constructing a DCFL circuit using MESFETs with the above structure, a large operating margin can be obtained compared to conventional FETs having metal/GaAs junctions, and the yield rate of integrated circuits can be reduced. It becomes possible to improve.
第２図は、本発明ＯＧａＡｓ ＭＥＳ ＦＥＴの製造工
程を示す断面図である。FIG. 2 is a cross-sectional view showing the manufacturing process of the OGaAs MES FET of the present invention.
ＧａＡｓ基板１上に、シリコンイオンを加速電圧１５Ｑ
ｋｅＶ、 ドーズ量３ Ｘ １０１２／ｃ１１４で注
入し、ｎ型導電層２を形成する。このｎ型導電層２上に
１０″Ｐａ以下の高真空中でＣＶＤ法にて厚さ３０Ａ程
度のＭ膜９を堆積する。（第２図（ａ））次に、真空を
破らずにＮ！又は、ＮＨｓガスを用いて、ｎ膜９のプラ
ズマ窒化を行ないＡＩＲ膜３を形成する。んα［３は非
単結晶状態として形成される。この際、窒化の進行はＡ
ｔ／ＧａＡｓ界面付近で止ま’） 、Ｇ ａ Ａ ｓ基
板１の窒化は、わずかしか生じない。これは、室温では
尤αの生成熱ΔＨｆは−５７，７ｋｃａｌ’ｍｏｌ
に対し、ＧａＮ （窒化ガリウム）ノ生成熱ΔＨｆは、
−２５，９ｋｃａｌ’ｍｏｌ と大きいため、紅に比
較してＧａＡｓの窒化は生じにくいからである。Silicon ions are accelerated on the GaAs substrate 1 at a voltage of 15Q.
keV and a dose of 3×1012/c114 to form an n-type conductive layer 2. On this n-type conductive layer 2, an M film 9 with a thickness of about 30A is deposited by CVD in a high vacuum of 10"Pa or less. (Fig. 2(a)) Next, an N film 9 is deposited without breaking the vacuum. !Alternatively, the n film 9 is plasma nitrided using NHs gas to form the AIR film 3.Nα[3 is formed in a non-single crystal state.At this time, the progress of nitridation is A
Since the nitridation of the GaAs substrate 1 stops near the t/GaAs interface, only a slight amount of nitridation occurs. This means that at room temperature, the heat of formation ΔHf of α is -57.7 kcal'mol
On the other hand, the heat of formation ΔHf of GaN (gallium nitride) is
This is because GaAs is less likely to be nitrided than red because of its large -25.9 kcal'mol.
よって、ＧａＡｓチャネル層に影響を与えずに制御性良
く窒化を行なうことができる。（第２図（ｂ））次に、
ＷＮｘ膜１０（窒化タングステン膜）を厚さａｏｏｏＸ
程度ＣＶＤ法によシ堆積した後、パターニングしたレジ
スト（図示せず）をマスクにしてドライエツチングによ
１）ＷＮｘ膜ｌＯ及び尤ａ膜３をパターニングしてゲー
ト電極４を形成する。Therefore, nitriding can be performed with good controllability without affecting the GaAs channel layer. (Figure 2(b)) Next,
WNx film 10 (tungsten nitride film) with thickness aoooX
After being deposited by the CVD method, 1) the WNx film 1O and the a film 3 are patterned by dry etching using a patterned resist (not shown) as a mask to form the gate electrode 4.
（第２図（Ｃ））
次にこのゲート電極４をマスクにしてシリコンのイオン
注入を加速エネルギー１００ｋｅＶ、 ドーズ量３
Ｘ Ｉ Ｑ”ｍｓ ”の条件で行なった後、ＡｓＨ，と
Ａｒ の混合ガス中で８００℃、２０分間のアニール処
理を行ない、ソース・ドレイン領域５，６を形成する。(Fig. 2 (C)) Next, using this gate electrode 4 as a mask, silicon ion implantation is performed at an acceleration energy of 100 keV and a dose of 3.
After performing the process under the conditions of X I Q "ms", annealing is performed at 800° C. for 20 minutes in a mixed gas of AsH and Ar to form source/drain regions 5 and 6.
更に、このソース・ドレイン領域上ＫＡｕＧｅから成る
電極７，８を形成することによシ、ＧａＡｓＦＥＴ が
完成する。（第２図（ｄ））以上の製造工程によυ形成
されたＧａＡｓ ＰＥＴと紅膜の堆積及び窒化の工程を
除いて形成された従来のＧａＡｓ ＦＥＴの特性を比較
したところ、実施例のＧａＡａ ＦＥＴでは、ショット
キ障壁は１．２ｅＶ程度に対し、従来例のＧａＡｓ Ｆ
ＥＴでは０．８ｅＶ程度となシ、実施例の方がＤＣＦＬ
回路等へ適用した場合、よシ大きな動作マージンが得ら
れる。Further, electrodes 7 and 8 made of KAuGe are formed on the source/drain regions to complete the GaAsFET. (Figure 2(d)) Comparing the characteristics of the GaAs PET formed by the above manufacturing process and the conventional GaAs FET formed without the red film deposition and nitriding process, it was found that the GaAs PET of the example In the FET, the Schottky barrier is about 1.2 eV, whereas the conventional GaAs FET has a Schottky barrier of about 1.2 eV.
In ET, it is about 0.8 eV, but in the example, DCFL
When applied to circuits, etc., a much larger operating margin can be obtained.
また、紅の堆積・窒化の工程の付加によってもＦＥＴ特
性の均一性は保たれ、再現性も良好であった０
なお、本発明は上記実施例に限らない。例えば、基板は
ＧａＡｓに限らず他の化合物半導体であってもよい。Ａ
ＪＬＪｌｌｉの窒化方法についても、上記実施例に限ら
ず、雰囲気としてＮ！あるいはＮ、またはＮＨ。Furthermore, even with the addition of the red deposition and nitriding steps, the uniformity of the FET characteristics was maintained and the reproducibility was also good. Note that the present invention is not limited to the above embodiments. For example, the substrate is not limited to GaAs, but may be other compound semiconductors. A
The nitriding method of JLJlli is not limited to the above example, and the atmosphere is N! Or N, or NH.
を含む混合ガスを用いてもよく、また低温のプラズマ処
理にかえて、高温処理を行なってもよい。A mixed gas containing the above may be used, and high-temperature treatment may be performed instead of low-temperature plasma treatment.
また、窒化を行なったＭ膜の上層に堆積される材料もＷ
Ｎｘに限らず、Ｗ、ＷＳｉｘ、ＷＳｉｘＮｙ、ＷＡｔな
どＷまたは、その化合物であればよい。また、ゲート電
極形成後の熱処理についてもＡｓＨ，雰囲気中でのキャ
ップレスアニール法に限らず、ｓｉｏ、 。Furthermore, the material deposited on the upper layer of the nitrided M film is also W.
The material is not limited to Nx, but may be W, such as W, WSix, WSixNy, WAt, or a compound thereof. In addition, the heat treatment after forming the gate electrode is not limited to capless annealing in an AsH atmosphere, but also sio,.
ＳｉＮ、５ｉＯＮ などを被覆膜として用いたΦヤッ
プアニール法を用いてもよい。A ΦYapp annealing method using SiN, 5iON, or the like as a coating film may also be used.
以上述べた様に、本発明によればＧａＡｓ基板上にん■
膜を形成することによシシ曹ット障壁が従来に比べて高
いＧａＡｓ ＦＥＴを得ることができる。As described above, according to the present invention,
By forming the film, it is possible to obtain a GaAs FET with a higher carbon barrier than the conventional one.
第１図は、本発明の実施例の化合物半導体装置を示す断
面図、第２図は、本発明の実施例の化合物半導体装置の
製造工程を示す断面図、第３図は、従来例の化合物半導
体装置を示す断面図である。
図において、
１・・・ＧａＡｓ基板、２・・・ｎ型導電層、３・・・
九へ膜、４・・・ゲート電極、５，６・・・ソース・ド
レイン領域、７．８・・・電極、９・・・ｎ膜、１０・
・・ＷＮｘ膜、２１・・・Ｇ ａ Ａ ｓ基板、２２・
・・ｎ型導電層、２３・・・ｐゲート領域、２４・・・
ゲート電極、２５，２６・・・ソース・ドレイン領域、
２７．２８・・・電極。
第３図
（ＮFIG. 1 is a cross-sectional view showing a compound semiconductor device according to an embodiment of the present invention, FIG. 2 is a cross-sectional view showing the manufacturing process of a compound semiconductor device according to an example of the present invention, and FIG. 3 is a cross-sectional view showing a compound semiconductor device according to an example of the present invention. FIG. 2 is a cross-sectional view showing a semiconductor device. In the figure, 1...GaAs substrate, 2...n-type conductive layer, 3...
9. Film, 4... Gate electrode, 5, 6... Source/drain region, 7.8... Electrode, 9... N film, 10.
... WNx film, 21... Ga As substrate, 22.
...n-type conductive layer, 23...p gate region, 24...
Gate electrode, 25, 26... source/drain region,
27.28...electrode. Figure 3 (N
Claims (3)
導電層と、この第１導電型の導電層上に形成された窒化
アルミニウム薄膜と、この窒化アルミニウム薄膜上に形
成されたタングステンまたはその化合物からなる電極と
を具備したことを特徴とする化合物半導体装置。(1) A first conductive type conductive layer formed on the surface of a compound semiconductor substrate, an aluminum nitride thin film formed on the first conductive type conductive layer, and a tungsten or aluminum nitride thin film formed on the aluminum nitride thin film. 1. A compound semiconductor device comprising an electrode made of a compound.
である請求項１記載の化合物半導体装置。(2) The compound semiconductor device according to claim 1, wherein the electrode is a gate electrode of a Schottky transistor.
程と、このアルミニウム薄膜を窒化する工程と、この窒
化されたアルミニウム薄膜上にタングステンまたはその
化合物からなる膜を堆積する工程と、この膜と前記窒化
されたアルミニウム薄膜をパターニングして電極を形成
する工程とを具備したことを特徴とする化合物半導体装
置の製造方法。(3) A step of depositing an aluminum thin film on a compound semiconductor, a step of nitriding this aluminum thin film, a step of depositing a film made of tungsten or its compound on this nitrided aluminum thin film, and this film and the nitriding step. 1. A method for manufacturing a compound semiconductor device, comprising the step of patterning the aluminum thin film formed to form an electrode.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8144089A JPH02262343A (en) | 1989-04-03 | 1989-04-03 | Compound semiconductor device and manufacture thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8144089A JPH02262343A (en) | 1989-04-03 | 1989-04-03 | Compound semiconductor device and manufacture thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02262343A true JPH02262343A (en) | 1990-10-25 |
Family
ID=13746455
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8144089A Pending JPH02262343A (en) | 1989-04-03 | 1989-04-03 | Compound semiconductor device and manufacture thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02262343A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2004335828A (en) * | 2003-05-09 | 2004-11-25 | Mitsubishi Electric Corp | Method for stabilizing surface and method for manufacturing semiconductor device |
-
1989
- 1989-04-03 JP JP8144089A patent/JPH02262343A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2004335828A (en) * | 2003-05-09 | 2004-11-25 | Mitsubishi Electric Corp | Method for stabilizing surface and method for manufacturing semiconductor device |
| JP4620333B2 (en) * | 2003-05-09 | 2011-01-26 | 三菱電機株式会社 | Manufacturing method of semiconductor device |
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