JPH0245332B2 - - Google Patents
Info
- Publication number
- JPH0245332B2 JPH0245332B2 JP55125149A JP12514980A JPH0245332B2 JP H0245332 B2 JPH0245332 B2 JP H0245332B2 JP 55125149 A JP55125149 A JP 55125149A JP 12514980 A JP12514980 A JP 12514980A JP H0245332 B2 JPH0245332 B2 JP H0245332B2
- Authority
- JP
- Japan
- Prior art keywords
- gaas
- film
- forming
- manufacturing
- sio
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims description 32
- 238000000034 method Methods 0.000 claims description 21
- 239000013078 crystal Substances 0.000 claims description 10
- 238000004519 manufacturing process Methods 0.000 claims description 10
- 238000005468 ion implantation Methods 0.000 claims description 7
- 238000010438 heat treatment Methods 0.000 claims description 5
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 3
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 claims description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 3
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 3
- 238000002161 passivation Methods 0.000 claims description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 14
- 238000000137 annealing Methods 0.000 description 13
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 8
- 239000000758 substrate Substances 0.000 description 6
- 229910045601 alloy Inorganic materials 0.000 description 5
- 239000000956 alloy Substances 0.000 description 5
- 229910052757 nitrogen Inorganic materials 0.000 description 4
- 238000005275 alloying Methods 0.000 description 3
- 230000029052 metamorphosis Effects 0.000 description 3
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 2
- 230000002730 additional effect Effects 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 239000002775 capsule Substances 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000001257 hydrogen Substances 0.000 description 2
- 229910052739 hydrogen Inorganic materials 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- 230000001133 acceleration Effects 0.000 description 1
- 229910052786 argon Inorganic materials 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 150000002431 hydrogen Chemical class 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 238000005979 thermal decomposition reaction Methods 0.000 description 1
- 238000007738 vacuum evaporation Methods 0.000 description 1
- 238000001947 vapour-phase growth Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
Description
本発明はシヨツトキー接触FETを含むGaAs
IC等のGaAs結晶を用いた電子デバイスの製造方
法に関するものである。
GaAs結晶を用いた電子デバイスを製造するに
際してはいくつかの熱処理工程を経なければなら
ない。例えば近年特に盛んに利用されているイオ
ン注入によつて半絶縁性GaAs基板に活性層を形
成しようとする場合、注入されたイオンを活性化
するためには、通常700℃以上での高温アニール
を必要とする。このアニールの際のGaAsの熱分
解を防ぐために、シリコン酸化膜やシリコン窒化
膜又はアルミナ膜でGaAs表面を覆つたり又適当
なAs雰囲気下でアニールしたりする方法がとら
れている。しかしGaAs表面を覆う方法はアニー
ル中にGaAs中に何らかの変成をもたらして
GaAsデバイスの特性に悪影響を及ぼすことが知
られており、また適当なAs雰囲気下でアニール
するにはそのための装置が大がかりになる等の難
点をもつている、一方これらイオン注入後のアニ
ール以外にも熱処理工程が存在する。オーミツク
電極のアロイ工程がそれである。ｎ型GaAsのオ
ーミツク電極としては例えばAu−Geを真空蒸着
後アロイする方法が用いられる。このアロイ工程
は水素中又は窒素中で500℃程度の温度で行なわ
れている。シヨツトキー接触を用いるデバイスの
シヨツトキー電極形成はこのあと行なわれるが、
本発明者はこのアロイ工程を経たあとにシヨツト
キー接触を形成すると、アロイ工程を経ない場合
に比べて、シヨツトキー接触の逆方向電流リーク
が増大する等、シヨツトキー接触特性の劣化が生
じることを見出した。この原因は、シヨツトキー
接触を形成すべきGaAs結晶表面がアロイ工程に
おける高温処理で変成するためと考えられる。
本発明は以上のような問題を解決し、オーミツ
ク電極のアロイ工程の影響を除いて優れたシヨツ
トキーゲート特性を得るようにしたGaAs−
MESFETの製造方法を提供することを目的とす
る。
本発明によるGaAs−MESFETの製造方法は、
GaAs結晶にイオン注入と熱処理により活性層を
形成した後、ソース、ドレインのオーミツク電
極、シヨツトキーゲート電極を形成する工程を含
み、オーミツク電極のアロイ工程において、As
を含む絶縁膜でGaAs結晶表面を覆うことを特徴
とする。
以下、本発明の実施例を図面を参照して説明す
る。
Crドープ半絶縁性GaAs基板１１にレジストを
マスクとして、 28Si+イオンを加速電圧250KV、
ドーズ量３×1012cm-2にてイオン注入し、さらに
加速電圧100KV、ドーズ量1.5×1012cm-2の選択２
重イオン注入を行なつた。このあとSiH4−O2−
N2系のCVD法によりGaAs基板表面にシリコン
酸化膜（SiO2膜）１３をデポジツトした。なお
この際、AsH3を同時に気相成長装置に流したの
で、このSiO2膜中にはAsが混入している。この
あと800℃にて20分間のアニール処理を窒素中で
行なつた。このアニール処理後の試料の断面を第
１図に模式的に示す。１２がイオン注入とアニー
ルにより形成された活性層である。比較のため
SiO2膜を付けずGaAs表面が露出したままの状態
でAs雰囲気中（窒素中にAsH3を導入して実現。
AsH3圧は0.1〜10Torr）にて800℃、20分間のア
ニール処理（キヤツプレスアニール）を行なつた
基板も用意した。このあと、キヤツプレスアニー
ルの基板についてはCVD法によりSiO2膜を付け
た。このときSiO2膜中にAsを含むもの（SiH4−
O2−N2系にAsH3を導入して実現）と含まないも
のを用意した。以上のように用意された試料には
下表に示すように(A)−(C)の３種類あることにな
る。
The present invention is a GaAs device containing a Schottky contact FET.
This invention relates to a method for manufacturing electronic devices such as ICs using GaAs crystals. When manufacturing electronic devices using GaAs crystals, several heat treatment steps must be performed. For example, when attempting to form an active layer on a semi-insulating GaAs substrate by ion implantation, which has been widely used in recent years, high-temperature annealing at 700°C or higher is usually required to activate the implanted ions. I need. In order to prevent thermal decomposition of GaAs during this annealing, methods are used to cover the GaAs surface with a silicon oxide film, silicon nitride film, or alumina film, or to perform annealing in a suitable As atmosphere. However, the method of covering the GaAs surface may cause some metamorphosis in the GaAs during annealing.
It is known that it has a negative effect on the characteristics of GaAs devices, and it also has the disadvantage that the equipment required for annealing in a suitable As atmosphere is large-scale. There is also a heat treatment process. This is the alloy process for ohmic electrodes. For the n-type GaAs ohmic electrode, for example, a method is used in which Au--Ge is vacuum-deposited and then alloyed. This alloying process is carried out in hydrogen or nitrogen at a temperature of about 500°C. The short-key electrode formation for devices using short-key contact occurs after this.
The inventor has discovered that when a shot key contact is formed after going through this alloy process, the short key contact characteristics deteriorate, such as an increase in reverse current leakage of the shot key contact, compared to when the alloy process is not performed. . The reason for this is thought to be that the GaAs crystal surface on which the Schottky contact should be formed is metamorphosed by high-temperature treatment in the alloying process. The present invention solves the above-mentioned problems and provides a GaAs-type semiconductor device that obtains excellent shot-key gate characteristics by eliminating the influence of the alloying process of the ohmic electrode.
The purpose is to provide a method for manufacturing MESFET. The method for manufacturing GaAs-MESFET according to the present invention is as follows:
After forming an active layer in GaAs crystal by ion implantation and heat treatment, the process includes forming source and drain ohmic electrodes and Schottky gate electrodes.
It is characterized by covering the GaAs crystal surface with an insulating film containing . Embodiments of the present invention will be described below with reference to the drawings. Using a resist as a mask on the Cr-doped semi-insulating GaAs substrate 11, 28 Si + ions were accelerated at a voltage of 250 KV .
Ion implantation was performed at a dose of 3×10 12 cm -2 , and selection 2 of an acceleration voltage of 100 KV and a dose of 1.5×10 12 cm -2
Heavy ion implantation was performed. After this, SiH 4 −O 2 −
A silicon oxide film (SiO 2 film) 13 was deposited on the surface of the GaAs substrate by N 2 -based CVD method. At this time, since AsH 3 was simultaneously flowed into the vapor phase growth apparatus, As was mixed into this SiO 2 film. Thereafter, annealing treatment was performed at 800° C. for 20 minutes in nitrogen. A cross section of the sample after this annealing treatment is schematically shown in FIG. 12 is an active layer formed by ion implantation and annealing. for comparison
The GaAs surface was exposed without a SiO 2 film in an As atmosphere (achieved by introducing AsH 3 into nitrogen).
A substrate was also prepared which was annealed at 800° C. for 20 minutes (capture press annealing) at an AsH 3 pressure of 0.1 to 10 Torr. After this, a SiO 2 film was attached to the substrate that was subjected to cathode annealing using the CVD method. At this time, the SiO 2 film containing As (SiH 4 −
(Achieved by introducing AsH 3 into the O 2 −N 2 system) and one without. There are three types of samples prepared as described above, (A) to (C), as shown in the table below.
【表】
これらの試料について以下全く同一の工程で
MESFETを作つた。まずドレイン、ソースのオ
ーミツク電極形成用にSiO2膜に窓あけを行なう。
このあとAu−Ge（Ge1％）を真空蒸着法により付
け、レジストによるリフトオフ法を用いてドレイ
ン及びソース電極１４，１５を形成した。このあ
と窒素又はアルゴン又は水素中にて、500℃、15
分間のアロイ処理を行なつた。このあと、ゲート
長1μのゲート電極形成用の窓あけを行ない、
FETのピンチオフ電圧（デブレシヨンモード動
作のとき）、スレシホールド電圧（エンハンスメ
ント動作の時）の調整を行なう必要があれば、窓
あけした部分のGaAsエツチングを行なつて、ゲ
ート電極であるAlの真空蒸着を行ない、レジス
トのリフトオフ法によりゲート電極１６を形成し
た。この時の素子断面図を第２図に示す。このよ
うにして作られたGaAs MESFETのゲートソー
ス間又はゲートドレイン間のシヨツトキー接合の
逆方向ブレイクダウン電圧は前記の表に示す試料
の違いで差が見られ、(A)では平均9.5V、(B)では
10Vと良好の特性を示したが(C)では7Vであつた。
以上によりAsを含まないSiO2膜をつけてオーミ
ツク電極のアロイ工程を行なうのに比べて、As
を含むSiO2膜を用いれば、シヨツトキー接触特
性に優れたMESFETを作ることが明らかとなつ
た。またイオン注入後のアニール処理をAs入り
SiO2膜で覆つて行うことも、キヤツプレスアニ
ールのように大掛りな装置を必要とせず、またキ
ヤツプレスアニールと比べてそれ程の特性劣化は
なく、有用であることが明らかとなつた。
このようにAsを含むSiO2膜でGaAs表面を覆て
から熱処理をすることで、GaAsの変成を十分防
止でき、その結果、GaAsデバイスの特性が向上
することがわかつた。又SiO2膜生成中の高温に
よつて生じるGaAsの変成も、AsをSiO2中に含ま
せるために導入するAs圧により防止できるとい
う付加的効果もあるといえる。
またAsを含むSiO2膜の代りに、As入りシリコ
ン窒化膜やAs入りアルミナ膜等他の絶縁膜を用
いても同様の効果を示すこともわかつた。また、
このような膜を残しておけば、GaAsのパツシベ
ーシヨン膜として使用できるという付加的効果も
あることがわかつた。
さらに本方法をMESFETを使つたGaAs集積
回路の製造工程に適用したところFETのピンチ
オフ電圧のばらつきが小さくなり、集積回路の歩
留りが向上するという効果も見出した。
以上のように本発明によれば、GaAs−
MESFETを製造するに際し、ソース、ドレイン
のオーミツク電極のアロイ工程において表面を
Asを含む絶縁膜で覆うことにより、優れたシヨ
ツトキーゲート特性を実現することができる。[Table] For these samples, the following exactly the same process is performed.
I made a MESFET. First, holes are made in the SiO 2 film to form ohmic electrodes for the drain and source.
Thereafter, Au--Ge (Ge 1%) was applied by vacuum evaporation, and drain and source electrodes 14 and 15 were formed using a resist lift-off method. After this, in nitrogen, argon or hydrogen, 500℃, 15
Alloy processing was carried out for 1 minute. After this, a window for forming a gate electrode with a gate length of 1μ is made,
If it is necessary to adjust the pinch-off voltage (when operating in depletion mode) and threshold voltage (when operating in enhancement mode) of the FET, perform GaAs etching on the open area, and A gate electrode 16 was formed using a resist lift-off method. A cross-sectional view of the element at this time is shown in FIG. The reverse breakdown voltage of the Schottky junction between the gate and source or between the gate and drain of GaAs MESFETs fabricated in this way differs among the samples shown in the table above, with an average of 9.5 V for (A) and ( In B)
It showed good characteristics at 10 V , but in (C) it was 7 V.
As a result of the above, compared to performing the alloy process of ohmic electrodes with a SiO 2 film that does not contain As, the As
It has become clear that MESFETs with excellent Schottky contact characteristics can be created by using SiO 2 films containing . In addition, the annealing process after ion implantation is performed to contain As.
It has become clear that covering with a SiO 2 film is also useful because it does not require large-scale equipment unlike capsule annealing, and there is no significant deterioration in properties compared to capsule annealing. It was found that by covering the GaAs surface with an SiO 2 film containing As in this manner and then performing heat treatment, metamorphosis of GaAs can be sufficiently prevented, and as a result, the characteristics of GaAs devices are improved. It can also be said that there is an additional effect that metamorphosis of GaAs caused by high temperatures during SiO 2 film formation can be prevented by the As pressure introduced to incorporate As into SiO 2 . It was also found that similar effects can be obtained by using other insulating films such as silicon nitride film containing As or alumina film containing As in place of the SiO 2 film containing As. Also,
It has been found that if such a film is left in place, it can be used as a passivation film for GaAs, which is an additional effect. Furthermore, when this method was applied to the manufacturing process of GaAs integrated circuits using MESFETs, it was found that the variation in pinch-off voltage of FETs was reduced, and the yield of integrated circuits was improved. As described above, according to the present invention, GaAs-
When manufacturing MESFETs, the surface of the source and drain ohmic electrodes is
By covering with an insulating film containing As, excellent Schottky gate characteristics can be achieved.
第１図および第２図はこの発明の一実施例の製
造工程を説明するための素子断面図である。
１１……半絶縁性GaAs基板、１２……活性
層、１３……As入りSiO2膜、１４……ドレイン
電極、１５……ソース電極、１６……ゲート電
極。
FIGS. 1 and 2 are cross-sectional views of an element for explaining the manufacturing process of an embodiment of the present invention. DESCRIPTION OF SYMBOLS 11... Semi-insulating GaAs substrate, 12... Active layer, 13... SiO 2 film containing As, 14... Drain electrode, 15... Source electrode, 16... Gate electrode.
Claims (1)
活性層を形成する工程と、ついでこの活性層にソ
ース・ドレインのオーミツク電極を前記GaAs結
晶全面にAsを含む絶縁膜で覆つた状態でアロイ
工程を行つて形成する工程と、この後前記絶縁膜
を除去し、露出した前記GaAs結晶表面にシヨツ
トキーゲート電極を形成する工程とを有すること
を特徴とするGaAs−MESFETの製造方法。 ２ 前記絶縁膜は、シリコン酸化膜、シリコン窒
化膜、アルミナ膜のうちから選ばれることを特徴
とする特許請求の範囲第１項記載のGaAs−
MESFETの製造方法。 ３ 前記絶縁膜は、GaAs結晶表面に残置され、
パツシベーシヨン膜として用いられることを特徴
とする特許請求の範囲第１項記載のGaAs−
MESFETの製造方法。[Claims] 1. A step of forming an active layer on the surface of the GaAs crystal by ion implantation and heat treatment, and then forming source/drain ohmic electrodes on the active layer and covering the entire surface of the GaAs crystal with an insulating film containing As. A method for manufacturing a GaAs-MESFET, comprising the steps of forming a Schottky gate electrode on the exposed GaAs crystal surface by removing the insulating film and forming a Schottky gate electrode on the exposed GaAs crystal surface. . 2. The GaAs film according to claim 1, wherein the insulating film is selected from a silicon oxide film, a silicon nitride film, and an alumina film.
MESFET manufacturing method. 3. The insulating film is left on the GaAs crystal surface,
GaAs according to claim 1, characterized in that it is used as a passivation film.
MESFET manufacturing method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP55125149A JPS5749239A (en) | 1980-09-09 | 1980-09-09 | Manufacture of gaas device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP55125149A JPS5749239A (en) | 1980-09-09 | 1980-09-09 | Manufacture of gaas device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5749239A JPS5749239A (en) | 1982-03-23 |
| JPH0245332B2 true JPH0245332B2 (en) | 1990-10-09 |
Family
ID=14903074
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP55125149A Granted JPS5749239A (en) | 1980-09-09 | 1980-09-09 | Manufacture of gaas device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5749239A (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59121833A (en) * | 1982-12-27 | 1984-07-14 | Toshiba Corp | Manufacture of semiconductor device |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5247675A (en) * | 1975-10-14 | 1977-04-15 | Matsushita Electric Ind Co Ltd | Process for production of semiconductor device |
-
1980
- 1980-09-09 JP JP55125149A patent/JPS5749239A/en active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5247675A (en) * | 1975-10-14 | 1977-04-15 | Matsushita Electric Ind Co Ltd | Process for production of semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5749239A (en) | 1982-03-23 |
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