JPS6410931B2 - - Google Patents
Info
- Publication number
- JPS6410931B2 JPS6410931B2 JP13587583A JP13587583A JPS6410931B2 JP S6410931 B2 JPS6410931 B2 JP S6410931B2 JP 13587583 A JP13587583 A JP 13587583A JP 13587583 A JP13587583 A JP 13587583A JP S6410931 B2 JPS6410931 B2 JP S6410931B2
- Authority
- JP
- Japan
- Prior art keywords
- compound semiconductor
- metal film
- mesfet
- annealing
- manufacturing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000004065 semiconductor Substances 0.000 claims description 25
- 150000001875 compounds Chemical class 0.000 claims description 16
- 238000000034 method Methods 0.000 claims description 16
- 239000000463 material Substances 0.000 claims description 14
- 238000000137 annealing Methods 0.000 claims description 12
- 239000002184 metal Substances 0.000 claims description 12
- 238000004519 manufacturing process Methods 0.000 claims description 11
- 238000000151 deposition Methods 0.000 claims description 5
- 150000002500 ions Chemical class 0.000 claims description 5
- 238000005468 ion implantation Methods 0.000 claims description 4
- 238000006243 chemical reaction Methods 0.000 claims description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 11
- 229910004298 SiO 2 Inorganic materials 0.000 description 4
- 229910045601 alloy Inorganic materials 0.000 description 4
- 239000000956 alloy Substances 0.000 description 4
- 230000004888 barrier function Effects 0.000 description 4
- 239000000758 substrate Substances 0.000 description 4
- 238000007796 conventional method Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- 238000002513 implantation Methods 0.000 description 3
- 239000012535 impurity Substances 0.000 description 3
- 239000000470 constituent Substances 0.000 description 2
- 239000007772 electrode material Substances 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 230000003213 activating effect Effects 0.000 description 1
- 230000004913 activation Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
Landscapes
- Physics & Mathematics (AREA)
- High Energy & Nuclear Physics (AREA)
- Engineering & Computer Science (AREA)
- Health & Medical Sciences (AREA)
- Toxicology (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Junction Field-Effect Transistors (AREA)
Description
【発明の詳細な説明】
本発明は半導体装置の製造方法、特にイオン注
入工程を含む半導体装置の製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of manufacturing a semiconductor device, and particularly to a method of manufacturing a semiconductor device including an ion implantation process.
半導体材料のうちでGaAs等の化合物半導体で
は、イオン注入後の活性化アニール温度工程にお
いて、加熱中に半導体構成元素のうちの一つが解
離し、半導体より抜け出すことが多い。これを防
ぐために従来よりSiO2、Si3N4等の絶縁膜をキヤ
ツプ材として半導体表面に被着し、加熱時の半導
体構成元素の抜け出しを抑える方法が採用されて
来た。 Among semiconductor materials, in compound semiconductors such as GaAs, in the activation annealing temperature step after ion implantation, one of the semiconductor constituent elements often dissociates during heating and escapes from the semiconductor. In order to prevent this, a method has conventionally been adopted in which an insulating film such as SiO 2 or Si 3 N 4 is applied as a cap material to the semiconductor surface to suppress the escape of semiconductor constituent elements during heating.
第1図a乃至fは従来のGaAsシヨツトキ障壁
ゲート電界効果トランジスタ(以下MESFETと
略称する)の製造方法を説明するための図で、主
要工程におけるMESFETの断面図である。同図
において、半絶縁性GaAs基板11にMESFET
の動作層を形成するための不純物イオンを選択注
入し、注入領域21を形成する(第1図a)。
GaAs基板11の表面にキヤツプ材としてCVD
(Chemical Vapor Deposition)法によりSiO2膜
31を被着し(第1図b)、800℃のH2雰囲気中
で20分間アニールして不純物を活性化した後、
SiO2膜31を除去する(第1図c)。22は活性
化された注入領域である。次にシヨツトキ障壁ゲ
ート電極金属としてAl膜41を被着し(第1図
d)、エツチングによりゲート電極411を残置
する(第1図e)。続いてAuGe合金、Niを順次
積層した積層金属膜を選択的に被着し、420℃の
H2雰囲気中でアニールすることによりソース電
極511、ドレイン電極512を形成し(第1図
f)、GaAs MESFETが製造される。 FIGS. 1a to 1f are diagrams for explaining a method of manufacturing a conventional GaAs shot barrier gate field effect transistor (hereinafter abbreviated as MESFET), and are cross-sectional views of the MESFET in main steps. In the same figure, a MESFET is mounted on a semi-insulating GaAs substrate 11.
Impurity ions for forming an active layer are selectively implanted to form an implanted region 21 (FIG. 1a).
CVD as a cap material on the surface of the GaAs substrate 11
After depositing a SiO 2 film 31 by (Chemical Vapor Deposition) method (Fig. 1b), and activating impurities by annealing for 20 minutes in an H 2 atmosphere at 800°C,
The SiO 2 film 31 is removed (FIG. 1c). 22 is an activated implantation region. Next, an Al film 41 is deposited as a shot barrier gate electrode metal (FIG. 1d), and the gate electrode 411 is left by etching (FIG. 1e). Next, a multilayer metal film consisting of AuGe alloy and Ni was sequentially deposited and heated at 420°C.
By annealing in an H 2 atmosphere, a source electrode 511 and a drain electrode 512 are formed (FIG. 1f), and a GaAs MESFET is manufactured.
しかしながらこの様な従来の方法は、アニール
工程のキヤツプと半導体装置の電極とをそれぞれ
別の材料を用いて形成するため、それぞれの材料
を被着する工程およびエツチングする工程が必要
であり、製造工程が煩雑となる欠点があつた。 However, in such conventional methods, the cap in the annealing process and the electrodes of the semiconductor device are formed using different materials, so a process of depositing and etching each material is required, which increases the manufacturing process. It has the disadvantage that it is complicated.
本発明の目的は、上記欠点を除去し、製造工程
が簡単で短かい半導体装置の製造方法を提供する
ことにある。 SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing a semiconductor device that eliminates the above-mentioned drawbacks and has a simple and short manufacturing process.
本発明によれば、化合物半導体にイオン注入を
行なう工程と、後工程のアニール温度以下の温度
では該化合物半導体と化学反応を起こさない金属
膜を該化合物半導体表面に被着する工程と、該金
属膜をキヤツプ材として該化合物半導体をアニー
ルして注入イオンを活性化する工程と、該金属膜
の少なくとも一部を化合物半導体装置の電極とし
て残置してそれ以外の該金属膜を除去する工程を
含むことを特徴とする化合物半導体装置の製造方
法が得られる。 According to the present invention, the steps include a step of implanting ions into a compound semiconductor, a step of depositing a metal film on the surface of the compound semiconductor that does not cause a chemical reaction with the compound semiconductor at a temperature below an annealing temperature in a subsequent step, and The method includes a step of annealing the compound semiconductor using the film as a cap material to activate implanted ions, and a step of leaving at least a portion of the metal film as an electrode of a compound semiconductor device and removing the remaining metal film. A method for manufacturing a compound semiconductor device is obtained.
次に本発明の実施例について図面を用いて説明
する。 Next, embodiments of the present invention will be described using the drawings.
第2図a乃至dは本発明の一実施例を説明する
ための図面で、GaAs MESFETの動作層をイオ
ン注入法により形成する場合の製造主要工程にお
けるMESFETの断面図である。 FIGS. 2a to 2d are drawings for explaining one embodiment of the present invention, and are cross-sectional views of the MESFET in the main manufacturing steps when the active layer of the GaAs MESFET is formed by ion implantation.
図において11は半絶縁性GaAs基板で、その
表面に動作層形成のためにSiイオンを加速電圧
70KeV、ドース量2.5×1012cm-2の条件で選択的
に注入し、注入領域21を形成する(第1図a)。
シヨツトキ障壁ゲート電極金属として、後工程の
アニール温度ではGaAsと反応しないTiW合金を
5000Åの厚さにスパツタ蒸着し(第2図b)、
TiW合金膜41をキヤツプ材として800℃のH2中
で20分間アニールし、注入不純物を活性化する。
次にSF6をエツチングガスとしてドライエツチン
グ法によりゲート電極411を残置し(第1図
c)、AuGe合金、Niを順次積層した積層金属膜
を通常のリフトオフ法により選択的に被着し、
420℃のH2中で1分間アニールすることによりソ
ース電極511、ドレイン電極512を形成し
GaAs MESFETを完成した(第1図d)。 In the figure, 11 is a semi-insulating GaAs substrate, on which Si ions are accelerated at an accelerating voltage to form an active layer.
Selective implantation is performed under conditions of 70 KeV and a dose of 2.5×10 12 cm −2 to form an implanted region 21 (FIG. 1a).
As the shot barrier gate electrode metal, a TiW alloy that does not react with GaAs at the annealing temperature in the post-process is used.
Sputter deposited to a thickness of 5000 Å (Figure 2b),
The TiW alloy film 41 is used as a cap material and annealed in H 2 at 800° C. for 20 minutes to activate the implanted impurities.
Next, a gate electrode 411 is left by a dry etching method using SF 6 as an etching gas (FIG. 1c), and a laminated metal film in which AuGe alloy and Ni are sequentially laminated is selectively deposited by a normal lift-off method.
A source electrode 511 and a drain electrode 512 are formed by annealing in H 2 at 420°C for 1 minute.
We completed a GaAs MESFET (Figure 1d).
この様な製造方法ではアニール工程のキヤツプ
材とMESFETのゲート電極材料が同一物質であ
るため、従来方法のキヤツプ材の除去工程とゲー
ト電極材料の被着工程が省略でき、工程と簡単化
と短縮が可能となり、MESFETの歩留りが向上
した。 In this manufacturing method, since the cap material in the annealing process and the MESFET gate electrode material are the same material, the cap material removal step and gate electrode material deposition step of the conventional method can be omitted, simplifying and shortening the process. has become possible, and the yield of MESFET has improved.
尚、本実施例ではアニール工程のキヤツプ材を
MESFETのゲート電極として用いる場合につい
てのみ説明したが、材料によつては他の電極とし
て用いることも可能である。またMESFET以外
の化合物半導体装置、あるいはGaAs以外の化合
物半導体材料を用いた化合物半導体装置の場合も
同様に本発明が有効であることは言うまでもな
い。 In this example, the cap material for the annealing process was
Although only the case where it is used as a gate electrode of MESFET has been described, it can also be used as other electrodes depending on the material. It goes without saying that the present invention is equally effective in the case of compound semiconductor devices other than MESFETs, or compound semiconductor devices using compound semiconductor materials other than GaAs.
第1図a及至fは従来のシヨツトキ障壁ゲート
電界効果トランジスタの製造方法を説明するため
の図で、主要工程におけるMESFETの断面図、
第2図a乃至dは本発明の実施例を説明するため
の図で、主要工程におけるMESFETの断面図で
ある。
11…半絶縁性GaAs基板、21…注入領域、
22…活性化された注入領域、31…SiO2膜、
41…シヨツトキ金属膜、411…ゲート電極、
511…ソース電極、52…ドレイン電極。
Figures 1a to 1f are diagrams for explaining the conventional method of manufacturing a short barrier gate field effect transistor, including cross-sectional views of the MESFET in the main steps;
FIGS. 2a to 2d are diagrams for explaining an embodiment of the present invention, and are cross-sectional views of a MESFET in main steps. 11... Semi-insulating GaAs substrate, 21... Injection region,
22...Activated implantation region, 31...SiO 2 film,
41... shot metal film, 411... gate electrode,
511... Source electrode, 52... Drain electrode.
Claims (1)
後工程のアニール温度以下の温度では該化合物半
導体と化学反応を起こさない金属膜を該化合物半
導体表面に被着する工程と、該金属膜をキヤツプ
材として該化合物半導体をアニールして注入イオ
ンを活性化する工程と、該金属膜の少なくとも一
部を化合物半導体装置の電極として残置してそれ
以外の該金属膜を除去する工程を含むことを特徴
とする化合物半導体装置の製造方法。1. A process of ion implantation into a compound semiconductor,
A step of depositing a metal film on the surface of the compound semiconductor that does not cause a chemical reaction with the compound semiconductor at a temperature below the annealing temperature in a subsequent step, and annealing the compound semiconductor using the metal film as a cap material to activate the implanted ions. 1. A method for manufacturing a compound semiconductor device, comprising: a step of leaving at least a part of the metal film as an electrode of the compound semiconductor device, and removing the remaining metal film.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP13587583A JPS6028229A (en) | 1983-07-27 | 1983-07-27 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP13587583A JPS6028229A (en) | 1983-07-27 | 1983-07-27 | Manufacture of semiconductor device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS6028229A JPS6028229A (en) | 1985-02-13 |
JPS6410931B2 true JPS6410931B2 (en) | 1989-02-22 |
Family
ID=15161808
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP13587583A Granted JPS6028229A (en) | 1983-07-27 | 1983-07-27 | Manufacture of semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6028229A (en) |
-
1983
- 1983-07-27 JP JP13587583A patent/JPS6028229A/en active Granted
Also Published As
Publication number | Publication date |
---|---|
JPS6028229A (en) | 1985-02-13 |
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